Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 24 | #include "gf100.h" |
| 25 | #include "ctxgf100.h" |
| 26 | #include "fuc/os.h" |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 27 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 28 | #include <core/client.h> |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 29 | #include <core/option.h> |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 30 | #include <subdev/fb.h> |
| 31 | #include <subdev/mc.h> |
| 32 | #include <subdev/timer.h> |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 33 | #include <engine/fifo.h> |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 34 | |
| 35 | #include <nvif/class.h> |
| 36 | #include <nvif/unpack.h> |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 37 | |
| 38 | /******************************************************************************* |
| 39 | * Zero Bandwidth Clear |
| 40 | ******************************************************************************/ |
| 41 | |
| 42 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 43 | gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 44 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 45 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 46 | if (gr->zbc_color[zbc].format) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 47 | nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); |
| 48 | nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); |
| 49 | nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); |
| 50 | nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 51 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 52 | nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); |
| 53 | nvkm_wr32(device, 0x405820, zbc); |
| 54 | nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | static int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 58 | gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 59 | const u32 ds[4], const u32 l2[4]) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 60 | { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 61 | struct nvkm_ltc *ltc = nvkm_ltc(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 62 | int zbc = -ENOSPC, i; |
| 63 | |
| 64 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 65 | if (gr->zbc_color[i].format) { |
| 66 | if (gr->zbc_color[i].format != format) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 67 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 68 | if (memcmp(gr->zbc_color[i].ds, ds, sizeof( |
| 69 | gr->zbc_color[i].ds))) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 70 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 71 | if (memcmp(gr->zbc_color[i].l2, l2, sizeof( |
| 72 | gr->zbc_color[i].l2))) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 73 | WARN_ON(1); |
| 74 | return -EINVAL; |
| 75 | } |
| 76 | return i; |
| 77 | } else { |
| 78 | zbc = (zbc < 0) ? i : zbc; |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | if (zbc < 0) |
| 83 | return zbc; |
| 84 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 85 | memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); |
| 86 | memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); |
| 87 | gr->zbc_color[zbc].format = format; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 88 | ltc->zbc_color_get(ltc, zbc, l2); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 89 | gf100_gr_zbc_clear_color(gr, zbc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 90 | return zbc; |
| 91 | } |
| 92 | |
| 93 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 94 | gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 95 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 96 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 97 | if (gr->zbc_depth[zbc].format) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 98 | nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); |
| 99 | nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); |
| 100 | nvkm_wr32(device, 0x405820, zbc); |
| 101 | nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 105 | gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 106 | const u32 ds, const u32 l2) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 107 | { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 108 | struct nvkm_ltc *ltc = nvkm_ltc(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 109 | int zbc = -ENOSPC, i; |
| 110 | |
| 111 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 112 | if (gr->zbc_depth[i].format) { |
| 113 | if (gr->zbc_depth[i].format != format) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 114 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 115 | if (gr->zbc_depth[i].ds != ds) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 116 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 117 | if (gr->zbc_depth[i].l2 != l2) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 118 | WARN_ON(1); |
| 119 | return -EINVAL; |
| 120 | } |
| 121 | return i; |
| 122 | } else { |
| 123 | zbc = (zbc < 0) ? i : zbc; |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | if (zbc < 0) |
| 128 | return zbc; |
| 129 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 130 | gr->zbc_depth[zbc].format = format; |
| 131 | gr->zbc_depth[zbc].ds = ds; |
| 132 | gr->zbc_depth[zbc].l2 = l2; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 133 | ltc->zbc_depth_get(ltc, zbc, l2); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 134 | gf100_gr_zbc_clear_depth(gr, zbc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 135 | return zbc; |
| 136 | } |
| 137 | |
| 138 | /******************************************************************************* |
| 139 | * Graphics object classes |
| 140 | ******************************************************************************/ |
| 141 | |
| 142 | static int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 143 | gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 144 | { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 145 | struct gf100_gr *gr = (void *)object->engine; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 146 | union { |
| 147 | struct fermi_a_zbc_color_v0 v0; |
| 148 | } *args = data; |
| 149 | int ret; |
| 150 | |
| 151 | if (nvif_unpack(args->v0, 0, 0, false)) { |
| 152 | switch (args->v0.format) { |
| 153 | case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: |
| 154 | case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: |
| 155 | case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: |
| 156 | case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: |
| 157 | case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: |
| 158 | case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: |
| 159 | case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: |
| 160 | case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: |
| 161 | case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: |
| 162 | case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: |
| 163 | case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: |
| 164 | case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: |
| 165 | case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: |
| 166 | case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: |
| 167 | case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: |
| 168 | case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: |
| 169 | case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: |
| 170 | case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: |
| 171 | case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 172 | ret = gf100_gr_zbc_color_get(gr, args->v0.format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 173 | args->v0.ds, |
| 174 | args->v0.l2); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 175 | if (ret >= 0) { |
| 176 | args->v0.index = ret; |
| 177 | return 0; |
| 178 | } |
| 179 | break; |
| 180 | default: |
| 181 | return -EINVAL; |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | return ret; |
| 186 | } |
| 187 | |
| 188 | static int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 189 | gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 190 | { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 191 | struct gf100_gr *gr = (void *)object->engine; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 192 | union { |
| 193 | struct fermi_a_zbc_depth_v0 v0; |
| 194 | } *args = data; |
| 195 | int ret; |
| 196 | |
| 197 | if (nvif_unpack(args->v0, 0, 0, false)) { |
| 198 | switch (args->v0.format) { |
| 199 | case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 200 | ret = gf100_gr_zbc_depth_get(gr, args->v0.format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 201 | args->v0.ds, |
| 202 | args->v0.l2); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 203 | return (ret >= 0) ? 0 : -ENOSPC; |
| 204 | default: |
| 205 | return -EINVAL; |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | return ret; |
| 210 | } |
| 211 | |
| 212 | static int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 213 | gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 214 | { |
| 215 | switch (mthd) { |
| 216 | case FERMI_A_ZBC_COLOR: |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 217 | return gf100_fermi_mthd_zbc_color(object, data, size); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 218 | case FERMI_A_ZBC_DEPTH: |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 219 | return gf100_fermi_mthd_zbc_depth(object, data, size); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 220 | default: |
| 221 | break; |
| 222 | } |
| 223 | return -EINVAL; |
| 224 | } |
| 225 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 226 | struct nvkm_ofuncs |
| 227 | gf100_fermi_ofuncs = { |
| 228 | .ctor = _nvkm_object_ctor, |
| 229 | .dtor = nvkm_object_destroy, |
Ben Skeggs | aa35888 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 230 | .init = _nvkm_object_init, |
| 231 | .fini = _nvkm_object_fini, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 232 | .mthd = gf100_fermi_mthd, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 233 | }; |
| 234 | |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 235 | static void |
| 236 | gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 237 | { |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 238 | nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); |
| 239 | nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 240 | } |
| 241 | |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 242 | static bool |
| 243 | gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) |
| 244 | { |
| 245 | switch (class & 0x00ff) { |
| 246 | case 0x97: |
| 247 | case 0xc0: |
| 248 | switch (mthd) { |
| 249 | case 0x1528: |
| 250 | gf100_gr_mthd_set_shader_exceptions(device, data); |
| 251 | return true; |
| 252 | default: |
| 253 | break; |
| 254 | } |
| 255 | break; |
| 256 | default: |
| 257 | break; |
| 258 | } |
| 259 | return false; |
| 260 | } |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 261 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 262 | struct nvkm_oclass |
| 263 | gf100_gr_sclass[] = { |
Ben Skeggs | 3740c82 | 2015-03-26 09:18:32 +1000 | [diff] [blame] | 264 | { FERMI_TWOD_A, &nvkm_object_ofuncs }, |
| 265 | { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 266 | { FERMI_A, &gf100_fermi_ofuncs }, |
| 267 | { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 268 | {} |
| 269 | }; |
| 270 | |
| 271 | /******************************************************************************* |
| 272 | * PGRAPH context |
| 273 | ******************************************************************************/ |
| 274 | |
| 275 | int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 276 | gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 277 | struct nvkm_oclass *oclass, void *args, u32 size, |
| 278 | struct nvkm_object **pobject) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 279 | { |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 280 | struct nvkm_vm *vm = nvkm_client(parent)->vm; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 281 | struct gf100_gr *gr = (void *)engine; |
| 282 | struct gf100_gr_data *data = gr->mmio_data; |
| 283 | struct gf100_gr_mmio *mmio = gr->mmio_list; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 284 | struct gf100_gr_chan *chan; |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 285 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 286 | struct nvkm_gpuobj *image; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 287 | int ret, i; |
| 288 | |
| 289 | /* allocate memory for context, and fill with default values */ |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 290 | ret = nvkm_gr_context_create(parent, engine, oclass, NULL, |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 291 | gr->size, 0x100, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 292 | NVOBJ_FLAG_ZERO_ALLOC, &chan); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 293 | *pobject = nv_object(chan); |
| 294 | if (ret) |
| 295 | return ret; |
| 296 | |
| 297 | /* allocate memory for a "mmio list" buffer that's used by the HUB |
| 298 | * fuc to modify some per-context register settings on first load |
| 299 | * of the context. |
| 300 | */ |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 301 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, |
| 302 | false, &chan->mmio); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 303 | if (ret) |
| 304 | return ret; |
| 305 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 306 | ret = nvkm_vm_get(vm, 0x1000, 12, NV_MEM_ACCESS_RW | |
| 307 | NV_MEM_ACCESS_SYS, &chan->mmio_vma); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 308 | if (ret) |
| 309 | return ret; |
| 310 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 311 | nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); |
| 312 | |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 313 | /* allocate buffers referenced by mmio list */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 314 | for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 315 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, |
| 316 | data->size, data->align, false, |
| 317 | &chan->data[i].mem); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 318 | if (ret) |
| 319 | return ret; |
| 320 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 321 | ret = nvkm_vm_get(vm, nvkm_memory_size(chan->data[i].mem), |
| 322 | 12, data->access, &chan->data[i].vma); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 323 | if (ret) |
| 324 | return ret; |
| 325 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 326 | nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 327 | data++; |
| 328 | } |
| 329 | |
| 330 | /* finally, fill in the mmio list and point the context at it */ |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 331 | nvkm_kmap(chan->mmio); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 332 | for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 333 | u32 addr = mmio->addr; |
| 334 | u32 data = mmio->data; |
| 335 | |
| 336 | if (mmio->buffer >= 0) { |
| 337 | u64 info = chan->data[mmio->buffer].vma.offset; |
| 338 | data |= info >> mmio->shift; |
| 339 | } |
| 340 | |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 341 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); |
| 342 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 343 | mmio++; |
| 344 | } |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 345 | nvkm_done(chan->mmio); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 346 | |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 347 | image = &chan->base.base.gpuobj; |
| 348 | nvkm_kmap(image); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 349 | for (i = 0; i < gr->size; i += 4) |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 350 | nvkm_wo32(image, i, gr->data[i / 4]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 351 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 352 | if (!gr->firmware) { |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 353 | nvkm_wo32(image, 0x00, chan->mmio_nr / 2); |
| 354 | nvkm_wo32(image, 0x04, chan->mmio_vma.offset >> 8); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 355 | } else { |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 356 | nvkm_wo32(image, 0xf4, 0); |
| 357 | nvkm_wo32(image, 0xf8, 0); |
| 358 | nvkm_wo32(image, 0x10, chan->mmio_nr / 2); |
| 359 | nvkm_wo32(image, 0x14, lower_32_bits(chan->mmio_vma.offset)); |
| 360 | nvkm_wo32(image, 0x18, upper_32_bits(chan->mmio_vma.offset)); |
| 361 | nvkm_wo32(image, 0x1c, 1); |
| 362 | nvkm_wo32(image, 0x20, 0); |
| 363 | nvkm_wo32(image, 0x28, 0); |
| 364 | nvkm_wo32(image, 0x2c, 0); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 365 | } |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 366 | nvkm_done(image); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | void |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 371 | gf100_gr_context_dtor(struct nvkm_object *object) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 372 | { |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 373 | struct gf100_gr_chan *chan = (void *)object; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 374 | int i; |
| 375 | |
| 376 | for (i = 0; i < ARRAY_SIZE(chan->data); i++) { |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 377 | if (chan->data[i].vma.node) { |
| 378 | nvkm_vm_unmap(&chan->data[i].vma); |
| 379 | nvkm_vm_put(&chan->data[i].vma); |
| 380 | } |
| 381 | nvkm_memory_del(&chan->data[i].mem); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 382 | } |
| 383 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 384 | if (chan->mmio_vma.node) { |
| 385 | nvkm_vm_unmap(&chan->mmio_vma); |
| 386 | nvkm_vm_put(&chan->mmio_vma); |
| 387 | } |
| 388 | nvkm_memory_del(&chan->mmio); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 389 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 390 | nvkm_gr_context_destroy(&chan->base); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 391 | } |
| 392 | |
| 393 | /******************************************************************************* |
| 394 | * PGRAPH register lists |
| 395 | ******************************************************************************/ |
| 396 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 397 | const struct gf100_gr_init |
| 398 | gf100_gr_init_main_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 399 | { 0x400080, 1, 0x04, 0x003083c2 }, |
| 400 | { 0x400088, 1, 0x04, 0x00006fe7 }, |
| 401 | { 0x40008c, 1, 0x04, 0x00000000 }, |
| 402 | { 0x400090, 1, 0x04, 0x00000030 }, |
| 403 | { 0x40013c, 1, 0x04, 0x013901f7 }, |
| 404 | { 0x400140, 1, 0x04, 0x00000100 }, |
| 405 | { 0x400144, 1, 0x04, 0x00000000 }, |
| 406 | { 0x400148, 1, 0x04, 0x00000110 }, |
| 407 | { 0x400138, 1, 0x04, 0x00000000 }, |
| 408 | { 0x400130, 2, 0x04, 0x00000000 }, |
| 409 | { 0x400124, 1, 0x04, 0x00000002 }, |
| 410 | {} |
| 411 | }; |
| 412 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 413 | const struct gf100_gr_init |
| 414 | gf100_gr_init_fe_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 415 | { 0x40415c, 1, 0x04, 0x00000000 }, |
| 416 | { 0x404170, 1, 0x04, 0x00000000 }, |
| 417 | {} |
| 418 | }; |
| 419 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 420 | const struct gf100_gr_init |
| 421 | gf100_gr_init_pri_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 422 | { 0x404488, 2, 0x04, 0x00000000 }, |
| 423 | {} |
| 424 | }; |
| 425 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 426 | const struct gf100_gr_init |
| 427 | gf100_gr_init_rstr2d_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 428 | { 0x407808, 1, 0x04, 0x00000000 }, |
| 429 | {} |
| 430 | }; |
| 431 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 432 | const struct gf100_gr_init |
| 433 | gf100_gr_init_pd_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 434 | { 0x406024, 1, 0x04, 0x00000000 }, |
| 435 | {} |
| 436 | }; |
| 437 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 438 | const struct gf100_gr_init |
| 439 | gf100_gr_init_ds_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 440 | { 0x405844, 1, 0x04, 0x00ffffff }, |
| 441 | { 0x405850, 1, 0x04, 0x00000000 }, |
| 442 | { 0x405908, 1, 0x04, 0x00000000 }, |
| 443 | {} |
| 444 | }; |
| 445 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 446 | const struct gf100_gr_init |
| 447 | gf100_gr_init_scc_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 448 | { 0x40803c, 1, 0x04, 0x00000000 }, |
| 449 | {} |
| 450 | }; |
| 451 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 452 | const struct gf100_gr_init |
| 453 | gf100_gr_init_prop_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 454 | { 0x4184a0, 1, 0x04, 0x00000000 }, |
| 455 | {} |
| 456 | }; |
| 457 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 458 | const struct gf100_gr_init |
| 459 | gf100_gr_init_gpc_unk_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 460 | { 0x418604, 1, 0x04, 0x00000000 }, |
| 461 | { 0x418680, 1, 0x04, 0x00000000 }, |
| 462 | { 0x418714, 1, 0x04, 0x80000000 }, |
| 463 | { 0x418384, 1, 0x04, 0x00000000 }, |
| 464 | {} |
| 465 | }; |
| 466 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 467 | const struct gf100_gr_init |
| 468 | gf100_gr_init_setup_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 469 | { 0x418814, 3, 0x04, 0x00000000 }, |
| 470 | {} |
| 471 | }; |
| 472 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 473 | const struct gf100_gr_init |
| 474 | gf100_gr_init_crstr_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 475 | { 0x418b04, 1, 0x04, 0x00000000 }, |
| 476 | {} |
| 477 | }; |
| 478 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 479 | const struct gf100_gr_init |
| 480 | gf100_gr_init_setup_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 481 | { 0x4188c8, 1, 0x04, 0x80000000 }, |
| 482 | { 0x4188cc, 1, 0x04, 0x00000000 }, |
| 483 | { 0x4188d0, 1, 0x04, 0x00010000 }, |
| 484 | { 0x4188d4, 1, 0x04, 0x00000001 }, |
| 485 | {} |
| 486 | }; |
| 487 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 488 | const struct gf100_gr_init |
| 489 | gf100_gr_init_zcull_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 490 | { 0x418910, 1, 0x04, 0x00010001 }, |
| 491 | { 0x418914, 1, 0x04, 0x00000301 }, |
| 492 | { 0x418918, 1, 0x04, 0x00800000 }, |
| 493 | { 0x418980, 1, 0x04, 0x77777770 }, |
| 494 | { 0x418984, 3, 0x04, 0x77777777 }, |
| 495 | {} |
| 496 | }; |
| 497 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 498 | const struct gf100_gr_init |
| 499 | gf100_gr_init_gpm_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 500 | { 0x418c04, 1, 0x04, 0x00000000 }, |
| 501 | { 0x418c88, 1, 0x04, 0x00000000 }, |
| 502 | {} |
| 503 | }; |
| 504 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 505 | const struct gf100_gr_init |
| 506 | gf100_gr_init_gpc_unk_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 507 | { 0x418d00, 1, 0x04, 0x00000000 }, |
| 508 | { 0x418f08, 1, 0x04, 0x00000000 }, |
| 509 | { 0x418e00, 1, 0x04, 0x00000050 }, |
| 510 | { 0x418e08, 1, 0x04, 0x00000000 }, |
| 511 | {} |
| 512 | }; |
| 513 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 514 | const struct gf100_gr_init |
| 515 | gf100_gr_init_gcc_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 516 | { 0x41900c, 1, 0x04, 0x00000000 }, |
| 517 | { 0x419018, 1, 0x04, 0x00000000 }, |
| 518 | {} |
| 519 | }; |
| 520 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 521 | const struct gf100_gr_init |
| 522 | gf100_gr_init_tpccs_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 523 | { 0x419d08, 2, 0x04, 0x00000000 }, |
| 524 | { 0x419d10, 1, 0x04, 0x00000014 }, |
| 525 | {} |
| 526 | }; |
| 527 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 528 | const struct gf100_gr_init |
| 529 | gf100_gr_init_tex_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 530 | { 0x419ab0, 1, 0x04, 0x00000000 }, |
| 531 | { 0x419ab8, 1, 0x04, 0x000000e7 }, |
| 532 | { 0x419abc, 2, 0x04, 0x00000000 }, |
| 533 | {} |
| 534 | }; |
| 535 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 536 | const struct gf100_gr_init |
| 537 | gf100_gr_init_pe_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 538 | { 0x41980c, 3, 0x04, 0x00000000 }, |
| 539 | { 0x419844, 1, 0x04, 0x00000000 }, |
| 540 | { 0x41984c, 1, 0x04, 0x00005bc5 }, |
| 541 | { 0x419850, 4, 0x04, 0x00000000 }, |
| 542 | {} |
| 543 | }; |
| 544 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 545 | const struct gf100_gr_init |
| 546 | gf100_gr_init_l1c_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 547 | { 0x419c98, 1, 0x04, 0x00000000 }, |
| 548 | { 0x419ca8, 1, 0x04, 0x80000000 }, |
| 549 | { 0x419cb4, 1, 0x04, 0x00000000 }, |
| 550 | { 0x419cb8, 1, 0x04, 0x00008bf4 }, |
| 551 | { 0x419cbc, 1, 0x04, 0x28137606 }, |
| 552 | { 0x419cc0, 2, 0x04, 0x00000000 }, |
| 553 | {} |
| 554 | }; |
| 555 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 556 | const struct gf100_gr_init |
| 557 | gf100_gr_init_wwdx_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 558 | { 0x419bd4, 1, 0x04, 0x00800000 }, |
| 559 | { 0x419bdc, 1, 0x04, 0x00000000 }, |
| 560 | {} |
| 561 | }; |
| 562 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 563 | const struct gf100_gr_init |
| 564 | gf100_gr_init_tpccs_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 565 | { 0x419d2c, 1, 0x04, 0x00000000 }, |
| 566 | {} |
| 567 | }; |
| 568 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 569 | const struct gf100_gr_init |
| 570 | gf100_gr_init_mpc_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 571 | { 0x419c0c, 1, 0x04, 0x00000000 }, |
| 572 | {} |
| 573 | }; |
| 574 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 575 | static const struct gf100_gr_init |
| 576 | gf100_gr_init_sm_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 577 | { 0x419e00, 1, 0x04, 0x00000000 }, |
| 578 | { 0x419ea0, 1, 0x04, 0x00000000 }, |
| 579 | { 0x419ea4, 1, 0x04, 0x00000100 }, |
| 580 | { 0x419ea8, 1, 0x04, 0x00001100 }, |
| 581 | { 0x419eac, 1, 0x04, 0x11100702 }, |
| 582 | { 0x419eb0, 1, 0x04, 0x00000003 }, |
| 583 | { 0x419eb4, 4, 0x04, 0x00000000 }, |
| 584 | { 0x419ec8, 1, 0x04, 0x06060618 }, |
| 585 | { 0x419ed0, 1, 0x04, 0x0eff0e38 }, |
| 586 | { 0x419ed4, 1, 0x04, 0x011104f1 }, |
| 587 | { 0x419edc, 1, 0x04, 0x00000000 }, |
| 588 | { 0x419f00, 1, 0x04, 0x00000000 }, |
| 589 | { 0x419f2c, 1, 0x04, 0x00000000 }, |
| 590 | {} |
| 591 | }; |
| 592 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 593 | const struct gf100_gr_init |
| 594 | gf100_gr_init_be_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 595 | { 0x40880c, 1, 0x04, 0x00000000 }, |
| 596 | { 0x408910, 9, 0x04, 0x00000000 }, |
| 597 | { 0x408950, 1, 0x04, 0x00000000 }, |
| 598 | { 0x408954, 1, 0x04, 0x0000ffff }, |
| 599 | { 0x408984, 1, 0x04, 0x00000000 }, |
| 600 | { 0x408988, 1, 0x04, 0x08040201 }, |
| 601 | { 0x40898c, 1, 0x04, 0x80402010 }, |
| 602 | {} |
| 603 | }; |
| 604 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 605 | const struct gf100_gr_init |
| 606 | gf100_gr_init_fe_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 607 | { 0x4040f0, 1, 0x04, 0x00000000 }, |
| 608 | {} |
| 609 | }; |
| 610 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 611 | const struct gf100_gr_init |
| 612 | gf100_gr_init_pe_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 613 | { 0x419880, 1, 0x04, 0x00000002 }, |
| 614 | {} |
| 615 | }; |
| 616 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 617 | static const struct gf100_gr_pack |
| 618 | gf100_gr_pack_mmio[] = { |
| 619 | { gf100_gr_init_main_0 }, |
| 620 | { gf100_gr_init_fe_0 }, |
| 621 | { gf100_gr_init_pri_0 }, |
| 622 | { gf100_gr_init_rstr2d_0 }, |
| 623 | { gf100_gr_init_pd_0 }, |
| 624 | { gf100_gr_init_ds_0 }, |
| 625 | { gf100_gr_init_scc_0 }, |
| 626 | { gf100_gr_init_prop_0 }, |
| 627 | { gf100_gr_init_gpc_unk_0 }, |
| 628 | { gf100_gr_init_setup_0 }, |
| 629 | { gf100_gr_init_crstr_0 }, |
| 630 | { gf100_gr_init_setup_1 }, |
| 631 | { gf100_gr_init_zcull_0 }, |
| 632 | { gf100_gr_init_gpm_0 }, |
| 633 | { gf100_gr_init_gpc_unk_1 }, |
| 634 | { gf100_gr_init_gcc_0 }, |
| 635 | { gf100_gr_init_tpccs_0 }, |
| 636 | { gf100_gr_init_tex_0 }, |
| 637 | { gf100_gr_init_pe_0 }, |
| 638 | { gf100_gr_init_l1c_0 }, |
| 639 | { gf100_gr_init_wwdx_0 }, |
| 640 | { gf100_gr_init_tpccs_1 }, |
| 641 | { gf100_gr_init_mpc_0 }, |
| 642 | { gf100_gr_init_sm_0 }, |
| 643 | { gf100_gr_init_be_0 }, |
| 644 | { gf100_gr_init_fe_1 }, |
| 645 | { gf100_gr_init_pe_1 }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 646 | {} |
| 647 | }; |
| 648 | |
| 649 | /******************************************************************************* |
| 650 | * PGRAPH engine/subdev functions |
| 651 | ******************************************************************************/ |
| 652 | |
| 653 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 654 | gf100_gr_zbc_init(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 655 | { |
| 656 | const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 657 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; |
| 658 | const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, |
| 659 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 660 | const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 661 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; |
| 662 | const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, |
| 663 | 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 664 | struct nvkm_ltc *ltc = nvkm_ltc(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 665 | int index; |
| 666 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 667 | if (!gr->zbc_color[0].format) { |
| 668 | gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); |
| 669 | gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); |
| 670 | gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); |
| 671 | gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); |
| 672 | gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); |
| 673 | gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 674 | } |
| 675 | |
| 676 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 677 | gf100_gr_zbc_clear_color(gr, index); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 678 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 679 | gf100_gr_zbc_clear_depth(gr, index); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 680 | } |
| 681 | |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 682 | /** |
| 683 | * Wait until GR goes idle. GR is considered idle if it is disabled by the |
| 684 | * MC (0x200) register, or GR is not busy and a context switch is not in |
| 685 | * progress. |
| 686 | */ |
| 687 | int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 688 | gf100_gr_wait_idle(struct gf100_gr *gr) |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 689 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 690 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 691 | struct nvkm_device *device = subdev->device; |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 692 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); |
| 693 | bool gr_enabled, ctxsw_active, gr_busy; |
| 694 | |
| 695 | do { |
| 696 | /* |
| 697 | * required to make sure FIFO_ENGINE_STATUS (0x2640) is |
| 698 | * up-to-date |
| 699 | */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 700 | nvkm_rd32(device, 0x400700); |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 701 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 702 | gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; |
| 703 | ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; |
| 704 | gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 705 | |
| 706 | if (!gr_enabled || (!gr_busy && !ctxsw_active)) |
| 707 | return 0; |
| 708 | } while (time_before(jiffies, end_jiffies)); |
| 709 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 710 | nvkm_error(subdev, |
| 711 | "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", |
| 712 | gr_enabled, ctxsw_active, gr_busy); |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 713 | return -EAGAIN; |
| 714 | } |
| 715 | |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 716 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 717 | gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 718 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 719 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 720 | const struct gf100_gr_pack *pack; |
| 721 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 722 | |
| 723 | pack_for_each_init(init, pack, p) { |
| 724 | u32 next = init->addr + init->count * init->pitch; |
| 725 | u32 addr = init->addr; |
| 726 | while (addr < next) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 727 | nvkm_wr32(device, addr, init->data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 728 | addr += init->pitch; |
| 729 | } |
| 730 | } |
| 731 | } |
| 732 | |
| 733 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 734 | gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 735 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 736 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 737 | const struct gf100_gr_pack *pack; |
| 738 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 739 | u32 data = 0; |
| 740 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 741 | nvkm_wr32(device, 0x400208, 0x80000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 742 | |
| 743 | pack_for_each_init(init, pack, p) { |
| 744 | u32 next = init->addr + init->count * init->pitch; |
| 745 | u32 addr = init->addr; |
| 746 | |
| 747 | if ((pack == p && init == p->init) || data != init->data) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 748 | nvkm_wr32(device, 0x400204, init->data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 749 | data = init->data; |
| 750 | } |
| 751 | |
| 752 | while (addr < next) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 753 | nvkm_wr32(device, 0x400200, addr); |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 754 | /** |
| 755 | * Wait for GR to go idle after submitting a |
| 756 | * GO_IDLE bundle |
| 757 | */ |
| 758 | if ((addr & 0xffff) == 0xe100) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 759 | gf100_gr_wait_idle(gr); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 760 | nvkm_msec(device, 2000, |
| 761 | if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) |
| 762 | break; |
| 763 | ); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 764 | addr += init->pitch; |
| 765 | } |
| 766 | } |
| 767 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 768 | nvkm_wr32(device, 0x400208, 0x00000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 769 | } |
| 770 | |
| 771 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 772 | gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 773 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 774 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 775 | const struct gf100_gr_pack *pack; |
| 776 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 777 | u32 data = 0; |
| 778 | |
| 779 | pack_for_each_init(init, pack, p) { |
| 780 | u32 ctrl = 0x80000000 | pack->type; |
| 781 | u32 next = init->addr + init->count * init->pitch; |
| 782 | u32 addr = init->addr; |
| 783 | |
| 784 | if ((pack == p && init == p->init) || data != init->data) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 785 | nvkm_wr32(device, 0x40448c, init->data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 786 | data = init->data; |
| 787 | } |
| 788 | |
| 789 | while (addr < next) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 790 | nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 791 | addr += init->pitch; |
| 792 | } |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | u64 |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 797 | gf100_gr_units(struct nvkm_gr *obj) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 798 | { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 799 | struct gf100_gr *gr = container_of(obj, typeof(*gr), base); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 800 | u64 cfg; |
| 801 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 802 | cfg = (u32)gr->gpc_nr; |
| 803 | cfg |= (u32)gr->tpc_total << 8; |
| 804 | cfg |= (u64)gr->rop_nr << 32; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 805 | |
| 806 | return cfg; |
| 807 | } |
| 808 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 809 | static const struct nvkm_bitfield gk104_sked_error[] = { |
| 810 | { 0x00000080, "CONSTANT_BUFFER_SIZE" }, |
| 811 | { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, |
| 812 | { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, |
| 813 | { 0x00000800, "WARP_CSTACK_SIZE" }, |
| 814 | { 0x00001000, "TOTAL_TEMP_SIZE" }, |
| 815 | { 0x00002000, "REGISTER_COUNT" }, |
| 816 | { 0x00040000, "TOTAL_THREADS" }, |
| 817 | { 0x00100000, "PROGRAM_OFFSET" }, |
| 818 | { 0x00200000, "SHARED_MEMORY_SIZE" }, |
| 819 | { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, |
| 820 | { 0x04000000, "TOTAL_REGISTER_COUNT" }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 821 | {} |
| 822 | }; |
| 823 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 824 | static const struct nvkm_bitfield gf100_gpc_rop_error[] = { |
| 825 | { 0x00000002, "RT_PITCH_OVERRUN" }, |
| 826 | { 0x00000010, "RT_WIDTH_OVERRUN" }, |
| 827 | { 0x00000020, "RT_HEIGHT_OVERRUN" }, |
| 828 | { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, |
| 829 | { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, |
| 830 | { 0x00000400, "RT_LINEAR_MISMATCH" }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 831 | {} |
| 832 | }; |
| 833 | |
| 834 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 835 | gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 836 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 837 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 838 | struct nvkm_device *device = subdev->device; |
| 839 | char error[128]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 840 | u32 trap[4]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 841 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 842 | trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 843 | trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); |
| 844 | trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); |
| 845 | trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 846 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 847 | nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 848 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 849 | nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " |
| 850 | "format = %x, storage type = %x\n", |
| 851 | gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, |
| 852 | (trap[2] >> 8) & 0x3f, trap[3] & 0xff); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 853 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 854 | } |
| 855 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 856 | static const struct nvkm_enum gf100_mp_warp_error[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 857 | { 0x00, "NO_ERROR" }, |
| 858 | { 0x01, "STACK_MISMATCH" }, |
| 859 | { 0x05, "MISALIGNED_PC" }, |
| 860 | { 0x08, "MISALIGNED_GPR" }, |
| 861 | { 0x09, "INVALID_OPCODE" }, |
| 862 | { 0x0d, "GPR_OUT_OF_BOUNDS" }, |
| 863 | { 0x0e, "MEM_OUT_OF_BOUNDS" }, |
| 864 | { 0x0f, "UNALIGNED_MEM_ACCESS" }, |
| 865 | { 0x11, "INVALID_PARAM" }, |
| 866 | {} |
| 867 | }; |
| 868 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 869 | static const struct nvkm_bitfield gf100_mp_global_error[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 870 | { 0x00000004, "MULTIPLE_WARP_ERRORS" }, |
| 871 | { 0x00000008, "OUT_OF_STACK_SPACE" }, |
| 872 | {} |
| 873 | }; |
| 874 | |
| 875 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 876 | gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 877 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 878 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 879 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 880 | u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); |
| 881 | u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 882 | const struct nvkm_enum *warp; |
| 883 | char glob[128]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 884 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 885 | nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); |
| 886 | warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); |
| 887 | |
| 888 | nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " |
| 889 | "global %08x [%s] warp %04x [%s]\n", |
| 890 | gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 891 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 892 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); |
| 893 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 894 | } |
| 895 | |
| 896 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 897 | gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 898 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 899 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 900 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 901 | u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 902 | |
| 903 | if (stat & 0x00000001) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 904 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 905 | nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 906 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 907 | stat &= ~0x00000001; |
| 908 | } |
| 909 | |
| 910 | if (stat & 0x00000002) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 911 | gf100_gr_trap_mp(gr, gpc, tpc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 912 | stat &= ~0x00000002; |
| 913 | } |
| 914 | |
| 915 | if (stat & 0x00000004) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 916 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 917 | nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 918 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 919 | stat &= ~0x00000004; |
| 920 | } |
| 921 | |
| 922 | if (stat & 0x00000008) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 923 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 924 | nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 925 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 926 | stat &= ~0x00000008; |
| 927 | } |
| 928 | |
| 929 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 930 | nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 931 | } |
| 932 | } |
| 933 | |
| 934 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 935 | gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 936 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 937 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 938 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 939 | u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 940 | int tpc; |
| 941 | |
| 942 | if (stat & 0x00000001) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 943 | gf100_gr_trap_gpc_rop(gr, gpc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 944 | stat &= ~0x00000001; |
| 945 | } |
| 946 | |
| 947 | if (stat & 0x00000002) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 948 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 949 | nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 950 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 951 | stat &= ~0x00000002; |
| 952 | } |
| 953 | |
| 954 | if (stat & 0x00000004) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 955 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 956 | nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 957 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 958 | stat &= ~0x00000004; |
| 959 | } |
| 960 | |
| 961 | if (stat & 0x00000008) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 962 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 963 | nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 964 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 965 | stat &= ~0x00000009; |
| 966 | } |
| 967 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 968 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 969 | u32 mask = 0x00010000 << tpc; |
| 970 | if (stat & mask) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 971 | gf100_gr_trap_tpc(gr, gpc, tpc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 972 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 973 | stat &= ~mask; |
| 974 | } |
| 975 | } |
| 976 | |
| 977 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 978 | nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 979 | } |
| 980 | } |
| 981 | |
| 982 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 983 | gf100_gr_trap_intr(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 984 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 985 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 986 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 987 | u32 trap = nvkm_rd32(device, 0x400108); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 988 | int rop, gpc; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 989 | |
| 990 | if (trap & 0x00000001) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 991 | u32 stat = nvkm_rd32(device, 0x404000); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 992 | nvkm_error(subdev, "DISPATCH %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 993 | nvkm_wr32(device, 0x404000, 0xc0000000); |
| 994 | nvkm_wr32(device, 0x400108, 0x00000001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 995 | trap &= ~0x00000001; |
| 996 | } |
| 997 | |
| 998 | if (trap & 0x00000002) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 999 | u32 stat = nvkm_rd32(device, 0x404600); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1000 | nvkm_error(subdev, "M2MF %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1001 | nvkm_wr32(device, 0x404600, 0xc0000000); |
| 1002 | nvkm_wr32(device, 0x400108, 0x00000002); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1003 | trap &= ~0x00000002; |
| 1004 | } |
| 1005 | |
| 1006 | if (trap & 0x00000008) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1007 | u32 stat = nvkm_rd32(device, 0x408030); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1008 | nvkm_error(subdev, "CCACHE %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1009 | nvkm_wr32(device, 0x408030, 0xc0000000); |
| 1010 | nvkm_wr32(device, 0x400108, 0x00000008); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1011 | trap &= ~0x00000008; |
| 1012 | } |
| 1013 | |
| 1014 | if (trap & 0x00000010) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1015 | u32 stat = nvkm_rd32(device, 0x405840); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1016 | nvkm_error(subdev, "SHADER %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1017 | nvkm_wr32(device, 0x405840, 0xc0000000); |
| 1018 | nvkm_wr32(device, 0x400108, 0x00000010); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1019 | trap &= ~0x00000010; |
| 1020 | } |
| 1021 | |
| 1022 | if (trap & 0x00000040) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1023 | u32 stat = nvkm_rd32(device, 0x40601c); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1024 | nvkm_error(subdev, "UNK6 %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1025 | nvkm_wr32(device, 0x40601c, 0xc0000000); |
| 1026 | nvkm_wr32(device, 0x400108, 0x00000040); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1027 | trap &= ~0x00000040; |
| 1028 | } |
| 1029 | |
| 1030 | if (trap & 0x00000080) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1031 | u32 stat = nvkm_rd32(device, 0x404490); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1032 | nvkm_error(subdev, "MACRO %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1033 | nvkm_wr32(device, 0x404490, 0xc0000000); |
| 1034 | nvkm_wr32(device, 0x400108, 0x00000080); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1035 | trap &= ~0x00000080; |
| 1036 | } |
| 1037 | |
| 1038 | if (trap & 0x00000100) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1039 | u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; |
| 1040 | char sked[128]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1041 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1042 | nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat); |
| 1043 | nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1044 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1045 | if (stat) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1046 | nvkm_wr32(device, 0x407020, 0x40000000); |
| 1047 | nvkm_wr32(device, 0x400108, 0x00000100); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1048 | trap &= ~0x00000100; |
| 1049 | } |
| 1050 | |
| 1051 | if (trap & 0x01000000) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1052 | u32 stat = nvkm_rd32(device, 0x400118); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1053 | for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1054 | u32 mask = 0x00000001 << gpc; |
| 1055 | if (stat & mask) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1056 | gf100_gr_trap_gpc(gr, gpc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1057 | nvkm_wr32(device, 0x400118, mask); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1058 | stat &= ~mask; |
| 1059 | } |
| 1060 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1061 | nvkm_wr32(device, 0x400108, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1062 | trap &= ~0x01000000; |
| 1063 | } |
| 1064 | |
| 1065 | if (trap & 0x02000000) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1066 | for (rop = 0; rop < gr->rop_nr; rop++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1067 | u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); |
| 1068 | u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1069 | nvkm_error(subdev, "ROP%d %08x %08x\n", |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1070 | rop, statz, statc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1071 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); |
| 1072 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1073 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1074 | nvkm_wr32(device, 0x400108, 0x02000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1075 | trap &= ~0x02000000; |
| 1076 | } |
| 1077 | |
| 1078 | if (trap) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1079 | nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1080 | nvkm_wr32(device, 0x400108, trap); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1081 | } |
| 1082 | } |
| 1083 | |
| 1084 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1085 | gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1086 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1087 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1088 | struct nvkm_device *device = subdev->device; |
| 1089 | nvkm_error(subdev, "%06x - done %08x\n", base, |
| 1090 | nvkm_rd32(device, base + 0x400)); |
| 1091 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, |
| 1092 | nvkm_rd32(device, base + 0x800), |
| 1093 | nvkm_rd32(device, base + 0x804), |
| 1094 | nvkm_rd32(device, base + 0x808), |
| 1095 | nvkm_rd32(device, base + 0x80c)); |
| 1096 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, |
| 1097 | nvkm_rd32(device, base + 0x810), |
| 1098 | nvkm_rd32(device, base + 0x814), |
| 1099 | nvkm_rd32(device, base + 0x818), |
| 1100 | nvkm_rd32(device, base + 0x81c)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1101 | } |
| 1102 | |
| 1103 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1104 | gf100_gr_ctxctl_debug(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1105 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1106 | struct nvkm_device *device = gr->base.engine.subdev.device; |
| 1107 | u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1108 | u32 gpc; |
| 1109 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1110 | gf100_gr_ctxctl_debug_unit(gr, 0x409000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1111 | for (gpc = 0; gpc < gpcnr; gpc++) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1112 | gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1113 | } |
| 1114 | |
| 1115 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1116 | gf100_gr_ctxctl_isr(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1117 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1118 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1119 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1120 | u32 stat = nvkm_rd32(device, 0x409c18); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1121 | |
| 1122 | if (stat & 0x00000001) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1123 | u32 code = nvkm_rd32(device, 0x409814); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1124 | if (code == E_BAD_FWMTHD) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1125 | u32 class = nvkm_rd32(device, 0x409808); |
| 1126 | u32 addr = nvkm_rd32(device, 0x40980c); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1127 | u32 subc = (addr & 0x00070000) >> 16; |
| 1128 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1129 | u32 data = nvkm_rd32(device, 0x409810); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1130 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1131 | nvkm_error(subdev, "FECS MTHD subc %d class %04x " |
| 1132 | "mthd %04x data %08x\n", |
| 1133 | subc, class, mthd, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1134 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1135 | nvkm_wr32(device, 0x409c20, 0x00000001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1136 | stat &= ~0x00000001; |
| 1137 | } else { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1138 | nvkm_error(subdev, "FECS ucode error %d\n", code); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | if (stat & 0x00080000) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1143 | nvkm_error(subdev, "FECS watchdog timeout\n"); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1144 | gf100_gr_ctxctl_debug(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1145 | nvkm_wr32(device, 0x409c20, 0x00080000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1146 | stat &= ~0x00080000; |
| 1147 | } |
| 1148 | |
| 1149 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1150 | nvkm_error(subdev, "FECS %08x\n", stat); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1151 | gf100_gr_ctxctl_debug(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1152 | nvkm_wr32(device, 0x409c20, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1153 | } |
| 1154 | } |
| 1155 | |
| 1156 | static void |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1157 | gf100_gr_intr(struct nvkm_subdev *subdev) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1158 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1159 | struct gf100_gr *gr = (void *)subdev; |
| 1160 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1161 | struct nvkm_fifo_chan *chan; |
| 1162 | unsigned long flags; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1163 | u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; |
| 1164 | u32 stat = nvkm_rd32(device, 0x400100); |
| 1165 | u32 addr = nvkm_rd32(device, 0x400704); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1166 | u32 mthd = (addr & 0x00003ffc); |
| 1167 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1168 | u32 data = nvkm_rd32(device, 0x400708); |
| 1169 | u32 code = nvkm_rd32(device, 0x400110); |
Ben Skeggs | 91c772e | 2015-04-13 13:09:28 +1000 | [diff] [blame] | 1170 | u32 class; |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame^] | 1171 | const char *name = "unknown"; |
| 1172 | int chid = -1; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1173 | |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1174 | chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame^] | 1175 | if (chan) { |
| 1176 | name = chan->object.client->name; |
| 1177 | chid = chan->chid; |
| 1178 | } |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1179 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1180 | if (nv_device(gr)->card_type < NV_E0 || subc < 4) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1181 | class = nvkm_rd32(device, 0x404200 + (subc * 4)); |
Ben Skeggs | 91c772e | 2015-04-13 13:09:28 +1000 | [diff] [blame] | 1182 | else |
| 1183 | class = 0x0000; |
| 1184 | |
Lauri Peltonen | c6a7b02 | 2015-02-26 13:16:48 +0900 | [diff] [blame] | 1185 | if (stat & 0x00000001) { |
| 1186 | /* |
| 1187 | * notifier interrupt, only needed for cyclestats |
| 1188 | * can be safely ignored |
| 1189 | */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1190 | nvkm_wr32(device, 0x400100, 0x00000001); |
Lauri Peltonen | c6a7b02 | 2015-02-26 13:16:48 +0900 | [diff] [blame] | 1191 | stat &= ~0x00000001; |
| 1192 | } |
| 1193 | |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1194 | if (stat & 0x00000010) { |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1195 | if (!gf100_gr_mthd_sw(device, class, mthd, data)) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1196 | nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " |
| 1197 | "subc %d class %04x mthd %04x data %08x\n", |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame^] | 1198 | chid, inst << 12, name, subc, |
| 1199 | class, mthd, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1200 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1201 | nvkm_wr32(device, 0x400100, 0x00000010); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1202 | stat &= ~0x00000010; |
| 1203 | } |
| 1204 | |
| 1205 | if (stat & 0x00000020) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1206 | nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " |
| 1207 | "subc %d class %04x mthd %04x data %08x\n", |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame^] | 1208 | chid, inst << 12, name, subc, class, mthd, data); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1209 | nvkm_wr32(device, 0x400100, 0x00000020); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1210 | stat &= ~0x00000020; |
| 1211 | } |
| 1212 | |
| 1213 | if (stat & 0x00100000) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1214 | const struct nvkm_enum *en = |
| 1215 | nvkm_enum_find(nv50_data_error_names, code); |
| 1216 | nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " |
| 1217 | "subc %d class %04x mthd %04x data %08x\n", |
| 1218 | code, en ? en->name : "", chid, inst << 12, |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame^] | 1219 | name, subc, class, mthd, data); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1220 | nvkm_wr32(device, 0x400100, 0x00100000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1221 | stat &= ~0x00100000; |
| 1222 | } |
| 1223 | |
| 1224 | if (stat & 0x00200000) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1225 | nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame^] | 1226 | chid, inst << 12, name); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1227 | gf100_gr_trap_intr(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1228 | nvkm_wr32(device, 0x400100, 0x00200000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1229 | stat &= ~0x00200000; |
| 1230 | } |
| 1231 | |
| 1232 | if (stat & 0x00080000) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1233 | gf100_gr_ctxctl_isr(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1234 | nvkm_wr32(device, 0x400100, 0x00080000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1235 | stat &= ~0x00080000; |
| 1236 | } |
| 1237 | |
| 1238 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1239 | nvkm_error(subdev, "intr %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1240 | nvkm_wr32(device, 0x400100, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1241 | } |
| 1242 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1243 | nvkm_wr32(device, 0x400500, 0x00010001); |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1244 | nvkm_fifo_chan_put(device->fifo, flags, &chan); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1245 | } |
| 1246 | |
| 1247 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1248 | gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1249 | struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1250 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1251 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1252 | int i; |
| 1253 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1254 | nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1255 | for (i = 0; i < data->size / 4; i++) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1256 | nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1257 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1258 | nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1259 | for (i = 0; i < code->size / 4; i++) { |
| 1260 | if ((i & 0x3f) == 0) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1261 | nvkm_wr32(device, fuc_base + 0x0188, i >> 6); |
| 1262 | nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1263 | } |
| 1264 | |
| 1265 | /* code must be padded to 0x40 words */ |
| 1266 | for (; i & 0x3f; i++) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1267 | nvkm_wr32(device, fuc_base + 0x0184, 0); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1268 | } |
| 1269 | |
| 1270 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1271 | gf100_gr_init_csdata(struct gf100_gr *gr, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1272 | const struct gf100_gr_pack *pack, |
| 1273 | u32 falcon, u32 starstar, u32 base) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1274 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1275 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1276 | const struct gf100_gr_pack *iter; |
| 1277 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1278 | u32 addr = ~0, prev = ~0, xfer = 0; |
| 1279 | u32 star, temp; |
| 1280 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1281 | nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); |
| 1282 | star = nvkm_rd32(device, falcon + 0x01c4); |
| 1283 | temp = nvkm_rd32(device, falcon + 0x01c4); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1284 | if (temp > star) |
| 1285 | star = temp; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1286 | nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1287 | |
| 1288 | pack_for_each_init(init, iter, pack) { |
| 1289 | u32 head = init->addr - base; |
| 1290 | u32 tail = head + init->count * init->pitch; |
| 1291 | while (head < tail) { |
| 1292 | if (head != prev + 4 || xfer >= 32) { |
| 1293 | if (xfer) { |
| 1294 | u32 data = ((--xfer << 26) | addr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1295 | nvkm_wr32(device, falcon + 0x01c4, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1296 | star += 4; |
| 1297 | } |
| 1298 | addr = head; |
| 1299 | xfer = 0; |
| 1300 | } |
| 1301 | prev = head; |
| 1302 | xfer = xfer + 1; |
| 1303 | head = head + init->pitch; |
| 1304 | } |
| 1305 | } |
| 1306 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1307 | nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); |
| 1308 | nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); |
| 1309 | nvkm_wr32(device, falcon + 0x01c4, star + 4); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1310 | } |
| 1311 | |
| 1312 | int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1313 | gf100_gr_init_ctxctl(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1314 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1315 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1316 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1317 | struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; |
| 1318 | struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1319 | int i; |
| 1320 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1321 | if (gr->firmware) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1322 | /* load fuc microcode */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1323 | nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); |
| 1324 | gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, |
| 1325 | &gr->fuc409d); |
| 1326 | gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, |
| 1327 | &gr->fuc41ad); |
| 1328 | nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1329 | |
| 1330 | /* start both of them running */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1331 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1332 | nvkm_wr32(device, 0x41a10c, 0x00000000); |
| 1333 | nvkm_wr32(device, 0x40910c, 0x00000000); |
| 1334 | nvkm_wr32(device, 0x41a100, 0x00000002); |
| 1335 | nvkm_wr32(device, 0x409100, 0x00000002); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1336 | if (nvkm_msec(device, 2000, |
| 1337 | if (nvkm_rd32(device, 0x409800) & 0x00000001) |
| 1338 | break; |
| 1339 | ) < 0) |
| 1340 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1341 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1342 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1343 | nvkm_wr32(device, 0x409500, 0x7fffffff); |
| 1344 | nvkm_wr32(device, 0x409504, 0x00000021); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1345 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1346 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1347 | nvkm_wr32(device, 0x409500, 0x00000000); |
| 1348 | nvkm_wr32(device, 0x409504, 0x00000010); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1349 | if (nvkm_msec(device, 2000, |
| 1350 | if ((gr->size = nvkm_rd32(device, 0x409800))) |
| 1351 | break; |
| 1352 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1353 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1354 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1355 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1356 | nvkm_wr32(device, 0x409500, 0x00000000); |
| 1357 | nvkm_wr32(device, 0x409504, 0x00000016); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1358 | if (nvkm_msec(device, 2000, |
| 1359 | if (nvkm_rd32(device, 0x409800)) |
| 1360 | break; |
| 1361 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1362 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1363 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1364 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1365 | nvkm_wr32(device, 0x409500, 0x00000000); |
| 1366 | nvkm_wr32(device, 0x409504, 0x00000025); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1367 | if (nvkm_msec(device, 2000, |
| 1368 | if (nvkm_rd32(device, 0x409800)) |
| 1369 | break; |
| 1370 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1371 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1372 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1373 | if (nv_device(gr)->chipset >= 0xe0) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1374 | nvkm_wr32(device, 0x409800, 0x00000000); |
| 1375 | nvkm_wr32(device, 0x409500, 0x00000001); |
| 1376 | nvkm_wr32(device, 0x409504, 0x00000030); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1377 | if (nvkm_msec(device, 2000, |
| 1378 | if (nvkm_rd32(device, 0x409800)) |
| 1379 | break; |
| 1380 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1381 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1382 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1383 | nvkm_wr32(device, 0x409810, 0xb00095c8); |
| 1384 | nvkm_wr32(device, 0x409800, 0x00000000); |
| 1385 | nvkm_wr32(device, 0x409500, 0x00000001); |
| 1386 | nvkm_wr32(device, 0x409504, 0x00000031); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1387 | if (nvkm_msec(device, 2000, |
| 1388 | if (nvkm_rd32(device, 0x409800)) |
| 1389 | break; |
| 1390 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1391 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1392 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1393 | nvkm_wr32(device, 0x409810, 0x00080420); |
| 1394 | nvkm_wr32(device, 0x409800, 0x00000000); |
| 1395 | nvkm_wr32(device, 0x409500, 0x00000001); |
| 1396 | nvkm_wr32(device, 0x409504, 0x00000032); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1397 | if (nvkm_msec(device, 2000, |
| 1398 | if (nvkm_rd32(device, 0x409800)) |
| 1399 | break; |
| 1400 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1401 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1402 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1403 | nvkm_wr32(device, 0x409614, 0x00000070); |
| 1404 | nvkm_wr32(device, 0x409614, 0x00000770); |
| 1405 | nvkm_wr32(device, 0x40802c, 0x00000001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1406 | } |
| 1407 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1408 | if (gr->data == NULL) { |
| 1409 | int ret = gf100_grctx_generate(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1410 | if (ret) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1411 | nvkm_error(subdev, "failed to construct context\n"); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1412 | return ret; |
| 1413 | } |
| 1414 | } |
| 1415 | |
| 1416 | return 0; |
| 1417 | } else |
| 1418 | if (!oclass->fecs.ucode) { |
| 1419 | return -ENOSYS; |
| 1420 | } |
| 1421 | |
| 1422 | /* load HUB microcode */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1423 | nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1424 | nvkm_wr32(device, 0x4091c0, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1425 | for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1426 | nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1427 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1428 | nvkm_wr32(device, 0x409180, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1429 | for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { |
| 1430 | if ((i & 0x3f) == 0) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1431 | nvkm_wr32(device, 0x409188, i >> 6); |
| 1432 | nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1433 | } |
| 1434 | |
| 1435 | /* load GPC microcode */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1436 | nvkm_wr32(device, 0x41a1c0, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1437 | for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1438 | nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1439 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1440 | nvkm_wr32(device, 0x41a180, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1441 | for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { |
| 1442 | if ((i & 0x3f) == 0) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1443 | nvkm_wr32(device, 0x41a188, i >> 6); |
| 1444 | nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1445 | } |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1446 | nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1447 | |
| 1448 | /* load register lists */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1449 | gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000); |
| 1450 | gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000); |
| 1451 | gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800); |
| 1452 | gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1453 | |
| 1454 | /* start HUB ucode running, it'll init the GPCs */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1455 | nvkm_wr32(device, 0x40910c, 0x00000000); |
| 1456 | nvkm_wr32(device, 0x409100, 0x00000002); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1457 | if (nvkm_msec(device, 2000, |
| 1458 | if (nvkm_rd32(device, 0x409800) & 0x80000000) |
| 1459 | break; |
| 1460 | ) < 0) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1461 | gf100_gr_ctxctl_debug(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1462 | return -EBUSY; |
| 1463 | } |
| 1464 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1465 | gr->size = nvkm_rd32(device, 0x409804); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1466 | if (gr->data == NULL) { |
| 1467 | int ret = gf100_grctx_generate(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1468 | if (ret) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1469 | nvkm_error(subdev, "failed to construct context\n"); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1470 | return ret; |
| 1471 | } |
| 1472 | } |
| 1473 | |
| 1474 | return 0; |
| 1475 | } |
| 1476 | |
| 1477 | int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1478 | gf100_gr_init(struct nvkm_object *object) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1479 | { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1480 | struct gf100_gr *gr = (void *)object; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1481 | struct nvkm_device *device = gr->base.engine.subdev.device; |
| 1482 | struct gf100_gr_oclass *oclass = (void *)object->oclass; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1483 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1484 | u32 data[TPC_MAX / 8] = {}; |
| 1485 | u8 tpcnr[GPC_MAX]; |
| 1486 | int gpc, tpc, rop; |
| 1487 | int ret, i; |
| 1488 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1489 | ret = nvkm_gr_init(&gr->base); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1490 | if (ret) |
| 1491 | return ret; |
| 1492 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1493 | nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); |
| 1494 | nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); |
| 1495 | nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); |
| 1496 | nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); |
| 1497 | nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); |
| 1498 | nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1499 | nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); |
| 1500 | nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1501 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1502 | gf100_gr_mmio(gr, oclass->mmio); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1503 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1504 | memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); |
| 1505 | for (i = 0, gpc = -1; i < gr->tpc_total; i++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1506 | do { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1507 | gpc = (gpc + 1) % gr->gpc_nr; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1508 | } while (!tpcnr[gpc]); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1509 | tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1510 | |
| 1511 | data[i / 8] |= tpc << ((i % 8) * 4); |
| 1512 | } |
| 1513 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1514 | nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); |
| 1515 | nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); |
| 1516 | nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); |
| 1517 | nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1518 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1519 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1520 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1521 | gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1522 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1523 | gr->tpc_total); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1524 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1525 | } |
| 1526 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1527 | if (nv_device(gr)->chipset != 0xd7) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1528 | nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1529 | else |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1530 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1531 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1532 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1533 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1534 | nvkm_wr32(device, 0x400500, 0x00010001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1535 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1536 | nvkm_wr32(device, 0x400100, 0xffffffff); |
| 1537 | nvkm_wr32(device, 0x40013c, 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1538 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1539 | nvkm_wr32(device, 0x409c24, 0x000f0000); |
| 1540 | nvkm_wr32(device, 0x404000, 0xc0000000); |
| 1541 | nvkm_wr32(device, 0x404600, 0xc0000000); |
| 1542 | nvkm_wr32(device, 0x408030, 0xc0000000); |
| 1543 | nvkm_wr32(device, 0x40601c, 0xc0000000); |
| 1544 | nvkm_wr32(device, 0x404490, 0xc0000000); |
| 1545 | nvkm_wr32(device, 0x406018, 0xc0000000); |
| 1546 | nvkm_wr32(device, 0x405840, 0xc0000000); |
| 1547 | nvkm_wr32(device, 0x405844, 0x00ffffff); |
| 1548 | nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); |
| 1549 | nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1550 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1551 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1552 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
| 1553 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
| 1554 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
| 1555 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1556 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1557 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); |
| 1558 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); |
| 1559 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); |
| 1560 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); |
| 1561 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); |
| 1562 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); |
| 1563 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1564 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1565 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); |
| 1566 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1567 | } |
| 1568 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1569 | for (rop = 0; rop < gr->rop_nr; rop++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1570 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); |
| 1571 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); |
| 1572 | nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); |
| 1573 | nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1574 | } |
| 1575 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1576 | nvkm_wr32(device, 0x400108, 0xffffffff); |
| 1577 | nvkm_wr32(device, 0x400138, 0xffffffff); |
| 1578 | nvkm_wr32(device, 0x400118, 0xffffffff); |
| 1579 | nvkm_wr32(device, 0x400130, 0xffffffff); |
| 1580 | nvkm_wr32(device, 0x40011c, 0xffffffff); |
| 1581 | nvkm_wr32(device, 0x400134, 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1582 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1583 | nvkm_wr32(device, 0x400054, 0x34ce3464); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1584 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1585 | gf100_gr_zbc_init(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1586 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1587 | return gf100_gr_init_ctxctl(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1588 | } |
| 1589 | |
Alexandre Courbot | c4d0f8f | 2015-06-23 15:16:02 +0900 | [diff] [blame] | 1590 | void |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1591 | gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1592 | { |
| 1593 | kfree(fuc->data); |
| 1594 | fuc->data = NULL; |
| 1595 | } |
| 1596 | |
| 1597 | int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1598 | gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1599 | struct gf100_gr_fuc *fuc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1600 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1601 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1602 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1603 | const struct firmware *fw; |
Alexandre Courbot | 8539b37 | 2015-06-23 15:16:01 +0900 | [diff] [blame] | 1604 | char f[64]; |
| 1605 | char cname[16]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1606 | int ret; |
Alexandre Courbot | 8539b37 | 2015-06-23 15:16:01 +0900 | [diff] [blame] | 1607 | int i; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1608 | |
Alexandre Courbot | 8539b37 | 2015-06-23 15:16:01 +0900 | [diff] [blame] | 1609 | /* Convert device name to lowercase */ |
Ben Skeggs | 6cf813f | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1610 | strncpy(cname, device->chip->name, sizeof(cname)); |
Alexandre Courbot | 8539b37 | 2015-06-23 15:16:01 +0900 | [diff] [blame] | 1611 | cname[sizeof(cname) - 1] = '\0'; |
| 1612 | i = strlen(cname); |
| 1613 | while (i) { |
| 1614 | --i; |
| 1615 | cname[i] = tolower(cname[i]); |
| 1616 | } |
| 1617 | |
| 1618 | snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1619 | ret = request_firmware(&fw, f, nv_device_base(device)); |
| 1620 | if (ret) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1621 | nvkm_error(subdev, "failed to load %s\n", fwname); |
Alexandre Courbot | 8539b37 | 2015-06-23 15:16:01 +0900 | [diff] [blame] | 1622 | return ret; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1623 | } |
| 1624 | |
| 1625 | fuc->size = fw->size; |
| 1626 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); |
| 1627 | release_firmware(fw); |
| 1628 | return (fuc->data != NULL) ? 0 : -ENOMEM; |
| 1629 | } |
| 1630 | |
| 1631 | void |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1632 | gf100_gr_dtor(struct nvkm_object *object) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1633 | { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1634 | struct gf100_gr *gr = (void *)object; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1635 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1636 | kfree(gr->data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1637 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1638 | gf100_gr_dtor_fw(&gr->fuc409c); |
| 1639 | gf100_gr_dtor_fw(&gr->fuc409d); |
| 1640 | gf100_gr_dtor_fw(&gr->fuc41ac); |
| 1641 | gf100_gr_dtor_fw(&gr->fuc41ad); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1642 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1643 | nvkm_memory_del(&gr->unk4188b8); |
| 1644 | nvkm_memory_del(&gr->unk4188b4); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1645 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1646 | nvkm_gr_destroy(&gr->base); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1647 | } |
| 1648 | |
| 1649 | int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1650 | gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 1651 | struct nvkm_oclass *bclass, void *data, u32 size, |
| 1652 | struct nvkm_object **pobject) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1653 | { |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1654 | struct gf100_gr_oclass *oclass = (void *)bclass; |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1655 | struct nvkm_device *device = (void *)parent; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1656 | struct gf100_gr *gr; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1657 | bool use_ext_fw, enable; |
| 1658 | int ret, i, j; |
| 1659 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1660 | use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", |
| 1661 | oclass->fecs.ucode == NULL); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1662 | enable = use_ext_fw || oclass->fecs.ucode != NULL; |
| 1663 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1664 | ret = nvkm_gr_create(parent, engine, bclass, enable, &gr); |
| 1665 | *pobject = nv_object(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1666 | if (ret) |
| 1667 | return ret; |
| 1668 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1669 | nv_subdev(gr)->unit = 0x08001000; |
| 1670 | nv_subdev(gr)->intr = gf100_gr_intr; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1671 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1672 | gr->base.units = gf100_gr_units; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1673 | |
| 1674 | if (use_ext_fw) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1675 | nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1676 | if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || |
| 1677 | gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || |
| 1678 | gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || |
| 1679 | gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1680 | return -ENODEV; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1681 | gr->firmware = true; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1682 | } |
| 1683 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1684 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1685 | &gr->unk4188b4); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1686 | if (ret) |
| 1687 | return ret; |
| 1688 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1689 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1690 | &gr->unk4188b8); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1691 | if (ret) |
| 1692 | return ret; |
| 1693 | |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 1694 | nvkm_kmap(gr->unk4188b4); |
| 1695 | for (i = 0; i < 0x1000; i += 4) |
| 1696 | nvkm_wo32(gr->unk4188b4, i, 0x00000010); |
| 1697 | nvkm_done(gr->unk4188b4); |
| 1698 | |
| 1699 | nvkm_kmap(gr->unk4188b8); |
| 1700 | for (i = 0; i < 0x1000; i += 4) |
| 1701 | nvkm_wo32(gr->unk4188b8, i, 0x00000010); |
| 1702 | nvkm_done(gr->unk4188b8); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1703 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1704 | gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; |
| 1705 | gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1706 | for (i = 0; i < gr->gpc_nr; i++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1707 | gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1708 | gr->tpc_total += gr->tpc_nr[i]; |
| 1709 | gr->ppc_nr[i] = oclass->ppc_nr; |
| 1710 | for (j = 0; j < gr->ppc_nr[i]; j++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1711 | u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1712 | gr->ppc_tpc_nr[i][j] = hweight8(mask); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1713 | } |
| 1714 | } |
| 1715 | |
| 1716 | /*XXX: these need figuring out... though it might not even matter */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1717 | switch (nv_device(gr)->chipset) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1718 | case 0xc0: |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1719 | if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ |
| 1720 | gr->magic_not_rop_nr = 0x07; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1721 | } else |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1722 | if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ |
| 1723 | gr->magic_not_rop_nr = 0x05; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1724 | } else |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1725 | if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ |
| 1726 | gr->magic_not_rop_nr = 0x06; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1727 | } |
| 1728 | break; |
| 1729 | case 0xc3: /* 450, 4/0/0/0, 2 */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1730 | gr->magic_not_rop_nr = 0x03; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1731 | break; |
| 1732 | case 0xc4: /* 460, 3/4/0/0, 4 */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1733 | gr->magic_not_rop_nr = 0x01; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1734 | break; |
| 1735 | case 0xc1: /* 2/0/0/0, 1 */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1736 | gr->magic_not_rop_nr = 0x01; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1737 | break; |
| 1738 | case 0xc8: /* 4/4/3/4, 5 */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1739 | gr->magic_not_rop_nr = 0x06; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1740 | break; |
| 1741 | case 0xce: /* 4/4/0/0, 4 */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1742 | gr->magic_not_rop_nr = 0x03; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1743 | break; |
| 1744 | case 0xcf: /* 4/0/0/0, 3 */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1745 | gr->magic_not_rop_nr = 0x03; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1746 | break; |
| 1747 | case 0xd7: |
| 1748 | case 0xd9: /* 1/0/0/0, 1 */ |
Alexandre Courbot | c4d0f8f | 2015-06-23 15:16:02 +0900 | [diff] [blame] | 1749 | case 0xea: /* gk20a */ |
Alexandre Courbot | a032fb9 | 2015-06-23 15:16:04 +0900 | [diff] [blame] | 1750 | case 0x12b: /* gm20b */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1751 | gr->magic_not_rop_nr = 0x01; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1752 | break; |
| 1753 | } |
| 1754 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1755 | nv_engine(gr)->cclass = *oclass->cclass; |
| 1756 | nv_engine(gr)->sclass = oclass->sclass; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1757 | return 0; |
| 1758 | } |
| 1759 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1760 | #include "fuc/hubgf100.fuc3.h" |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1761 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1762 | struct gf100_gr_ucode |
| 1763 | gf100_gr_fecs_ucode = { |
| 1764 | .code.data = gf100_grhub_code, |
| 1765 | .code.size = sizeof(gf100_grhub_code), |
| 1766 | .data.data = gf100_grhub_data, |
| 1767 | .data.size = sizeof(gf100_grhub_data), |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1768 | }; |
| 1769 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1770 | #include "fuc/gpcgf100.fuc3.h" |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1771 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1772 | struct gf100_gr_ucode |
| 1773 | gf100_gr_gpccs_ucode = { |
| 1774 | .code.data = gf100_grgpc_code, |
| 1775 | .code.size = sizeof(gf100_grgpc_code), |
| 1776 | .data.data = gf100_grgpc_data, |
| 1777 | .data.size = sizeof(gf100_grgpc_data), |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1778 | }; |
| 1779 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1780 | struct nvkm_oclass * |
| 1781 | gf100_gr_oclass = &(struct gf100_gr_oclass) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1782 | .base.handle = NV_ENGINE(GR, 0xc0), |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1783 | .base.ofuncs = &(struct nvkm_ofuncs) { |
| 1784 | .ctor = gf100_gr_ctor, |
| 1785 | .dtor = gf100_gr_dtor, |
| 1786 | .init = gf100_gr_init, |
| 1787 | .fini = _nvkm_gr_fini, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1788 | }, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1789 | .cclass = &gf100_grctx_oclass, |
| 1790 | .sclass = gf100_gr_sclass, |
| 1791 | .mmio = gf100_gr_pack_mmio, |
| 1792 | .fecs.ucode = &gf100_gr_fecs_ucode, |
| 1793 | .gpccs.ucode = &gf100_gr_gpccs_ucode, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1794 | }.base; |