blob: 951b620bfa73e725d0858329b9f3b2e62aeaa3a1 [file] [log] [blame]
Kevin Hilman7c6337e2007-04-30 19:37:19 +01001/*
2 * TI DaVinci serial driver
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/serial_8250.h>
25#include <linux/serial_reg.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010029#include <linux/io.h>
Kevin Hilman7c6337e2007-04-30 19:37:19 +010030
Russell Kinga09e64f2008-08-05 16:14:15 +010031#include <mach/serial.h>
Kevin Hilman617b9252009-04-14 08:04:26 -050032#include <mach/cputype.h>
Kevin Hilman7c6337e2007-04-30 19:37:19 +010033
Kevin Hilman617b9252009-04-14 08:04:26 -050034static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
35 int value)
Kevin Hilman7c6337e2007-04-30 19:37:19 +010036{
37 offset <<= p->regshift;
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -040038
39 WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
40
41 __raw_writel(value, p->membase + offset);
Kevin Hilman7c6337e2007-04-30 19:37:19 +010042}
43
Kevin Hilman7c6337e2007-04-30 19:37:19 +010044static void __init davinci_serial_reset(struct plat_serial8250_port *p)
45{
Kevin Hilman7c6337e2007-04-30 19:37:19 +010046 unsigned int pwremu = 0;
47
Kevin Hilman617b9252009-04-14 08:04:26 -050048 serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
Kevin Hilman7c6337e2007-04-30 19:37:19 +010049
Kevin Hilman617b9252009-04-14 08:04:26 -050050 /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
51 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
Kevin Hilman7c6337e2007-04-30 19:37:19 +010052 mdelay(10);
53
54 pwremu |= (0x3 << 13);
55 pwremu |= 0x1;
Kevin Hilman617b9252009-04-14 08:04:26 -050056 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
57
58 if (cpu_is_davinci_dm646x())
59 serial_write_reg(p, UART_DM646X_SCR,
60 UART_DM646X_SCR_TX_WATERMARK);
61}
62
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +053063int __init davinci_serial_init(struct platform_device *serial_dev)
Kevin Hilman617b9252009-04-14 08:04:26 -050064{
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053065 int i, ret = 0;
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053066 struct device *dev;
67 struct plat_serial8250_port *p;
Manjunathappa, Prakash323761bb2013-06-19 14:45:42 +053068 struct clk *clk;
Kevin Hilman617b9252009-04-14 08:04:26 -050069
70 /*
71 * Make sure the serial ports are muxed on at this point.
Mark A. Greer65e866a2009-03-18 12:36:08 -050072 * You have to mux them off in device drivers later on if not needed.
Kevin Hilman617b9252009-04-14 08:04:26 -050073 */
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +053074 for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
75 dev = &serial_dev[i].dev;
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053076 p = dev->platform_data;
Kevin Hilman617b9252009-04-14 08:04:26 -050077
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +053078 ret = platform_device_register(&serial_dev[i]);
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053079 if (ret)
80 continue;
81
Manjunathappa, Prakash323761bb2013-06-19 14:45:42 +053082 clk = clk_get(dev, NULL);
83 if (IS_ERR(clk)) {
84 pr_err("%s:%d: failed to get UART%d clock\n",
85 __func__, __LINE__, i);
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -040086 continue;
Manjunathappa, Prakash323761bb2013-06-19 14:45:42 +053087 }
88
89 clk_prepare_enable(clk);
90
91 p->uartclk = clk_get_rate(clk);
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -040092
93 if (!p->membase && p->mapbase) {
94 p->membase = ioremap(p->mapbase, SZ_4K);
95
96 if (p->membase)
97 p->flags &= ~UPF_IOREMAP;
98 else
99 pr_err("uart regs ioremap failed\n");
100 }
101
Cyril Chemparathye2800002010-05-02 14:28:14 -0400102 if (p->membase && p->type != PORT_AR7)
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -0400103 davinci_serial_reset(p);
Kevin Hilman617b9252009-04-14 08:04:26 -0500104 }
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530105 return ret;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100106}