Linus Walleij | 1e22a8c | 2013-03-19 15:36:12 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2010-2013 |
| 3 | * Author: Rickard Andersson <rickard.andersson@stericsson.com> for |
| 4 | * ST-Ericsson. |
| 5 | * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. |
Ulf Hansson | ead9e29 | 2013-12-18 15:59:37 +0100 | [diff] [blame] | 6 | * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro. |
| 7 | * |
Linus Walleij | 1e22a8c | 2013-03-19 15:36:12 +0100 | [diff] [blame] | 8 | * License terms: GNU General Public License (GPL) version 2 |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/irqchip/arm-gic.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/io.h> |
Ulf Hansson | ead9e29 | 2013-12-18 15:59:37 +0100 | [diff] [blame] | 16 | #include <linux/suspend.h> |
Linus Walleij | 1e22a8c | 2013-03-19 15:36:12 +0100 | [diff] [blame] | 17 | #include <linux/platform_data/arm-ux500-pm.h> |
| 18 | |
Linus Walleij | 174e779 | 2013-03-19 15:41:55 +0100 | [diff] [blame] | 19 | #include "db8500-regs.h" |
Ulf Hansson | cd931dc | 2014-10-14 11:12:56 +0200 | [diff] [blame] | 20 | #include "pm_domains.h" |
Linus Walleij | 1e22a8c | 2013-03-19 15:36:12 +0100 | [diff] [blame] | 21 | |
| 22 | /* ARM WFI Standby signal register */ |
| 23 | #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) |
| 24 | #define PRCM_ARM_WFI_STANDBY_WFI0 0x08 |
| 25 | #define PRCM_ARM_WFI_STANDBY_WFI1 0x10 |
| 26 | #define PRCM_IOCR (prcmu_base + 0x310) |
| 27 | #define PRCM_IOCR_IOFORCE 0x1 |
| 28 | |
| 29 | /* Dual A9 core interrupt management unit registers */ |
| 30 | #define PRCM_A9_MASK_REQ (prcmu_base + 0x328) |
| 31 | #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 |
| 32 | |
| 33 | #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) |
| 34 | #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) |
| 35 | #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) |
| 36 | #define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) |
| 37 | #define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) |
| 38 | #define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) |
| 39 | #define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) |
| 40 | #define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) |
| 41 | #define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) |
| 42 | #define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) |
| 43 | |
| 44 | static void __iomem *prcmu_base; |
| 45 | |
| 46 | /* This function decouple the gic from the prcmu */ |
| 47 | int prcmu_gic_decouple(void) |
| 48 | { |
| 49 | u32 val = readl(PRCM_A9_MASK_REQ); |
| 50 | |
| 51 | /* Set bit 0 register value to 1 */ |
| 52 | writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, |
| 53 | PRCM_A9_MASK_REQ); |
| 54 | |
| 55 | /* Make sure the register is updated */ |
| 56 | readl(PRCM_A9_MASK_REQ); |
| 57 | |
| 58 | /* Wait a few cycles for the gic mask completion */ |
| 59 | udelay(1); |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | /* This function recouple the gic with the prcmu */ |
| 65 | int prcmu_gic_recouple(void) |
| 66 | { |
| 67 | u32 val = readl(PRCM_A9_MASK_REQ); |
| 68 | |
| 69 | /* Set bit 0 register value to 0 */ |
| 70 | writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | #define PRCMU_GIC_NUMBER_REGS 5 |
| 76 | |
| 77 | /* |
| 78 | * This function checks if there are pending irq on the gic. It only |
| 79 | * makes sense if the gic has been decoupled before with the |
| 80 | * db8500_prcmu_gic_decouple function. Disabling an interrupt only |
| 81 | * disables the forwarding of the interrupt to any CPU interface. It |
| 82 | * does not prevent the interrupt from changing state, for example |
| 83 | * becoming pending, or active and pending if it is already |
| 84 | * active. Hence, we have to check the interrupt is pending *and* is |
| 85 | * active. |
| 86 | */ |
| 87 | bool prcmu_gic_pending_irq(void) |
| 88 | { |
| 89 | u32 pr; /* Pending register */ |
| 90 | u32 er; /* Enable register */ |
| 91 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); |
| 92 | int i; |
| 93 | |
| 94 | /* 5 registers. STI & PPI not skipped */ |
| 95 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { |
| 96 | |
| 97 | pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); |
| 98 | er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 99 | |
| 100 | if (pr & er) |
| 101 | return true; /* There is a pending interrupt */ |
| 102 | } |
| 103 | |
| 104 | return false; |
| 105 | } |
| 106 | |
| 107 | /* |
| 108 | * This function checks if there are pending interrupt on the |
| 109 | * prcmu which has been delegated to monitor the irqs with the |
| 110 | * db8500_prcmu_copy_gic_settings function. |
| 111 | */ |
| 112 | bool prcmu_pending_irq(void) |
| 113 | { |
| 114 | u32 it, im; |
| 115 | int i; |
| 116 | |
| 117 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { |
| 118 | it = readl(PRCM_ARMITVAL31TO0 + i * 4); |
| 119 | im = readl(PRCM_ARMITMSK31TO0 + i * 4); |
| 120 | if (it & im) |
| 121 | return true; /* There is a pending interrupt */ |
| 122 | } |
| 123 | |
| 124 | return false; |
| 125 | } |
| 126 | |
| 127 | /* |
| 128 | * This function checks if the specified cpu is in in WFI. It's usage |
| 129 | * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple |
| 130 | * function. Of course passing smp_processor_id() to this function will |
| 131 | * always return false... |
| 132 | */ |
| 133 | bool prcmu_is_cpu_in_wfi(int cpu) |
| 134 | { |
| 135 | return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : |
| 136 | PRCM_ARM_WFI_STANDBY_WFI0; |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | * This function copies the gic SPI settings to the prcmu in order to |
| 141 | * monitor them and abort/finish the retention/off sequence or state. |
| 142 | */ |
| 143 | int prcmu_copy_gic_settings(void) |
| 144 | { |
| 145 | u32 er; /* Enable register */ |
| 146 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); |
| 147 | int i; |
| 148 | |
| 149 | /* We skip the STI and PPI */ |
| 150 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { |
| 151 | er = readl_relaxed(dist_base + |
| 152 | GIC_DIST_ENABLE_SET + (i + 1) * 4); |
| 153 | writel(er, PRCM_ARMITMSK31TO0 + i * 4); |
| 154 | } |
| 155 | |
| 156 | return 0; |
| 157 | } |
| 158 | |
Ulf Hansson | ead9e29 | 2013-12-18 15:59:37 +0100 | [diff] [blame] | 159 | #ifdef CONFIG_SUSPEND |
| 160 | static int ux500_suspend_enter(suspend_state_t state) |
| 161 | { |
| 162 | cpu_do_idle(); |
| 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | static int ux500_suspend_valid(suspend_state_t state) |
| 167 | { |
| 168 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; |
| 169 | } |
| 170 | |
| 171 | static const struct platform_suspend_ops ux500_suspend_ops = { |
| 172 | .enter = ux500_suspend_enter, |
| 173 | .valid = ux500_suspend_valid, |
| 174 | }; |
| 175 | #define UX500_SUSPEND_OPS (&ux500_suspend_ops) |
| 176 | #else |
| 177 | #define UX500_SUSPEND_OPS NULL |
| 178 | #endif |
| 179 | |
Linus Walleij | 1e22a8c | 2013-03-19 15:36:12 +0100 | [diff] [blame] | 180 | void __init ux500_pm_init(u32 phy_base, u32 size) |
| 181 | { |
| 182 | prcmu_base = ioremap(phy_base, size); |
| 183 | if (!prcmu_base) { |
| 184 | pr_err("could not remap PRCMU for PM functions\n"); |
| 185 | return; |
| 186 | } |
| 187 | /* |
| 188 | * On watchdog reboot the GIC is in some cases decoupled. |
| 189 | * This will make sure that the GIC is correctly configured. |
| 190 | */ |
| 191 | prcmu_gic_recouple(); |
Ulf Hansson | ead9e29 | 2013-12-18 15:59:37 +0100 | [diff] [blame] | 192 | |
| 193 | /* Set up ux500 suspend callbacks. */ |
| 194 | suspend_set_ops(UX500_SUSPEND_OPS); |
Ulf Hansson | cd931dc | 2014-10-14 11:12:56 +0200 | [diff] [blame] | 195 | |
| 196 | /* Initialize ux500 power domains */ |
| 197 | ux500_pm_domains_init(); |
Linus Walleij | 1e22a8c | 2013-03-19 15:36:12 +0100 | [diff] [blame] | 198 | } |