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gerrit-public.fairphone.software / kernel / msm-4.9 / 8f0fc088f5fff0c2e4683bc0de7fc849e7d5357a / . / arch / blackfin / mach-bf533 / include / mach / mem_map.h
blob: 197af1a398ac83add512ff366bf2eb925383d403 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1/*
Mike Frysingerfa48f842009-06-17 11:25:06 -0400[diff] [blame]2 * BF533 memory map
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]3 *
Mike Frysingerfa48f842009-06-17 11:25:06 -0400[diff] [blame]4 * Copyright 2004-2009 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]6 */
7
Mike Frysingerfa48f842009-06-17 11:25:06 -0400[diff] [blame]8#ifndef __BFIN_MACH_MEM_MAP_H__
9#define __BFIN_MACH_MEM_MAP_H__
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]10
Mike Frysingerfa48f842009-06-17 11:25:06 -0400[diff] [blame]11#ifndef __BFIN_MEM_MAP_H__
12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]14
15/* Async Memory Banks */
16#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
17#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
18#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
19#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
20#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
21#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
22#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
23#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
24
25/* Boot ROM Memory */
26
27#define BOOT_ROM_START 0xEF000000
Mike Frysingerc3a9f432007-11-21 16:12:12 +0800[diff] [blame]28#define BOOT_ROM_LENGTH 0x400
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]29
30/* Level 1 Memory */
31
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]32#ifdef CONFIG_BFIN_ICACHE
33#define BFIN_ICACHESIZE (16*1024)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]34#else
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]35#define BFIN_ICACHESIZE (0*1024)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]36#endif
37
38/* Memory Map for ADSP-BF533 processors */
39
40#ifdef CONFIG_BF533
41#define L1_CODE_START 0xFFA00000
42#define L1_DATA_A_START 0xFF800000
43#define L1_DATA_B_START 0xFF900000
44
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]45#ifdef CONFIG_BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]46#define L1_CODE_LENGTH (0x14000 - 0x4000)
47#else
48#define L1_CODE_LENGTH 0x14000
49#endif
50
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]51#ifdef CONFIG_BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]52
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]53#ifdef CONFIG_BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]54#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
55#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
56#define L1_DATA_B_LENGTH 0x8000
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]57#define BFIN_DCACHESIZE (16*1024)
58#define BFIN_DSUPBANKS 1
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]59#else
60#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
61#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
62#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]63#define BFIN_DCACHESIZE (32*1024)
64#define BFIN_DSUPBANKS 2
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]65#endif
66
67#else
68#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
69#define L1_DATA_A_LENGTH 0x8000
70#define L1_DATA_B_LENGTH 0x8000
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]71#define BFIN_DCACHESIZE (0*1024)
72#define BFIN_DSUPBANKS 0
73#endif /*CONFIG_BFIN_DCACHE*/
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]74#endif
75
76/* Memory Map for ADSP-BF532 processors */
77
78#ifdef CONFIG_BF532
79#define L1_CODE_START 0xFFA08000
80#define L1_DATA_A_START 0xFF804000
81#define L1_DATA_B_START 0xFF904000
82
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]83#ifdef CONFIG_BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]84#define L1_CODE_LENGTH (0xC000 - 0x4000)
85#else
86#define L1_CODE_LENGTH 0xC000
87#endif
88
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]89#ifdef CONFIG_BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]90
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]91#ifdef CONFIG_BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]92#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
93#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
94#define L1_DATA_B_LENGTH 0x4000
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]95#define BFIN_DCACHESIZE (16*1024)
96#define BFIN_DSUPBANKS 1
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]97
98#else
99#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
100#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
101#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]102#define BFIN_DCACHESIZE (32*1024)
103#define BFIN_DSUPBANKS 2
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]104#endif
105
106#else
107#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
108#define L1_DATA_A_LENGTH 0x4000
109#define L1_DATA_B_LENGTH 0x4000
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]110#define BFIN_DCACHESIZE (0*1024)
111#define BFIN_DSUPBANKS 0
112#endif /*CONFIG_BFIN_DCACHE*/
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]113#endif
114
115/* Memory Map for ADSP-BF531 processors */
116
117#ifdef CONFIG_BF531
118#define L1_CODE_START 0xFFA08000
119#define L1_DATA_A_START 0xFF804000
120#define L1_DATA_B_START 0xFF904000
121#define L1_CODE_LENGTH 0x4000
122#define L1_DATA_B_LENGTH 0x0000
123
124
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]125#ifdef CONFIG_BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]126#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
127#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]128#define BFIN_DCACHESIZE (16*1024)
129#define BFIN_DSUPBANKS 1
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]130#else
131#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
132#define L1_DATA_A_LENGTH 0x4000
Robin Getz3bebca22007-10-10 23:55:26 +0800[diff] [blame]133#define BFIN_DCACHESIZE (0*1024)
134#define BFIN_DSUPBANKS 0
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]135#endif
136
137#endif
138
Mike Frysingerfa48f842009-06-17 11:25:06 -0400[diff] [blame]139#endif