blob: 4a70be485ff8fe68fd96a9544ac73117d0f27857 [file] [log] [blame]
Rob Herring61727632012-09-06 13:43:04 -05001config ARCH_VEXPRESS
2 bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
Pawel Moll38669e02012-10-09 12:56:36 +01003 select ARCH_REQUIRE_GPIOLIB
Ben Dooks98dec912013-05-28 21:34:50 +01004 select ARCH_SUPPORTS_BIG_ENDIAN
Rob Herring61727632012-09-06 13:43:04 -05005 select ARM_AMBA
6 select ARM_GIC
7 select ARM_TIMER_SP804
Rob Herring61727632012-09-06 13:43:04 -05008 select COMMON_CLK
Pawel Moll38669e02012-10-09 12:56:36 +01009 select COMMON_CLK_VERSATILE
Rob Herring61727632012-09-06 13:43:04 -050010 select CPU_V7
11 select GENERIC_CLOCKEVENTS
Stephen Boyd4c3ffff2013-02-27 15:28:14 -080012 select HAVE_ARM_SCU if SMP
Stephen Boyda894fcc2013-02-15 16:02:20 -080013 select HAVE_ARM_TWD if SMP
Rob Herring61727632012-09-06 13:43:04 -050014 select HAVE_PATA_PLATFORM
15 select HAVE_SMP
16 select ICST
17 select MIGHT_HAVE_CACHE_L2X0
18 select NO_IOPORT
19 select PLAT_VERSATILE
20 select PLAT_VERSATILE_CLCD
Catalin Marinas2655f512013-01-15 11:24:14 +000021 select POWER_RESET
22 select POWER_RESET_VEXPRESS
23 select POWER_SUPPLY
Rob Herring61727632012-09-06 13:43:04 -050024 select REGULATOR_FIXED_VOLTAGE if REGULATOR
Pawel Moll38669e02012-10-09 12:56:36 +010025 select VEXPRESS_CONFIG
Rob Herring61727632012-09-06 13:43:04 -050026 help
27 This option enables support for systems using Cortex processor based
28 ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
29 for example:
30
31 - CoreTile Express A5x2 (V2P-CA5s)
32 - CoreTile Express A9x4 (V2P-CA9)
33 - CoreTile Express A15x2 (V2P-CA15)
34 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
35 (Soft Macrocell Models)
36 - Versatile Express RTSMs (Models)
37
38 You must boot using a Flattened Device Tree in order to use these
39 platforms. The traditional (ATAGs) boot method is not usable on
40 these boards with this option.
41
Russell Kingceade892010-02-11 21:44:53 +000042menu "Versatile Express platform type"
43 depends on ARCH_VEXPRESS
44
Pawel Moll8deed172012-02-23 13:04:51 +000045config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
Will Deaconef591192012-07-04 16:01:16 +010046 bool "Enable A5 and A9 only errata work-arounds"
47 default y
Will Deacon3de4ade2011-02-21 19:12:27 +010048 select ARM_ERRATA_720789
Pawel Moll8deed172012-02-23 13:04:51 +000049 select PL310_ERRATA_753970 if CACHE_PL310
50 help
51 Provides common dependencies for Versatile Express platforms
52 based on Cortex-A5 and Cortex-A9 processors. In order to
53 build a working kernel, you must also enable relevant core
54 tile support or Flattened Device Tree based support options.
55
56config ARCH_VEXPRESS_CA9X4
57 bool "Versatile Express Cortex-A9x4 tile"
Pawel Moll8deed172012-02-23 13:04:51 +000058
Nicolas Pitre1e904e12012-05-02 20:56:52 -040059config ARCH_VEXPRESS_DCSCB
60 bool "Dual Cluster System Control Block (DCSCB) support"
61 depends on MCPM
Dave Martind41418c02012-07-17 14:25:44 +010062 select ARM_CCI
Nicolas Pitre1e904e12012-05-02 20:56:52 -040063 help
64 Support for the Dual Cluster System Configuration Block (DCSCB).
65 This is needed to provide CPU and cluster power management
66 on RTSM implementing big.LITTLE.
67
Sudeep KarkadaNageshaf7cd2d82013-10-29 12:18:37 +000068config ARCH_VEXPRESS_SPC
69 bool "Versatile Express Serial Power Controller (SPC)"
70 select ARCH_HAS_CPUFREQ
71 select ARCH_HAS_OPP
72 select PM_OPP
73 help
74 The TC2 (A15x2 A7x3) versatile express core tile integrates a logic
75 block called Serial Power Controller (SPC) that provides the interface
76 between the dual cluster test-chip and the M3 microcontroller that
77 carries out power management.
78
Nicolas Pitre11b277e2013-08-06 19:10:08 +010079config ARCH_VEXPRESS_TC2_PM
80 bool "Versatile Express TC2 power management"
81 depends on MCPM
82 select ARM_CCI
Sudeep KarkadaNageshaf7cd2d82013-10-29 12:18:37 +000083 select ARCH_VEXPRESS_SPC
Nicolas Pitre11b277e2013-08-06 19:10:08 +010084 help
85 Support for CPU and cluster power management on Versatile Express
86 with a TC2 (A15x2 A7x3) big.LITTLE core tile.
87
Russell Kingceade892010-02-11 21:44:53 +000088endmenu