Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2010 Daniel Vetter |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 25 | #include <drm/drmP.h> |
| 26 | #include <drm/i915_drm.h> |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 27 | #include "i915_drv.h" |
| 28 | #include "i915_trace.h" |
| 29 | #include "intel_drv.h" |
| 30 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 31 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
| 32 | static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
| 33 | unsigned first_entry, |
| 34 | unsigned num_entries) |
| 35 | { |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 36 | uint32_t *pt_vaddr; |
| 37 | uint32_t scratch_pte; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 38 | unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; |
| 39 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
| 40 | unsigned last_pte, i; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 41 | |
| 42 | scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr); |
| 43 | scratch_pte |= GEN6_PTE_VALID | GEN6_PTE_CACHE_LLC; |
| 44 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 45 | while (num_entries) { |
| 46 | last_pte = first_pte + num_entries; |
| 47 | if (last_pte > I915_PPGTT_PT_ENTRIES) |
| 48 | last_pte = I915_PPGTT_PT_ENTRIES; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 49 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 50 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]); |
| 51 | |
| 52 | for (i = first_pte; i < last_pte; i++) |
| 53 | pt_vaddr[i] = scratch_pte; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 54 | |
| 55 | kunmap_atomic(pt_vaddr); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 56 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 57 | num_entries -= last_pte - first_pte; |
| 58 | first_pte = 0; |
| 59 | act_pd++; |
| 60 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) |
| 64 | { |
| 65 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 66 | struct i915_hw_ppgtt *ppgtt; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 67 | unsigned first_pd_entry_in_global_pt; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 68 | int i; |
| 69 | int ret = -ENOMEM; |
| 70 | |
| 71 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 |
| 72 | * entries. For aliasing ppgtt support we just steal them at the end for |
| 73 | * now. */ |
Chris Wilson | 9a0f938 | 2012-08-24 09:12:22 +0100 | [diff] [blame] | 74 | first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 75 | |
| 76 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 77 | if (!ppgtt) |
| 78 | return ret; |
| 79 | |
Ben Widawsky | 8f2c59f | 2012-09-24 08:55:51 -0700 | [diff] [blame^] | 80 | ppgtt->dev = dev; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 81 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
| 82 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
| 83 | GFP_KERNEL); |
| 84 | if (!ppgtt->pt_pages) |
| 85 | goto err_ppgtt; |
| 86 | |
| 87 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 88 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); |
| 89 | if (!ppgtt->pt_pages[i]) |
| 90 | goto err_pt_alloc; |
| 91 | } |
| 92 | |
| 93 | if (dev_priv->mm.gtt->needs_dmar) { |
| 94 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) |
| 95 | *ppgtt->num_pd_entries, |
| 96 | GFP_KERNEL); |
| 97 | if (!ppgtt->pt_dma_addr) |
| 98 | goto err_pt_alloc; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 99 | |
Daniel Vetter | 211c568 | 2012-04-10 17:29:17 +0200 | [diff] [blame] | 100 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 101 | dma_addr_t pt_addr; |
| 102 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 103 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], |
| 104 | 0, 4096, |
| 105 | PCI_DMA_BIDIRECTIONAL); |
| 106 | |
| 107 | if (pci_dma_mapping_error(dev->pdev, |
| 108 | pt_addr)) { |
| 109 | ret = -EIO; |
| 110 | goto err_pd_pin; |
| 111 | |
| 112 | } |
| 113 | ppgtt->pt_dma_addr[i] = pt_addr; |
Daniel Vetter | 211c568 | 2012-04-10 17:29:17 +0200 | [diff] [blame] | 114 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 115 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 116 | |
| 117 | ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma; |
| 118 | |
| 119 | i915_ppgtt_clear_range(ppgtt, 0, |
| 120 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); |
| 121 | |
| 122 | ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(uint32_t); |
| 123 | |
| 124 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
| 125 | |
| 126 | return 0; |
| 127 | |
| 128 | err_pd_pin: |
| 129 | if (ppgtt->pt_dma_addr) { |
| 130 | for (i--; i >= 0; i--) |
| 131 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], |
| 132 | 4096, PCI_DMA_BIDIRECTIONAL); |
| 133 | } |
| 134 | err_pt_alloc: |
| 135 | kfree(ppgtt->pt_dma_addr); |
| 136 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 137 | if (ppgtt->pt_pages[i]) |
| 138 | __free_page(ppgtt->pt_pages[i]); |
| 139 | } |
| 140 | kfree(ppgtt->pt_pages); |
| 141 | err_ppgtt: |
| 142 | kfree(ppgtt); |
| 143 | |
| 144 | return ret; |
| 145 | } |
| 146 | |
| 147 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) |
| 148 | { |
| 149 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 150 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 151 | int i; |
| 152 | |
| 153 | if (!ppgtt) |
| 154 | return; |
| 155 | |
| 156 | if (ppgtt->pt_dma_addr) { |
| 157 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
| 158 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], |
| 159 | 4096, PCI_DMA_BIDIRECTIONAL); |
| 160 | } |
| 161 | |
| 162 | kfree(ppgtt->pt_dma_addr); |
| 163 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
| 164 | __free_page(ppgtt->pt_pages[i]); |
| 165 | kfree(ppgtt->pt_pages); |
| 166 | kfree(ppgtt); |
| 167 | } |
| 168 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 169 | static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt, |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 170 | const struct sg_table *pages, |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 171 | unsigned first_entry, |
| 172 | uint32_t pte_flags) |
| 173 | { |
| 174 | uint32_t *pt_vaddr, pte; |
| 175 | unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; |
| 176 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
| 177 | unsigned i, j, m, segment_len; |
| 178 | dma_addr_t page_addr; |
| 179 | struct scatterlist *sg; |
| 180 | |
| 181 | /* init sg walking */ |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 182 | sg = pages->sgl; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 183 | i = 0; |
| 184 | segment_len = sg_dma_len(sg) >> PAGE_SHIFT; |
| 185 | m = 0; |
| 186 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 187 | while (i < pages->nents) { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 188 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]); |
| 189 | |
| 190 | for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) { |
| 191 | page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT); |
| 192 | pte = GEN6_PTE_ADDR_ENCODE(page_addr); |
| 193 | pt_vaddr[j] = pte | pte_flags; |
| 194 | |
| 195 | /* grab the next page */ |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 196 | if (++m == segment_len) { |
| 197 | if (++i == pages->nents) |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 198 | break; |
| 199 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 200 | sg = sg_next(sg); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 201 | segment_len = sg_dma_len(sg) >> PAGE_SHIFT; |
| 202 | m = 0; |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | kunmap_atomic(pt_vaddr); |
| 207 | |
| 208 | first_pte = 0; |
| 209 | act_pd++; |
| 210 | } |
| 211 | } |
| 212 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 213 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
| 214 | struct drm_i915_gem_object *obj, |
| 215 | enum i915_cache_level cache_level) |
| 216 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 217 | uint32_t pte_flags = GEN6_PTE_VALID; |
| 218 | |
| 219 | switch (cache_level) { |
| 220 | case I915_CACHE_LLC_MLC: |
Ben Widawsky | 8693607 | 2012-09-21 16:54:14 -0700 | [diff] [blame] | 221 | /* Haswell doesn't set L3 this way */ |
Ben Widawsky | 8f2c59f | 2012-09-24 08:55:51 -0700 | [diff] [blame^] | 222 | if (IS_HASWELL(ppgtt->dev)) |
Ben Widawsky | 8693607 | 2012-09-21 16:54:14 -0700 | [diff] [blame] | 223 | pte_flags |= GEN6_PTE_CACHE_LLC; |
| 224 | else |
| 225 | pte_flags |= GEN6_PTE_CACHE_LLC_MLC; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 226 | break; |
| 227 | case I915_CACHE_LLC: |
| 228 | pte_flags |= GEN6_PTE_CACHE_LLC; |
| 229 | break; |
| 230 | case I915_CACHE_NONE: |
Ben Widawsky | 8f2c59f | 2012-09-24 08:55:51 -0700 | [diff] [blame^] | 231 | if (IS_HASWELL(ppgtt->dev)) |
Daniel Vetter | a843af1 | 2012-08-14 11:42:14 -0300 | [diff] [blame] | 232 | pte_flags |= HSW_PTE_UNCACHED; |
| 233 | else |
| 234 | pte_flags |= GEN6_PTE_UNCACHED; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 235 | break; |
| 236 | default: |
| 237 | BUG(); |
| 238 | } |
| 239 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 240 | i915_ppgtt_insert_sg_entries(ppgtt, |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 241 | obj->pages, |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 242 | obj->gtt_space->start >> PAGE_SHIFT, |
| 243 | pte_flags); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 244 | } |
| 245 | |
| 246 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, |
| 247 | struct drm_i915_gem_object *obj) |
| 248 | { |
| 249 | i915_ppgtt_clear_range(ppgtt, |
| 250 | obj->gtt_space->start >> PAGE_SHIFT, |
| 251 | obj->base.size >> PAGE_SHIFT); |
| 252 | } |
| 253 | |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 254 | /* XXX kill agp_type! */ |
| 255 | static unsigned int cache_level_to_agp_type(struct drm_device *dev, |
| 256 | enum i915_cache_level cache_level) |
| 257 | { |
| 258 | switch (cache_level) { |
| 259 | case I915_CACHE_LLC_MLC: |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 260 | /* Older chipsets do not have this extra level of CPU |
| 261 | * cacheing, so fallthrough and request the PTE simply |
| 262 | * as cached. |
| 263 | */ |
Ben Widawsky | 8693607 | 2012-09-21 16:54:14 -0700 | [diff] [blame] | 264 | if (INTEL_INFO(dev)->gen >= 6 && !IS_HASWELL(dev)) |
| 265 | return AGP_USER_CACHED_MEMORY_LLC_MLC; |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 266 | case I915_CACHE_LLC: |
| 267 | return AGP_USER_CACHED_MEMORY; |
| 268 | default: |
| 269 | case I915_CACHE_NONE: |
| 270 | return AGP_USER_MEMORY; |
| 271 | } |
| 272 | } |
| 273 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 274 | static bool do_idling(struct drm_i915_private *dev_priv) |
| 275 | { |
| 276 | bool ret = dev_priv->mm.interruptible; |
| 277 | |
| 278 | if (unlikely(dev_priv->mm.gtt->do_idle_maps)) { |
| 279 | dev_priv->mm.interruptible = false; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 280 | if (i915_gpu_idle(dev_priv->dev)) { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 281 | DRM_ERROR("Couldn't idle GPU\n"); |
| 282 | /* Wait a bit, in hopes it avoids the hang */ |
| 283 | udelay(10); |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | return ret; |
| 288 | } |
| 289 | |
| 290 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) |
| 291 | { |
| 292 | if (unlikely(dev_priv->mm.gtt->do_idle_maps)) |
| 293 | dev_priv->mm.interruptible = interruptible; |
| 294 | } |
| 295 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 296 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
| 297 | { |
| 298 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 299 | struct drm_i915_gem_object *obj; |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 300 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 301 | /* First fill our portion of the GTT with scratch pages */ |
| 302 | intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE, |
| 303 | (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE); |
| 304 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 305 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
Chris Wilson | a8e9312 | 2010-12-08 14:28:54 +0000 | [diff] [blame] | 306 | i915_gem_clflush_object(obj); |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 307 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 308 | } |
| 309 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 310 | intel_gtt_chipset_flush(); |
| 311 | } |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 312 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 313 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 314 | { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 315 | if (obj->has_dma_mapping) |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 316 | return 0; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 317 | |
| 318 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
| 319 | obj->pages->sgl, obj->pages->nents, |
| 320 | PCI_DMA_BIDIRECTIONAL)) |
| 321 | return -ENOSPC; |
| 322 | |
| 323 | return 0; |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 324 | } |
| 325 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 326 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
| 327 | enum i915_cache_level cache_level) |
Chris Wilson | d5bd144 | 2011-04-14 06:48:26 +0100 | [diff] [blame] | 328 | { |
| 329 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | d5bd144 | 2011-04-14 06:48:26 +0100 | [diff] [blame] | 330 | unsigned int agp_type = cache_level_to_agp_type(dev, cache_level); |
| 331 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 332 | intel_gtt_insert_sg_entries(obj->pages, |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 333 | obj->gtt_space->start >> PAGE_SHIFT, |
| 334 | agp_type); |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 335 | obj->has_global_gtt_mapping = 1; |
Chris Wilson | d5bd144 | 2011-04-14 06:48:26 +0100 | [diff] [blame] | 336 | } |
| 337 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 338 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 339 | { |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 340 | intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT, |
| 341 | obj->base.size >> PAGE_SHIFT); |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 342 | |
| 343 | obj->has_global_gtt_mapping = 0; |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) |
| 347 | { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 348 | struct drm_device *dev = obj->base.dev; |
| 349 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 350 | bool interruptible; |
| 351 | |
| 352 | interruptible = do_idling(dev_priv); |
| 353 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 354 | if (!obj->has_dma_mapping) |
| 355 | dma_unmap_sg(&dev->pdev->dev, |
| 356 | obj->pages->sgl, obj->pages->nents, |
| 357 | PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 358 | |
| 359 | undo_idling(dev_priv, interruptible); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 360 | } |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 361 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 362 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
| 363 | unsigned long color, |
| 364 | unsigned long *start, |
| 365 | unsigned long *end) |
| 366 | { |
| 367 | if (node->color != color) |
| 368 | *start += 4096; |
| 369 | |
| 370 | if (!list_empty(&node->node_list)) { |
| 371 | node = list_entry(node->node_list.next, |
| 372 | struct drm_mm_node, |
| 373 | node_list); |
| 374 | if (node->allocated && node->color != color) |
| 375 | *end -= 4096; |
| 376 | } |
| 377 | } |
| 378 | |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 379 | void i915_gem_init_global_gtt(struct drm_device *dev, |
| 380 | unsigned long start, |
| 381 | unsigned long mappable_end, |
| 382 | unsigned long end) |
| 383 | { |
| 384 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 385 | |
Daniel Vetter | d1dd20a | 2012-03-26 09:45:42 +0200 | [diff] [blame] | 386 | /* Substract the guard page ... */ |
| 387 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 388 | if (!HAS_LLC(dev)) |
| 389 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 390 | |
| 391 | dev_priv->mm.gtt_start = start; |
| 392 | dev_priv->mm.gtt_mappable_end = mappable_end; |
| 393 | dev_priv->mm.gtt_end = end; |
| 394 | dev_priv->mm.gtt_total = end - start; |
| 395 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
| 396 | |
Daniel Vetter | d1dd20a | 2012-03-26 09:45:42 +0200 | [diff] [blame] | 397 | /* ... but ensure that we clear the entire range. */ |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 398 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); |
| 399 | } |