Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Imagination Technologies |
| 3 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | */ |
| 10 | |
| 11 | #include <asm/addrspace.h> |
| 12 | #include <asm/asm.h> |
| 13 | #include <asm/asm-offsets.h> |
| 14 | #include <asm/asmmacro.h> |
| 15 | #include <asm/cacheops.h> |
Markos Chandras | 6521d9a | 2014-07-21 14:35:56 +0100 | [diff] [blame] | 16 | #include <asm/eva.h> |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 17 | #include <asm/mipsregs.h> |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 18 | #include <asm/mipsmtregs.h> |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 19 | #include <asm/pm.h> |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 20 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 21 | #define GCR_CL_COHERENCE_OFS 0x2008 |
| 22 | #define GCR_CL_ID_OFS 0x2028 |
| 23 | |
| 24 | .extern mips_cm_base |
| 25 | |
| 26 | .set noreorder |
| 27 | |
Paul Burton | 8fe2c547 | 2015-09-22 11:12:10 -0700 | [diff] [blame^] | 28 | #ifdef CONFIG_64BIT |
| 29 | # define STATUS_BITDEPS ST0_KX |
| 30 | #else |
| 31 | # define STATUS_BITDEPS 0 |
| 32 | #endif |
| 33 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 34 | /* |
| 35 | * Set dest to non-zero if the core supports the MT ASE, else zero. If |
| 36 | * MT is not supported then branch to nomt. |
| 37 | */ |
| 38 | .macro has_mt dest, nomt |
| 39 | mfc0 \dest, CP0_CONFIG |
| 40 | bgez \dest, \nomt |
| 41 | mfc0 \dest, CP0_CONFIG, 1 |
| 42 | bgez \dest, \nomt |
| 43 | mfc0 \dest, CP0_CONFIG, 2 |
| 44 | bgez \dest, \nomt |
| 45 | mfc0 \dest, CP0_CONFIG, 3 |
| 46 | andi \dest, \dest, MIPS_CONF3_MT |
| 47 | beqz \dest, \nomt |
Paul Burton | 1e5fb28 | 2015-08-05 15:42:36 -0700 | [diff] [blame] | 48 | nop |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 49 | .endm |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 50 | |
| 51 | .section .text.cps-vec |
| 52 | .balign 0x1000 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 53 | |
| 54 | LEAF(mips_cps_core_entry) |
| 55 | /* |
Paul Burton | 0155a06 | 2014-04-16 11:10:57 +0100 | [diff] [blame] | 56 | * These first 12 bytes will be patched by cps_smp_setup to load the |
| 57 | * base address of the CM GCRs into register v1 and the CCA to use into |
| 58 | * register s0. |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 59 | */ |
| 60 | .quad 0 |
Paul Burton | 0155a06 | 2014-04-16 11:10:57 +0100 | [diff] [blame] | 61 | .word 0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 62 | |
| 63 | /* Check whether we're here due to an NMI */ |
| 64 | mfc0 k0, CP0_STATUS |
| 65 | and k0, k0, ST0_NMI |
| 66 | beqz k0, not_nmi |
| 67 | nop |
| 68 | |
| 69 | /* This is an NMI */ |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 70 | PTR_LA k0, nmi_handler |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 71 | jr k0 |
| 72 | nop |
| 73 | |
| 74 | not_nmi: |
| 75 | /* Setup Cause */ |
| 76 | li t0, CAUSEF_IV |
| 77 | mtc0 t0, CP0_CAUSE |
| 78 | |
| 79 | /* Setup Status */ |
Paul Burton | 8fe2c547 | 2015-09-22 11:12:10 -0700 | [diff] [blame^] | 80 | li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 81 | mtc0 t0, CP0_STATUS |
| 82 | |
| 83 | /* |
| 84 | * Clear the bits used to index the caches. Note that the architecture |
| 85 | * dictates that writing to any of TagLo or TagHi selects 0 or 2 should |
| 86 | * be valid for all MIPS32 CPUs, even those for which said writes are |
| 87 | * unnecessary. |
| 88 | */ |
| 89 | mtc0 zero, CP0_TAGLO, 0 |
| 90 | mtc0 zero, CP0_TAGHI, 0 |
| 91 | mtc0 zero, CP0_TAGLO, 2 |
| 92 | mtc0 zero, CP0_TAGHI, 2 |
| 93 | ehb |
| 94 | |
| 95 | /* Primary cache configuration is indicated by Config1 */ |
| 96 | mfc0 v0, CP0_CONFIG, 1 |
| 97 | |
| 98 | /* Detect I-cache line size */ |
| 99 | _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ |
| 100 | beqz t0, icache_done |
| 101 | li t1, 2 |
| 102 | sllv t0, t1, t0 |
| 103 | |
| 104 | /* Detect I-cache size */ |
| 105 | _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ |
| 106 | xori t2, t1, 0x7 |
| 107 | beqz t2, 1f |
| 108 | li t3, 32 |
Markos Chandras | acac410 | 2014-11-24 14:40:11 +0000 | [diff] [blame] | 109 | addiu t1, t1, 1 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 110 | sllv t1, t3, t1 |
| 111 | 1: /* At this point t1 == I-cache sets per way */ |
| 112 | _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ |
Markos Chandras | acac410 | 2014-11-24 14:40:11 +0000 | [diff] [blame] | 113 | addiu t2, t2, 1 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 114 | mul t1, t1, t0 |
| 115 | mul t1, t1, t2 |
| 116 | |
Markos Chandras | 717f142 | 2015-07-01 09:13:32 +0100 | [diff] [blame] | 117 | li a0, CKSEG0 |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 118 | PTR_ADD a1, a0, t1 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 119 | 1: cache Index_Store_Tag_I, 0(a0) |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 120 | PTR_ADD a0, a0, t0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 121 | bne a0, a1, 1b |
| 122 | nop |
| 123 | icache_done: |
| 124 | |
| 125 | /* Detect D-cache line size */ |
| 126 | _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ |
| 127 | beqz t0, dcache_done |
| 128 | li t1, 2 |
| 129 | sllv t0, t1, t0 |
| 130 | |
| 131 | /* Detect D-cache size */ |
| 132 | _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ |
| 133 | xori t2, t1, 0x7 |
| 134 | beqz t2, 1f |
| 135 | li t3, 32 |
Markos Chandras | acac410 | 2014-11-24 14:40:11 +0000 | [diff] [blame] | 136 | addiu t1, t1, 1 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 137 | sllv t1, t3, t1 |
| 138 | 1: /* At this point t1 == D-cache sets per way */ |
| 139 | _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ |
Markos Chandras | acac410 | 2014-11-24 14:40:11 +0000 | [diff] [blame] | 140 | addiu t2, t2, 1 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 141 | mul t1, t1, t0 |
| 142 | mul t1, t1, t2 |
| 143 | |
Markos Chandras | 717f142 | 2015-07-01 09:13:32 +0100 | [diff] [blame] | 144 | li a0, CKSEG0 |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 145 | PTR_ADDU a1, a0, t1 |
| 146 | PTR_SUBU a1, a1, t0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 147 | 1: cache Index_Store_Tag_D, 0(a0) |
| 148 | bne a0, a1, 1b |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 149 | PTR_ADD a0, a0, t0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 150 | dcache_done: |
| 151 | |
Paul Burton | 0155a06 | 2014-04-16 11:10:57 +0100 | [diff] [blame] | 152 | /* Set Kseg0 CCA to that in s0 */ |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 153 | mfc0 t0, CP0_CONFIG |
| 154 | ori t0, 0x7 |
Paul Burton | 0155a06 | 2014-04-16 11:10:57 +0100 | [diff] [blame] | 155 | xori t0, 0x7 |
| 156 | or t0, t0, s0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 157 | mtc0 t0, CP0_CONFIG |
| 158 | ehb |
| 159 | |
| 160 | /* Enter the coherent domain */ |
| 161 | li t0, 0xff |
Paul Burton | 9099651 | 2015-08-05 15:42:35 -0700 | [diff] [blame] | 162 | sw t0, GCR_CL_COHERENCE_OFS(v1) |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 163 | ehb |
| 164 | |
| 165 | /* Jump to kseg0 */ |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 166 | PTR_LA t0, 1f |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 167 | jr t0 |
| 168 | nop |
| 169 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 170 | /* |
| 171 | * We're up, cached & coherent. Perform any further required core-level |
| 172 | * initialisation. |
| 173 | */ |
| 174 | 1: jal mips_cps_core_init |
| 175 | nop |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 176 | |
Markos Chandras | 6521d9a | 2014-07-21 14:35:56 +0100 | [diff] [blame] | 177 | /* Do any EVA initialization if necessary */ |
| 178 | eva_init |
| 179 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 180 | /* |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 181 | * Boot any other VPEs within this core that should be online, and |
| 182 | * deactivate this VPE if it should be offline. |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 183 | */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 184 | jal mips_cps_boot_vpes |
| 185 | nop |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 186 | |
| 187 | /* Off we go! */ |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 188 | PTR_L t1, VPEBOOTCFG_PC(v0) |
| 189 | PTR_L gp, VPEBOOTCFG_GP(v0) |
| 190 | PTR_L sp, VPEBOOTCFG_SP(v0) |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 191 | jr t1 |
| 192 | nop |
| 193 | END(mips_cps_core_entry) |
| 194 | |
| 195 | .org 0x200 |
| 196 | LEAF(excep_tlbfill) |
| 197 | b . |
| 198 | nop |
| 199 | END(excep_tlbfill) |
| 200 | |
| 201 | .org 0x280 |
| 202 | LEAF(excep_xtlbfill) |
| 203 | b . |
| 204 | nop |
| 205 | END(excep_xtlbfill) |
| 206 | |
| 207 | .org 0x300 |
| 208 | LEAF(excep_cache) |
| 209 | b . |
| 210 | nop |
| 211 | END(excep_cache) |
| 212 | |
| 213 | .org 0x380 |
| 214 | LEAF(excep_genex) |
| 215 | b . |
| 216 | nop |
| 217 | END(excep_genex) |
| 218 | |
| 219 | .org 0x400 |
| 220 | LEAF(excep_intex) |
| 221 | b . |
| 222 | nop |
| 223 | END(excep_intex) |
| 224 | |
| 225 | .org 0x480 |
| 226 | LEAF(excep_ejtag) |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 227 | PTR_LA k0, ejtag_debug_handler |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 228 | jr k0 |
| 229 | nop |
| 230 | END(excep_ejtag) |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 231 | |
| 232 | LEAF(mips_cps_core_init) |
Paul Burton | 7a63076 | 2015-08-05 15:42:38 -0700 | [diff] [blame] | 233 | #ifdef CONFIG_MIPS_MT_SMP |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 234 | /* Check that the core implements the MT ASE */ |
| 235 | has_mt t0, 3f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 236 | |
| 237 | .set push |
Markos Chandras | 977e043 | 2015-07-01 09:13:30 +0100 | [diff] [blame] | 238 | .set mips64r2 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 239 | .set mt |
| 240 | |
| 241 | /* Only allow 1 TC per VPE to execute... */ |
| 242 | dmt |
| 243 | |
| 244 | /* ...and for the moment only 1 VPE */ |
| 245 | dvpe |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 246 | PTR_LA t1, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 247 | jr.hb t1 |
| 248 | nop |
| 249 | |
| 250 | /* Enter VPE configuration state */ |
| 251 | 1: mfc0 t0, CP0_MVPCONTROL |
| 252 | ori t0, t0, MVPCONTROL_VPC |
| 253 | mtc0 t0, CP0_MVPCONTROL |
| 254 | |
| 255 | /* Retrieve the number of VPEs within the core */ |
| 256 | mfc0 t0, CP0_MVPCONF0 |
| 257 | srl t0, t0, MVPCONF0_PVPE_SHIFT |
| 258 | andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT) |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 259 | addiu ta3, t0, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 260 | |
| 261 | /* If there's only 1, we're done */ |
| 262 | beqz t0, 2f |
| 263 | nop |
| 264 | |
| 265 | /* Loop through each VPE within this core */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 266 | li ta1, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 267 | |
| 268 | 1: /* Operate on the appropriate TC */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 269 | mtc0 ta1, CP0_VPECONTROL |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 270 | ehb |
| 271 | |
| 272 | /* Bind TC to VPE (1:1 TC:VPE mapping) */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 273 | mttc0 ta1, CP0_TCBIND |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 274 | |
| 275 | /* Set exclusive TC, non-active, master */ |
| 276 | li t0, VPECONF0_MVP |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 277 | sll t1, ta1, VPECONF0_XTC_SHIFT |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 278 | or t0, t0, t1 |
| 279 | mttc0 t0, CP0_VPECONF0 |
| 280 | |
| 281 | /* Set TC non-active, non-allocatable */ |
| 282 | mttc0 zero, CP0_TCSTATUS |
| 283 | |
| 284 | /* Set TC halted */ |
| 285 | li t0, TCHALT_H |
| 286 | mttc0 t0, CP0_TCHALT |
| 287 | |
| 288 | /* Next VPE */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 289 | addiu ta1, ta1, 1 |
| 290 | slt t0, ta1, ta3 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 291 | bnez t0, 1b |
| 292 | nop |
| 293 | |
| 294 | /* Leave VPE configuration state */ |
| 295 | 2: mfc0 t0, CP0_MVPCONTROL |
| 296 | xori t0, t0, MVPCONTROL_VPC |
| 297 | mtc0 t0, CP0_MVPCONTROL |
| 298 | |
| 299 | 3: .set pop |
| 300 | #endif |
| 301 | jr ra |
| 302 | nop |
| 303 | END(mips_cps_core_init) |
| 304 | |
| 305 | LEAF(mips_cps_boot_vpes) |
| 306 | /* Retrieve CM base address */ |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 307 | PTR_LA t0, mips_cm_base |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 308 | PTR_L t0, 0(t0) |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 309 | |
| 310 | /* Calculate a pointer to this cores struct core_boot_config */ |
Paul Burton | 9099651 | 2015-08-05 15:42:35 -0700 | [diff] [blame] | 311 | lw t0, GCR_CL_ID_OFS(t0) |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 312 | li t1, COREBOOTCFG_SIZE |
| 313 | mul t0, t0, t1 |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 314 | PTR_LA t1, mips_cps_core_bootcfg |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 315 | PTR_L t1, 0(t1) |
| 316 | PTR_ADDU t0, t0, t1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 317 | |
| 318 | /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ |
Paul Burton | 1e5fb28 | 2015-08-05 15:42:36 -0700 | [diff] [blame] | 319 | li t9, 0 |
Paul Burton | 7a63076 | 2015-08-05 15:42:38 -0700 | [diff] [blame] | 320 | #ifdef CONFIG_MIPS_MT_SMP |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 321 | has_mt ta2, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 322 | |
| 323 | /* Find the number of VPEs present in the core */ |
| 324 | mfc0 t1, CP0_MVPCONF0 |
| 325 | srl t1, t1, MVPCONF0_PVPE_SHIFT |
| 326 | andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT |
Markos Chandras | acac410 | 2014-11-24 14:40:11 +0000 | [diff] [blame] | 327 | addiu t1, t1, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 328 | |
| 329 | /* Calculate a mask for the VPE ID from EBase.CPUNum */ |
| 330 | clz t1, t1 |
| 331 | li t2, 31 |
| 332 | subu t1, t2, t1 |
| 333 | li t2, 1 |
| 334 | sll t1, t2, t1 |
| 335 | addiu t1, t1, -1 |
| 336 | |
| 337 | /* Retrieve the VPE ID from EBase.CPUNum */ |
| 338 | mfc0 t9, $15, 1 |
| 339 | and t9, t9, t1 |
Paul Burton | a5b0f6d | 2015-08-05 15:42:37 -0700 | [diff] [blame] | 340 | #endif |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 341 | |
| 342 | 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */ |
| 343 | li t1, VPEBOOTCFG_SIZE |
| 344 | mul v0, t9, t1 |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 345 | PTR_L ta3, COREBOOTCFG_VPECONFIG(t0) |
| 346 | PTR_ADDU v0, v0, ta3 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 347 | |
Paul Burton | 7a63076 | 2015-08-05 15:42:38 -0700 | [diff] [blame] | 348 | #ifdef CONFIG_MIPS_MT_SMP |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 349 | |
| 350 | /* If the core doesn't support MT then return */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 351 | bnez ta2, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 352 | nop |
| 353 | jr ra |
| 354 | nop |
| 355 | |
| 356 | .set push |
Markos Chandras | 977e043 | 2015-07-01 09:13:30 +0100 | [diff] [blame] | 357 | .set mips64r2 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 358 | .set mt |
| 359 | |
| 360 | 1: /* Enter VPE configuration state */ |
| 361 | dvpe |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 362 | PTR_LA t1, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 363 | jr.hb t1 |
| 364 | nop |
| 365 | 1: mfc0 t1, CP0_MVPCONTROL |
| 366 | ori t1, t1, MVPCONTROL_VPC |
| 367 | mtc0 t1, CP0_MVPCONTROL |
| 368 | ehb |
| 369 | |
| 370 | /* Loop through each VPE */ |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 371 | PTR_L ta2, COREBOOTCFG_VPEMASK(t0) |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 372 | move t8, ta2 |
| 373 | li ta1, 0 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 374 | |
| 375 | /* Check whether the VPE should be running. If not, skip it */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 376 | 1: andi t0, ta2, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 377 | beqz t0, 2f |
| 378 | nop |
| 379 | |
| 380 | /* Operate on the appropriate TC */ |
| 381 | mfc0 t0, CP0_VPECONTROL |
| 382 | ori t0, t0, VPECONTROL_TARGTC |
| 383 | xori t0, t0, VPECONTROL_TARGTC |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 384 | or t0, t0, ta1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 385 | mtc0 t0, CP0_VPECONTROL |
| 386 | ehb |
| 387 | |
| 388 | /* Skip the VPE if its TC is not halted */ |
| 389 | mftc0 t0, CP0_TCHALT |
| 390 | beqz t0, 2f |
| 391 | nop |
| 392 | |
| 393 | /* Calculate a pointer to the VPEs struct vpe_boot_config */ |
| 394 | li t0, VPEBOOTCFG_SIZE |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 395 | mul t0, t0, ta1 |
| 396 | addu t0, t0, ta3 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 397 | |
| 398 | /* Set the TC restart PC */ |
| 399 | lw t1, VPEBOOTCFG_PC(t0) |
| 400 | mttc0 t1, CP0_TCRESTART |
| 401 | |
| 402 | /* Set the TC stack pointer */ |
| 403 | lw t1, VPEBOOTCFG_SP(t0) |
| 404 | mttgpr t1, sp |
| 405 | |
| 406 | /* Set the TC global pointer */ |
| 407 | lw t1, VPEBOOTCFG_GP(t0) |
| 408 | mttgpr t1, gp |
| 409 | |
| 410 | /* Copy config from this VPE */ |
| 411 | mfc0 t0, CP0_CONFIG |
| 412 | mttc0 t0, CP0_CONFIG |
| 413 | |
| 414 | /* Ensure no software interrupts are pending */ |
| 415 | mttc0 zero, CP0_CAUSE |
| 416 | mttc0 zero, CP0_STATUS |
| 417 | |
| 418 | /* Set TC active, not interrupt exempt */ |
| 419 | mftc0 t0, CP0_TCSTATUS |
| 420 | li t1, ~TCSTATUS_IXMT |
| 421 | and t0, t0, t1 |
| 422 | ori t0, t0, TCSTATUS_A |
| 423 | mttc0 t0, CP0_TCSTATUS |
| 424 | |
| 425 | /* Clear the TC halt bit */ |
| 426 | mttc0 zero, CP0_TCHALT |
| 427 | |
| 428 | /* Set VPE active */ |
| 429 | mftc0 t0, CP0_VPECONF0 |
| 430 | ori t0, t0, VPECONF0_VPA |
| 431 | mttc0 t0, CP0_VPECONF0 |
| 432 | |
| 433 | /* Next VPE */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 434 | 2: srl ta2, ta2, 1 |
| 435 | addiu ta1, ta1, 1 |
| 436 | bnez ta2, 1b |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 437 | nop |
| 438 | |
| 439 | /* Leave VPE configuration state */ |
| 440 | mfc0 t1, CP0_MVPCONTROL |
| 441 | xori t1, t1, MVPCONTROL_VPC |
| 442 | mtc0 t1, CP0_MVPCONTROL |
| 443 | ehb |
| 444 | evpe |
| 445 | |
| 446 | /* Check whether this VPE is meant to be running */ |
| 447 | li t0, 1 |
| 448 | sll t0, t0, t9 |
| 449 | and t0, t0, t8 |
| 450 | bnez t0, 2f |
| 451 | nop |
| 452 | |
| 453 | /* This VPE should be offline, halt the TC */ |
| 454 | li t0, TCHALT_H |
| 455 | mtc0 t0, CP0_TCHALT |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 456 | PTR_LA t0, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 457 | 1: jr.hb t0 |
| 458 | nop |
| 459 | |
| 460 | 2: .set pop |
| 461 | |
Paul Burton | 7a63076 | 2015-08-05 15:42:38 -0700 | [diff] [blame] | 462 | #endif /* CONFIG_MIPS_MT_SMP */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 463 | |
| 464 | /* Return */ |
| 465 | jr ra |
| 466 | nop |
| 467 | END(mips_cps_boot_vpes) |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 468 | |
| 469 | #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM) |
| 470 | |
| 471 | /* Calculate a pointer to this CPUs struct mips_static_suspend_state */ |
| 472 | .macro psstate dest |
| 473 | .set push |
| 474 | .set noat |
| 475 | lw $1, TI_CPU(gp) |
| 476 | sll $1, $1, LONGLOG |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 477 | PTR_LA \dest, __per_cpu_offset |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 478 | addu $1, $1, \dest |
| 479 | lw $1, 0($1) |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 480 | PTR_LA \dest, cps_cpu_state |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 481 | addu \dest, \dest, $1 |
| 482 | .set pop |
| 483 | .endm |
| 484 | |
| 485 | LEAF(mips_cps_pm_save) |
| 486 | /* Save CPU state */ |
| 487 | SUSPEND_SAVE_REGS |
| 488 | psstate t1 |
| 489 | SUSPEND_SAVE_STATIC |
| 490 | jr v0 |
| 491 | nop |
| 492 | END(mips_cps_pm_save) |
| 493 | |
| 494 | LEAF(mips_cps_pm_restore) |
| 495 | /* Restore CPU state */ |
| 496 | psstate t1 |
| 497 | RESUME_RESTORE_STATIC |
| 498 | RESUME_RESTORE_REGS_RETURN |
| 499 | END(mips_cps_pm_restore) |
| 500 | |
| 501 | #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */ |