Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "intel_drv.h" |
| 26 | |
| 27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
| 28 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
| 30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
| 31 | |
| 32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
| 34 | |
| 35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
| 37 | |
| 38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
| 39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
| 40 | |
| 41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| 42 | |
| 43 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 44 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 45 | { |
| 46 | u32 gt_thread_status_mask; |
| 47 | |
| 48 | if (IS_HASWELL(dev_priv->dev)) |
| 49 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
| 50 | else |
| 51 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
| 52 | |
| 53 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 54 | * thread to wake up. |
| 55 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 56 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 57 | DRM_ERROR("GT thread status wait timed out\n"); |
| 58 | } |
| 59 | |
| 60 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
| 61 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 62 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 63 | /* something from same cacheline, but !FORCEWAKE */ |
| 64 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 68 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 69 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 70 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 71 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 72 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 73 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
| 74 | /* something from same cacheline, but !FORCEWAKE */ |
| 75 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 76 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 77 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 78 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 79 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 80 | |
| 81 | /* WaRsForcewakeWaitTC0:snb */ |
| 82 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 83 | } |
| 84 | |
| 85 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
| 86 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 87 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 88 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 89 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
| 93 | { |
| 94 | u32 forcewake_ack; |
| 95 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 96 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 97 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 98 | else |
| 99 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 100 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 101 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 102 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 103 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 104 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 105 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 106 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 107 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 108 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 109 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 110 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 111 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 112 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 113 | |
| 114 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
| 115 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 116 | } |
| 117 | |
| 118 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 119 | { |
| 120 | u32 gtfifodbg; |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 121 | |
| 122 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 123 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
| 124 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 125 | __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 129 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 130 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 131 | /* something from same cacheline, but !FORCEWAKE */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 132 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 133 | gen6_gt_check_fifodbg(dev_priv); |
| 134 | } |
| 135 | |
| 136 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
| 137 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 138 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 139 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 140 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 141 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 142 | gen6_gt_check_fifodbg(dev_priv); |
| 143 | } |
| 144 | |
| 145 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 146 | { |
| 147 | int ret = 0; |
| 148 | |
| 149 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 150 | int loop = 500; |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 151 | u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 152 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 153 | udelay(10); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 154 | fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 155 | } |
| 156 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 157 | ++ret; |
| 158 | dev_priv->uncore.fifo_count = fifo; |
| 159 | } |
| 160 | dev_priv->uncore.fifo_count--; |
| 161 | |
| 162 | return ret; |
| 163 | } |
| 164 | |
| 165 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
| 166 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 167 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 168 | _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 169 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 170 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
| 174 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 175 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 176 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 177 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 178 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 179 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 180 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 181 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 182 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 183 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 184 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 185 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 186 | DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); |
| 187 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 188 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) & |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 189 | FORCEWAKE_KERNEL), |
| 190 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 191 | DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); |
| 192 | |
| 193 | /* WaRsForcewakeWaitTC0:vlv */ |
| 194 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 195 | } |
| 196 | |
| 197 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
| 198 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 199 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 200 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 201 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 202 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 203 | /* The below doubles as a POSTING_READ */ |
| 204 | gen6_gt_check_fifodbg(dev_priv); |
| 205 | } |
| 206 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 207 | static void gen6_force_wake_work(struct work_struct *work) |
| 208 | { |
| 209 | struct drm_i915_private *dev_priv = |
| 210 | container_of(work, typeof(*dev_priv), uncore.force_wake_work.work); |
| 211 | unsigned long irqflags; |
| 212 | |
| 213 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 214 | if (--dev_priv->uncore.forcewake_count == 0) |
| 215 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
| 216 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 217 | } |
| 218 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 219 | void intel_uncore_early_sanitize(struct drm_device *dev) |
| 220 | { |
| 221 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 222 | |
| 223 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 224 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 225 | |
| 226 | if (IS_HASWELL(dev) && |
| 227 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { |
| 228 | /* The docs do not explain exactly how the calculation can be |
| 229 | * made. It is somewhat guessable, but for now, it's always |
| 230 | * 128MB. |
| 231 | * NB: We can't write IDICR yet because we do not have gt funcs |
| 232 | * set up */ |
| 233 | dev_priv->ellc_size = 128; |
| 234 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); |
| 235 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 236 | } |
| 237 | |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 238 | static void intel_uncore_forcewake_reset(struct drm_device *dev) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 239 | { |
| 240 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 241 | |
| 242 | if (IS_VALLEYVIEW(dev)) { |
| 243 | vlv_force_wake_reset(dev_priv); |
| 244 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 245 | __gen6_gt_force_wake_reset(dev_priv); |
| 246 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 247 | __gen6_gt_force_wake_mt_reset(dev_priv); |
| 248 | } |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | void intel_uncore_sanitize(struct drm_device *dev) |
| 252 | { |
Chon Ming Lee | 02f4c9e | 2013-10-03 23:16:17 +0800 | [diff] [blame] | 253 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 254 | u32 reg_val; |
| 255 | |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 256 | intel_uncore_forcewake_reset(dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 257 | |
| 258 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| 259 | intel_disable_gt_powersave(dev); |
Chon Ming Lee | 02f4c9e | 2013-10-03 23:16:17 +0800 | [diff] [blame] | 260 | |
| 261 | /* Turn off power gate, require especially for the BIOS less system */ |
| 262 | if (IS_VALLEYVIEW(dev)) { |
| 263 | |
| 264 | mutex_lock(&dev_priv->rps.hw_lock); |
| 265 | reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); |
| 266 | |
| 267 | if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT)) |
| 268 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); |
| 269 | |
| 270 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 271 | |
| 272 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | /* |
| 276 | * Generally this is called implicitly by the register read function. However, |
| 277 | * if some sequence requires the GT to not power down then this function should |
| 278 | * be called at the beginning of the sequence followed by a call to |
| 279 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 280 | */ |
| 281 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 282 | { |
| 283 | unsigned long irqflags; |
| 284 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 285 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 286 | return; |
| 287 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 288 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 289 | if (dev_priv->uncore.forcewake_count++ == 0) |
| 290 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
| 291 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 292 | } |
| 293 | |
| 294 | /* |
| 295 | * see gen6_gt_force_wake_get() |
| 296 | */ |
| 297 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 298 | { |
| 299 | unsigned long irqflags; |
| 300 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 301 | if (!dev_priv->uncore.funcs.force_wake_put) |
| 302 | return; |
| 303 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 304 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 305 | if (--dev_priv->uncore.forcewake_count == 0) { |
| 306 | dev_priv->uncore.forcewake_count++; |
| 307 | mod_delayed_work(dev_priv->wq, |
| 308 | &dev_priv->uncore.force_wake_work, |
| 309 | 1); |
| 310 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 311 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 312 | } |
| 313 | |
| 314 | /* We give fast paths for the really cool registers */ |
| 315 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 316 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 317 | |
| 318 | static void |
| 319 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 320 | { |
| 321 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| 322 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
| 323 | * hence harmless to write 0 into. */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 324 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | static void |
| 328 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
| 329 | { |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 330 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 331 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
| 332 | reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 333 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 334 | } |
| 335 | } |
| 336 | |
| 337 | static void |
| 338 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
| 339 | { |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 340 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 341 | DRM_ERROR("Unclaimed write to %x\n", reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 342 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 343 | } |
| 344 | } |
| 345 | |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 346 | #define REG_READ_HEADER(x) \ |
| 347 | unsigned long irqflags; \ |
| 348 | u##x val = 0; \ |
| 349 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 350 | |
| 351 | #define REG_READ_FOOTER \ |
| 352 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 353 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 354 | return val |
| 355 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 356 | #define __gen4_read(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 357 | static u##x \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 358 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 359 | REG_READ_HEADER(x); \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 360 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 361 | REG_READ_FOOTER; \ |
| 362 | } |
| 363 | |
| 364 | #define __gen5_read(x) \ |
| 365 | static u##x \ |
| 366 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 367 | REG_READ_HEADER(x); \ |
| 368 | ilk_dummy_write(dev_priv); \ |
| 369 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 370 | REG_READ_FOOTER; \ |
| 371 | } |
| 372 | |
| 373 | #define __gen6_read(x) \ |
| 374 | static u##x \ |
| 375 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 376 | REG_READ_HEADER(x); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 377 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 378 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 379 | dev_priv->uncore.funcs.force_wake_get(dev_priv); \ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 380 | val = __raw_i915_read##x(dev_priv, reg); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 381 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 382 | dev_priv->uncore.funcs.force_wake_put(dev_priv); \ |
| 383 | } else { \ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 384 | val = __raw_i915_read##x(dev_priv, reg); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 385 | } \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 386 | REG_READ_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 387 | } |
| 388 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 389 | __gen6_read(8) |
| 390 | __gen6_read(16) |
| 391 | __gen6_read(32) |
| 392 | __gen6_read(64) |
| 393 | __gen5_read(8) |
| 394 | __gen5_read(16) |
| 395 | __gen5_read(32) |
| 396 | __gen5_read(64) |
| 397 | __gen4_read(8) |
| 398 | __gen4_read(16) |
| 399 | __gen4_read(32) |
| 400 | __gen4_read(64) |
| 401 | |
| 402 | #undef __gen6_read |
| 403 | #undef __gen5_read |
| 404 | #undef __gen4_read |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 405 | #undef REG_READ_FOOTER |
| 406 | #undef REG_READ_HEADER |
| 407 | |
| 408 | #define REG_WRITE_HEADER \ |
| 409 | unsigned long irqflags; \ |
| 410 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
| 411 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 412 | |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 413 | #define __gen4_write(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 414 | static void \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 415 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 416 | REG_WRITE_HEADER; \ |
| 417 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 418 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 419 | } |
| 420 | |
| 421 | #define __gen5_write(x) \ |
| 422 | static void \ |
| 423 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 424 | REG_WRITE_HEADER; \ |
| 425 | ilk_dummy_write(dev_priv); \ |
| 426 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 427 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 428 | } |
| 429 | |
| 430 | #define __gen6_write(x) \ |
| 431 | static void \ |
| 432 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 433 | u32 __fifo_ret = 0; \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 434 | REG_WRITE_HEADER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 435 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 436 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 437 | } \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 438 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 439 | if (unlikely(__fifo_ret)) { \ |
| 440 | gen6_gt_check_fifodbg(dev_priv); \ |
| 441 | } \ |
| 442 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 443 | } |
| 444 | |
| 445 | #define __hsw_write(x) \ |
| 446 | static void \ |
| 447 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 448 | u32 __fifo_ret = 0; \ |
| 449 | REG_WRITE_HEADER; \ |
| 450 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 451 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 452 | } \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 453 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 454 | __raw_i915_write##x(dev_priv, reg, val); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 455 | if (unlikely(__fifo_ret)) { \ |
| 456 | gen6_gt_check_fifodbg(dev_priv); \ |
| 457 | } \ |
| 458 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
| 459 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 460 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 461 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 462 | static const u32 gen8_shadowed_regs[] = { |
| 463 | FORCEWAKE_MT, |
| 464 | GEN6_RPNSWREQ, |
| 465 | GEN6_RC_VIDEO_FREQ, |
| 466 | RING_TAIL(RENDER_RING_BASE), |
| 467 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 468 | RING_TAIL(VEBOX_RING_BASE), |
| 469 | RING_TAIL(BLT_RING_BASE), |
| 470 | /* TODO: Other registers are not yet used */ |
| 471 | }; |
| 472 | |
| 473 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 474 | { |
| 475 | int i; |
| 476 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) |
| 477 | if (reg == gen8_shadowed_regs[i]) |
| 478 | return true; |
| 479 | |
| 480 | return false; |
| 481 | } |
| 482 | |
| 483 | #define __gen8_write(x) \ |
| 484 | static void \ |
| 485 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 486 | bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \ |
| 487 | REG_WRITE_HEADER; \ |
| 488 | if (__needs_put) { \ |
| 489 | dev_priv->uncore.funcs.force_wake_get(dev_priv); \ |
| 490 | } \ |
| 491 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 492 | if (__needs_put) { \ |
| 493 | dev_priv->uncore.funcs.force_wake_put(dev_priv); \ |
| 494 | } \ |
| 495 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 496 | } |
| 497 | |
| 498 | __gen8_write(8) |
| 499 | __gen8_write(16) |
| 500 | __gen8_write(32) |
| 501 | __gen8_write(64) |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 502 | __hsw_write(8) |
| 503 | __hsw_write(16) |
| 504 | __hsw_write(32) |
| 505 | __hsw_write(64) |
| 506 | __gen6_write(8) |
| 507 | __gen6_write(16) |
| 508 | __gen6_write(32) |
| 509 | __gen6_write(64) |
| 510 | __gen5_write(8) |
| 511 | __gen5_write(16) |
| 512 | __gen5_write(32) |
| 513 | __gen5_write(64) |
| 514 | __gen4_write(8) |
| 515 | __gen4_write(16) |
| 516 | __gen4_write(32) |
| 517 | __gen4_write(64) |
| 518 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 519 | #undef __gen8_write |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 520 | #undef __hsw_write |
| 521 | #undef __gen6_write |
| 522 | #undef __gen5_write |
| 523 | #undef __gen4_write |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 524 | #undef REG_WRITE_HEADER |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 525 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 526 | void intel_uncore_init(struct drm_device *dev) |
| 527 | { |
| 528 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 529 | |
| 530 | INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work, |
| 531 | gen6_force_wake_work); |
| 532 | |
| 533 | if (IS_VALLEYVIEW(dev)) { |
| 534 | dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get; |
| 535 | dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put; |
Ben Widawsky | 43d1b64 | 2013-11-07 16:24:31 -0800 | [diff] [blame] | 536 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 537 | dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; |
| 538 | dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; |
| 539 | } else if (IS_IVYBRIDGE(dev)) { |
| 540 | u32 ecobus; |
| 541 | |
| 542 | /* IVB configs may use multi-threaded forcewake */ |
| 543 | |
| 544 | /* A small trick here - if the bios hasn't configured |
| 545 | * MT forcewake, and if the device is in RC6, then |
| 546 | * force_wake_mt_get will not wake the device and the |
| 547 | * ECOBUS read will return zero. Which will be |
| 548 | * (correctly) interpreted by the test below as MT |
| 549 | * forcewake being disabled. |
| 550 | */ |
| 551 | mutex_lock(&dev->struct_mutex); |
| 552 | __gen6_gt_force_wake_mt_get(dev_priv); |
| 553 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
| 554 | __gen6_gt_force_wake_mt_put(dev_priv); |
| 555 | mutex_unlock(&dev->struct_mutex); |
| 556 | |
| 557 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 558 | dev_priv->uncore.funcs.force_wake_get = |
| 559 | __gen6_gt_force_wake_mt_get; |
| 560 | dev_priv->uncore.funcs.force_wake_put = |
| 561 | __gen6_gt_force_wake_mt_put; |
| 562 | } else { |
| 563 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
| 564 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
| 565 | dev_priv->uncore.funcs.force_wake_get = |
| 566 | __gen6_gt_force_wake_get; |
| 567 | dev_priv->uncore.funcs.force_wake_put = |
| 568 | __gen6_gt_force_wake_put; |
| 569 | } |
| 570 | } else if (IS_GEN6(dev)) { |
| 571 | dev_priv->uncore.funcs.force_wake_get = |
| 572 | __gen6_gt_force_wake_get; |
| 573 | dev_priv->uncore.funcs.force_wake_put = |
| 574 | __gen6_gt_force_wake_put; |
| 575 | } |
| 576 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 577 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 578 | default: |
| 579 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; |
| 580 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; |
| 581 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; |
| 582 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; |
| 583 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 584 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 585 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 586 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 587 | break; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 588 | case 7: |
| 589 | case 6: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 590 | if (IS_HASWELL(dev)) { |
| 591 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; |
| 592 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; |
| 593 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; |
| 594 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; |
| 595 | } else { |
| 596 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; |
| 597 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; |
| 598 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; |
| 599 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; |
| 600 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 601 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 602 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 603 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 604 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 605 | break; |
| 606 | case 5: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 607 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
| 608 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; |
| 609 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; |
| 610 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 611 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
| 612 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; |
| 613 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; |
| 614 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; |
| 615 | break; |
| 616 | case 4: |
| 617 | case 3: |
| 618 | case 2: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 619 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
| 620 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; |
| 621 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; |
| 622 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 623 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
| 624 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; |
| 625 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; |
| 626 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; |
| 627 | break; |
| 628 | } |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | void intel_uncore_fini(struct drm_device *dev) |
| 632 | { |
| 633 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 634 | |
| 635 | flush_delayed_work(&dev_priv->uncore.force_wake_work); |
| 636 | |
| 637 | /* Paranoia: make sure we have disabled everything before we exit. */ |
| 638 | intel_uncore_sanitize(dev); |
| 639 | } |
| 640 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 641 | static const struct register_whitelist { |
| 642 | uint64_t offset; |
| 643 | uint32_t size; |
| 644 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 645 | } whitelist[] = { |
| 646 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, |
| 647 | }; |
| 648 | |
| 649 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 650 | void *data, struct drm_file *file) |
| 651 | { |
| 652 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 653 | struct drm_i915_reg_read *reg = data; |
| 654 | struct register_whitelist const *entry = whitelist; |
| 655 | int i; |
| 656 | |
| 657 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 658 | if (entry->offset == reg->offset && |
| 659 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 660 | break; |
| 661 | } |
| 662 | |
| 663 | if (i == ARRAY_SIZE(whitelist)) |
| 664 | return -EINVAL; |
| 665 | |
| 666 | switch (entry->size) { |
| 667 | case 8: |
| 668 | reg->val = I915_READ64(reg->offset); |
| 669 | break; |
| 670 | case 4: |
| 671 | reg->val = I915_READ(reg->offset); |
| 672 | break; |
| 673 | case 2: |
| 674 | reg->val = I915_READ16(reg->offset); |
| 675 | break; |
| 676 | case 1: |
| 677 | reg->val = I915_READ8(reg->offset); |
| 678 | break; |
| 679 | default: |
| 680 | WARN_ON(1); |
| 681 | return -EINVAL; |
| 682 | } |
| 683 | |
| 684 | return 0; |
| 685 | } |
| 686 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 687 | static int i965_reset_complete(struct drm_device *dev) |
| 688 | { |
| 689 | u8 gdrst; |
| 690 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 691 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
| 692 | } |
| 693 | |
| 694 | static int i965_do_reset(struct drm_device *dev) |
| 695 | { |
| 696 | int ret; |
| 697 | |
| 698 | /* |
| 699 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 700 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 701 | * triggers the reset; when done, the hardware will clear it. |
| 702 | */ |
| 703 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 704 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 705 | ret = wait_for(i965_reset_complete(dev), 500); |
| 706 | if (ret) |
| 707 | return ret; |
| 708 | |
| 709 | /* We can't reset render&media without also resetting display ... */ |
| 710 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 711 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 712 | |
| 713 | ret = wait_for(i965_reset_complete(dev), 500); |
| 714 | if (ret) |
| 715 | return ret; |
| 716 | |
| 717 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 718 | |
| 719 | return 0; |
| 720 | } |
| 721 | |
| 722 | static int ironlake_do_reset(struct drm_device *dev) |
| 723 | { |
| 724 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 725 | u32 gdrst; |
| 726 | int ret; |
| 727 | |
| 728 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 729 | gdrst &= ~GRDOM_MASK; |
| 730 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 731 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 732 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 733 | if (ret) |
| 734 | return ret; |
| 735 | |
| 736 | /* We can't reset render&media without also resetting display ... */ |
| 737 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 738 | gdrst &= ~GRDOM_MASK; |
| 739 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 740 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 741 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 742 | } |
| 743 | |
| 744 | static int gen6_do_reset(struct drm_device *dev) |
| 745 | { |
| 746 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 747 | int ret; |
| 748 | unsigned long irqflags; |
| 749 | |
| 750 | /* Hold uncore.lock across reset to prevent any register access |
| 751 | * with forcewake not set correctly |
| 752 | */ |
| 753 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 754 | |
| 755 | /* Reset the chip */ |
| 756 | |
| 757 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 758 | * for fifo space for the write or forcewake the chip for |
| 759 | * the read |
| 760 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 761 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 762 | |
| 763 | /* Spin waiting for the device to ack the reset request */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 764 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 765 | |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 766 | intel_uncore_forcewake_reset(dev); |
| 767 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 768 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
| 769 | if (dev_priv->uncore.forcewake_count) |
| 770 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
| 771 | else |
| 772 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
| 773 | |
| 774 | /* Restore fifo count */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 775 | dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 776 | |
| 777 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 778 | return ret; |
| 779 | } |
| 780 | |
| 781 | int intel_gpu_reset(struct drm_device *dev) |
| 782 | { |
| 783 | switch (INTEL_INFO(dev)->gen) { |
| 784 | case 7: |
| 785 | case 6: return gen6_do_reset(dev); |
| 786 | case 5: return ironlake_do_reset(dev); |
| 787 | case 4: return i965_do_reset(dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 788 | default: return -ENODEV; |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | void intel_uncore_clear_errors(struct drm_device *dev) |
| 793 | { |
| 794 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 795 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 796 | /* XXX needs spinlock around caller's grouping */ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 797 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 798 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | void intel_uncore_check_errors(struct drm_device *dev) |
| 802 | { |
| 803 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 804 | |
| 805 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 806 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 807 | DRM_ERROR("Unclaimed register before interrupt\n"); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 808 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 809 | } |
| 810 | } |