R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 10 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 12 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 13 | #include "skeleton.dtsi" |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 14 | |
| 15 | / { |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 19 | compatible = "ti,omap5"; |
| 20 | interrupt-parent = <&gic>; |
| 21 | |
| 22 | aliases { |
| 23 | serial0 = &uart1; |
| 24 | serial1 = &uart2; |
| 25 | serial2 = &uart3; |
| 26 | serial3 = &uart4; |
| 27 | serial4 = &uart5; |
| 28 | serial5 = &uart6; |
| 29 | }; |
| 30 | |
| 31 | cpus { |
| 32 | cpu@0 { |
| 33 | compatible = "arm,cortex-a15"; |
| 34 | }; |
| 35 | cpu@1 { |
| 36 | compatible = "arm,cortex-a15"; |
| 37 | }; |
| 38 | }; |
| 39 | |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 40 | timer { |
| 41 | compatible = "arm,armv7-timer"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 42 | /* PPI secure/nonsecure IRQ */ |
| 43 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 44 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 45 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 46 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 47 | clock-frequency = <6144000>; |
| 48 | }; |
| 49 | |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 50 | gic: interrupt-controller@48211000 { |
| 51 | compatible = "arm,cortex-a15-gic"; |
| 52 | interrupt-controller; |
| 53 | #interrupt-cells = <3>; |
| 54 | reg = <0x48211000 0x1000>, |
Santosh Shilimkar | 0129c16 | 2013-02-19 17:29:24 +0530 | [diff] [blame] | 55 | <0x48212000 0x1000>, |
| 56 | <0x48214000 0x2000>, |
| 57 | <0x48216000 0x2000>; |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 58 | }; |
| 59 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 60 | /* |
| 61 | * The soc node represents the soc top level view. It is uses for IPs |
| 62 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 63 | */ |
| 64 | soc { |
| 65 | compatible = "ti,omap-infra"; |
| 66 | mpu { |
| 67 | compatible = "ti,omap5-mpu"; |
| 68 | ti,hwmods = "mpu"; |
| 69 | }; |
| 70 | }; |
| 71 | |
| 72 | /* |
| 73 | * XXX: Use a flat representation of the OMAP3 interconnect. |
| 74 | * The real OMAP interconnect network is quite complex. |
| 75 | * Since that will not bring real advantage to represent that in DT for |
| 76 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 77 | * hierarchy. |
| 78 | */ |
| 79 | ocp { |
| 80 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
| 81 | #address-cells = <1>; |
| 82 | #size-cells = <1>; |
| 83 | ranges; |
| 84 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
Santosh Shilimkar | 20a60ea | 2013-02-26 17:36:14 +0530 | [diff] [blame] | 85 | reg = <0x44000000 0x2000>, |
| 86 | <0x44800000 0x3000>, |
| 87 | <0x45000000 0x4000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 88 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 89 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 90 | |
Jon Hunter | 3b3132f | 2012-11-01 09:12:23 -0500 | [diff] [blame] | 91 | counter32k: counter@4ae04000 { |
| 92 | compatible = "ti,omap-counter32k"; |
| 93 | reg = <0x4ae04000 0x40>; |
| 94 | ti,hwmods = "counter_32k"; |
| 95 | }; |
| 96 | |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 97 | omap5_pmx_core: pinmux@4a002840 { |
| 98 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 99 | reg = <0x4a002840 0x01b6>; |
| 100 | #address-cells = <1>; |
| 101 | #size-cells = <0>; |
| 102 | pinctrl-single,register-width = <16>; |
| 103 | pinctrl-single,function-mask = <0x7fff>; |
| 104 | }; |
| 105 | omap5_pmx_wkup: pinmux@4ae0c840 { |
| 106 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 107 | reg = <0x4ae0c840 0x0038>; |
| 108 | #address-cells = <1>; |
| 109 | #size-cells = <0>; |
| 110 | pinctrl-single,register-width = <16>; |
| 111 | pinctrl-single,function-mask = <0x7fff>; |
| 112 | }; |
| 113 | |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 114 | sdma: dma-controller@4a056000 { |
| 115 | compatible = "ti,omap4430-sdma"; |
| 116 | reg = <0x4a056000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 117 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 118 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 119 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 120 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 121 | #dma-cells = <1>; |
| 122 | #dma-channels = <32>; |
| 123 | #dma-requests = <127>; |
| 124 | }; |
| 125 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 126 | gpio1: gpio@4ae10000 { |
| 127 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 128 | reg = <0x4ae10000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 129 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 130 | ti,hwmods = "gpio1"; |
Jon Hunter | e4b9b9f | 2013-04-04 15:16:16 -0500 | [diff] [blame] | 131 | ti,gpio-always-on; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 132 | gpio-controller; |
| 133 | #gpio-cells = <2>; |
| 134 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 135 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | gpio2: gpio@48055000 { |
| 139 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 140 | reg = <0x48055000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 141 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 142 | ti,hwmods = "gpio2"; |
| 143 | gpio-controller; |
| 144 | #gpio-cells = <2>; |
| 145 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 146 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 147 | }; |
| 148 | |
| 149 | gpio3: gpio@48057000 { |
| 150 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 151 | reg = <0x48057000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 152 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 153 | ti,hwmods = "gpio3"; |
| 154 | gpio-controller; |
| 155 | #gpio-cells = <2>; |
| 156 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 157 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 158 | }; |
| 159 | |
| 160 | gpio4: gpio@48059000 { |
| 161 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 162 | reg = <0x48059000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 163 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 164 | ti,hwmods = "gpio4"; |
| 165 | gpio-controller; |
| 166 | #gpio-cells = <2>; |
| 167 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 168 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 169 | }; |
| 170 | |
| 171 | gpio5: gpio@4805b000 { |
| 172 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 173 | reg = <0x4805b000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 174 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 175 | ti,hwmods = "gpio5"; |
| 176 | gpio-controller; |
| 177 | #gpio-cells = <2>; |
| 178 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 179 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 180 | }; |
| 181 | |
| 182 | gpio6: gpio@4805d000 { |
| 183 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 184 | reg = <0x4805d000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 185 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 186 | ti,hwmods = "gpio6"; |
| 187 | gpio-controller; |
| 188 | #gpio-cells = <2>; |
| 189 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 190 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | gpio7: gpio@48051000 { |
| 194 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 195 | reg = <0x48051000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 196 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 197 | ti,hwmods = "gpio7"; |
| 198 | gpio-controller; |
| 199 | #gpio-cells = <2>; |
| 200 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 201 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 202 | }; |
| 203 | |
| 204 | gpio8: gpio@48053000 { |
| 205 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 206 | reg = <0x48053000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 207 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 208 | ti,hwmods = "gpio8"; |
| 209 | gpio-controller; |
| 210 | #gpio-cells = <2>; |
| 211 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 212 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 213 | }; |
| 214 | |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 215 | gpmc: gpmc@50000000 { |
| 216 | compatible = "ti,omap4430-gpmc"; |
| 217 | reg = <0x50000000 0x1000>; |
| 218 | #address-cells = <2>; |
| 219 | #size-cells = <1>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 220 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 221 | gpmc,num-cs = <8>; |
| 222 | gpmc,num-waitpins = <4>; |
| 223 | ti,hwmods = "gpmc"; |
| 224 | }; |
| 225 | |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 226 | i2c1: i2c@48070000 { |
| 227 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 228 | reg = <0x48070000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 229 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 230 | #address-cells = <1>; |
| 231 | #size-cells = <0>; |
| 232 | ti,hwmods = "i2c1"; |
| 233 | }; |
| 234 | |
| 235 | i2c2: i2c@48072000 { |
| 236 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 237 | reg = <0x48072000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 238 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 239 | #address-cells = <1>; |
| 240 | #size-cells = <0>; |
| 241 | ti,hwmods = "i2c2"; |
| 242 | }; |
| 243 | |
| 244 | i2c3: i2c@48060000 { |
| 245 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 246 | reg = <0x48060000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 247 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 248 | #address-cells = <1>; |
| 249 | #size-cells = <0>; |
| 250 | ti,hwmods = "i2c3"; |
| 251 | }; |
| 252 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 253 | i2c4: i2c@4807a000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 254 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 255 | reg = <0x4807a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 256 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 257 | #address-cells = <1>; |
| 258 | #size-cells = <0>; |
| 259 | ti,hwmods = "i2c4"; |
| 260 | }; |
| 261 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 262 | i2c5: i2c@4807c000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 263 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 264 | reg = <0x4807c000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 265 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 266 | #address-cells = <1>; |
| 267 | #size-cells = <0>; |
| 268 | ti,hwmods = "i2c5"; |
| 269 | }; |
| 270 | |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 271 | mcspi1: spi@48098000 { |
| 272 | compatible = "ti,omap4-mcspi"; |
| 273 | reg = <0x48098000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 274 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 275 | #address-cells = <1>; |
| 276 | #size-cells = <0>; |
| 277 | ti,hwmods = "mcspi1"; |
| 278 | ti,spi-num-cs = <4>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 279 | dmas = <&sdma 35>, |
| 280 | <&sdma 36>, |
| 281 | <&sdma 37>, |
| 282 | <&sdma 38>, |
| 283 | <&sdma 39>, |
| 284 | <&sdma 40>, |
| 285 | <&sdma 41>, |
| 286 | <&sdma 42>; |
| 287 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 288 | "tx2", "rx2", "tx3", "rx3"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | mcspi2: spi@4809a000 { |
| 292 | compatible = "ti,omap4-mcspi"; |
| 293 | reg = <0x4809a000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 294 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 295 | #address-cells = <1>; |
| 296 | #size-cells = <0>; |
| 297 | ti,hwmods = "mcspi2"; |
| 298 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 299 | dmas = <&sdma 43>, |
| 300 | <&sdma 44>, |
| 301 | <&sdma 45>, |
| 302 | <&sdma 46>; |
| 303 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 304 | }; |
| 305 | |
| 306 | mcspi3: spi@480b8000 { |
| 307 | compatible = "ti,omap4-mcspi"; |
| 308 | reg = <0x480b8000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 309 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 310 | #address-cells = <1>; |
| 311 | #size-cells = <0>; |
| 312 | ti,hwmods = "mcspi3"; |
| 313 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 314 | dmas = <&sdma 15>, <&sdma 16>; |
| 315 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 316 | }; |
| 317 | |
| 318 | mcspi4: spi@480ba000 { |
| 319 | compatible = "ti,omap4-mcspi"; |
| 320 | reg = <0x480ba000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 321 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 322 | #address-cells = <1>; |
| 323 | #size-cells = <0>; |
| 324 | ti,hwmods = "mcspi4"; |
| 325 | ti,spi-num-cs = <1>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 326 | dmas = <&sdma 70>, <&sdma 71>; |
| 327 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 328 | }; |
| 329 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 330 | uart1: serial@4806a000 { |
| 331 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 332 | reg = <0x4806a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 333 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 334 | ti,hwmods = "uart1"; |
| 335 | clock-frequency = <48000000>; |
| 336 | }; |
| 337 | |
| 338 | uart2: serial@4806c000 { |
| 339 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 340 | reg = <0x4806c000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 341 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 342 | ti,hwmods = "uart2"; |
| 343 | clock-frequency = <48000000>; |
| 344 | }; |
| 345 | |
| 346 | uart3: serial@48020000 { |
| 347 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 348 | reg = <0x48020000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 349 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 350 | ti,hwmods = "uart3"; |
| 351 | clock-frequency = <48000000>; |
| 352 | }; |
| 353 | |
| 354 | uart4: serial@4806e000 { |
| 355 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 356 | reg = <0x4806e000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 357 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 358 | ti,hwmods = "uart4"; |
| 359 | clock-frequency = <48000000>; |
| 360 | }; |
| 361 | |
| 362 | uart5: serial@48066000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 363 | compatible = "ti,omap4-uart"; |
| 364 | reg = <0x48066000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 365 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 366 | ti,hwmods = "uart5"; |
| 367 | clock-frequency = <48000000>; |
| 368 | }; |
| 369 | |
| 370 | uart6: serial@48068000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 371 | compatible = "ti,omap4-uart"; |
| 372 | reg = <0x48068000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 373 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 374 | ti,hwmods = "uart6"; |
| 375 | clock-frequency = <48000000>; |
| 376 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 377 | |
| 378 | mmc1: mmc@4809c000 { |
| 379 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 380 | reg = <0x4809c000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 381 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 382 | ti,hwmods = "mmc1"; |
| 383 | ti,dual-volt; |
| 384 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 385 | dmas = <&sdma 61>, <&sdma 62>; |
| 386 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | mmc2: mmc@480b4000 { |
| 390 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 391 | reg = <0x480b4000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 392 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 393 | ti,hwmods = "mmc2"; |
| 394 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 395 | dmas = <&sdma 47>, <&sdma 48>; |
| 396 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 397 | }; |
| 398 | |
| 399 | mmc3: mmc@480ad000 { |
| 400 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 401 | reg = <0x480ad000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 402 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 403 | ti,hwmods = "mmc3"; |
| 404 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 405 | dmas = <&sdma 77>, <&sdma 78>; |
| 406 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 407 | }; |
| 408 | |
| 409 | mmc4: mmc@480d1000 { |
| 410 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 411 | reg = <0x480d1000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 412 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 413 | ti,hwmods = "mmc4"; |
| 414 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 415 | dmas = <&sdma 57>, <&sdma 58>; |
| 416 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 417 | }; |
| 418 | |
| 419 | mmc5: mmc@480d5000 { |
| 420 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 421 | reg = <0x480d5000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 422 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 423 | ti,hwmods = "mmc5"; |
| 424 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 425 | dmas = <&sdma 59>, <&sdma 60>; |
| 426 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 427 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 428 | |
| 429 | keypad: keypad@4ae1c000 { |
| 430 | compatible = "ti,omap4-keypad"; |
Santosh Shilimkar | 8cc8b89 | 2013-01-23 19:53:30 +0530 | [diff] [blame] | 431 | reg = <0x4ae1c000 0x400>; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 432 | ti,hwmods = "kbd"; |
| 433 | }; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 434 | |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 435 | mcpdm: mcpdm@40132000 { |
| 436 | compatible = "ti,omap4-mcpdm"; |
| 437 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 438 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 439 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 440 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 441 | ti,hwmods = "mcpdm"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 442 | dmas = <&sdma 65>, |
| 443 | <&sdma 66>; |
| 444 | dma-names = "up_link", "dn_link"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 445 | }; |
| 446 | |
| 447 | dmic: dmic@4012e000 { |
| 448 | compatible = "ti,omap4-dmic"; |
| 449 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 450 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 451 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 452 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 453 | ti,hwmods = "dmic"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 454 | dmas = <&sdma 67>; |
| 455 | dma-names = "up_link"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 456 | }; |
| 457 | |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 458 | mcbsp1: mcbsp@40122000 { |
| 459 | compatible = "ti,omap4-mcbsp"; |
| 460 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 461 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 462 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 463 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 464 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 465 | ti,buffer-size = <128>; |
| 466 | ti,hwmods = "mcbsp1"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 467 | dmas = <&sdma 33>, |
| 468 | <&sdma 34>; |
| 469 | dma-names = "tx", "rx"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 470 | }; |
| 471 | |
| 472 | mcbsp2: mcbsp@40124000 { |
| 473 | compatible = "ti,omap4-mcbsp"; |
| 474 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 475 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 476 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 477 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 478 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 479 | ti,buffer-size = <128>; |
| 480 | ti,hwmods = "mcbsp2"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 481 | dmas = <&sdma 17>, |
| 482 | <&sdma 18>; |
| 483 | dma-names = "tx", "rx"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 484 | }; |
| 485 | |
| 486 | mcbsp3: mcbsp@40126000 { |
| 487 | compatible = "ti,omap4-mcbsp"; |
| 488 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 489 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 490 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 491 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 492 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 493 | ti,buffer-size = <128>; |
| 494 | ti,hwmods = "mcbsp3"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 495 | dmas = <&sdma 19>, |
| 496 | <&sdma 20>; |
| 497 | dma-names = "tx", "rx"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 498 | }; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 499 | |
| 500 | timer1: timer@4ae18000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 501 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 502 | reg = <0x4ae18000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 503 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 504 | ti,hwmods = "timer1"; |
| 505 | ti,timer-alwon; |
| 506 | }; |
| 507 | |
| 508 | timer2: timer@48032000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 509 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 510 | reg = <0x48032000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 511 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 512 | ti,hwmods = "timer2"; |
| 513 | }; |
| 514 | |
| 515 | timer3: timer@48034000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 516 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 517 | reg = <0x48034000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 518 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 519 | ti,hwmods = "timer3"; |
| 520 | }; |
| 521 | |
| 522 | timer4: timer@48036000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 523 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 524 | reg = <0x48036000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 525 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 526 | ti,hwmods = "timer4"; |
| 527 | }; |
| 528 | |
| 529 | timer5: timer@40138000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 530 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 531 | reg = <0x40138000 0x80>, |
| 532 | <0x49038000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 533 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 534 | ti,hwmods = "timer5"; |
| 535 | ti,timer-dsp; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 536 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 537 | }; |
| 538 | |
| 539 | timer6: timer@4013a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 540 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 541 | reg = <0x4013a000 0x80>, |
| 542 | <0x4903a000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 543 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 544 | ti,hwmods = "timer6"; |
| 545 | ti,timer-dsp; |
| 546 | ti,timer-pwm; |
| 547 | }; |
| 548 | |
| 549 | timer7: timer@4013c000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 550 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 551 | reg = <0x4013c000 0x80>, |
| 552 | <0x4903c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 553 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 554 | ti,hwmods = "timer7"; |
| 555 | ti,timer-dsp; |
| 556 | }; |
| 557 | |
| 558 | timer8: timer@4013e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 559 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 560 | reg = <0x4013e000 0x80>, |
| 561 | <0x4903e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 562 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 563 | ti,hwmods = "timer8"; |
| 564 | ti,timer-dsp; |
| 565 | ti,timer-pwm; |
| 566 | }; |
| 567 | |
| 568 | timer9: timer@4803e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 569 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 570 | reg = <0x4803e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 571 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 572 | ti,hwmods = "timer9"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 573 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 574 | }; |
| 575 | |
| 576 | timer10: timer@48086000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 577 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 578 | reg = <0x48086000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 579 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 580 | ti,hwmods = "timer10"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 581 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 582 | }; |
| 583 | |
| 584 | timer11: timer@48088000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 585 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 586 | reg = <0x48088000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 587 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 588 | ti,hwmods = "timer11"; |
| 589 | ti,timer-pwm; |
| 590 | }; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 591 | |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 592 | wdt2: wdt@4ae14000 { |
| 593 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; |
| 594 | reg = <0x4ae14000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 595 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 596 | ti,hwmods = "wd_timer2"; |
| 597 | }; |
| 598 | |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 599 | emif1: emif@0x4c000000 { |
| 600 | compatible = "ti,emif-4d5"; |
| 601 | ti,hwmods = "emif1"; |
| 602 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 603 | reg = <0x4c000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 604 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 605 | hw-caps-read-idle-ctrl; |
| 606 | hw-caps-ll-interface; |
| 607 | hw-caps-temp-alert; |
| 608 | }; |
| 609 | |
| 610 | emif2: emif@0x4d000000 { |
| 611 | compatible = "ti,emif-4d5"; |
| 612 | ti,hwmods = "emif2"; |
| 613 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 614 | reg = <0x4d000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 615 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 616 | hw-caps-read-idle-ctrl; |
| 617 | hw-caps-ll-interface; |
| 618 | hw-caps-temp-alert; |
| 619 | }; |
Kishon Vijay Abraham I | fedc428 | 2013-03-07 19:05:17 +0530 | [diff] [blame] | 620 | |
| 621 | omap_control_usb: omap-control-usb@4a002300 { |
| 622 | compatible = "ti,omap-control-usb"; |
| 623 | reg = <0x4a002300 0x4>, |
| 624 | <0x4a002370 0x4>; |
| 625 | reg-names = "control_dev_conf", "phy_power_usb"; |
| 626 | ti,type = <2>; |
| 627 | }; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 628 | |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 629 | omap_dwc3@4a020000 { |
| 630 | compatible = "ti,dwc3"; |
| 631 | ti,hwmods = "usb_otg_ss"; |
| 632 | reg = <0x4a020000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 633 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 634 | #address-cells = <1>; |
| 635 | #size-cells = <1>; |
| 636 | utmi-mode = <2>; |
| 637 | ranges; |
| 638 | dwc3@4a030000 { |
| 639 | compatible = "synopsys,dwc3"; |
| 640 | reg = <0x4a030000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame^] | 641 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 642 | usb-phy = <&usb2_phy>, <&usb3_phy>; |
| 643 | tx-fifo-resize; |
| 644 | }; |
| 645 | }; |
| 646 | |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 647 | ocp2scp { |
| 648 | compatible = "ti,omap-ocp2scp"; |
| 649 | #address-cells = <1>; |
| 650 | #size-cells = <1>; |
| 651 | ranges; |
| 652 | ti,hwmods = "ocp2scp1"; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 653 | usb2_phy: usb2phy@4a084000 { |
| 654 | compatible = "ti,omap-usb2"; |
| 655 | reg = <0x4a084000 0x7c>; |
| 656 | ctrl-module = <&omap_control_usb>; |
| 657 | }; |
| 658 | |
| 659 | usb3_phy: usb3phy@4a084400 { |
| 660 | compatible = "ti,omap-usb3"; |
| 661 | reg = <0x4a084400 0x80>, |
| 662 | <0x4a084800 0x64>, |
| 663 | <0x4a084c00 0x40>; |
| 664 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 665 | ctrl-module = <&omap_control_usb>; |
| 666 | }; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 667 | }; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 668 | }; |
| 669 | }; |