Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 1 | /* |
| 2 | * setup.c: Setup pointers to hardware dependent routines. |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU General Public |
| 5 | * License. See the file "COPYING" in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) |
| 9 | * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com> |
| 10 | */ |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 11 | #include <linux/init.h> |
| 12 | #include <linux/string.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/tty.h> |
| 15 | #include <linux/serial.h> |
| 16 | #include <linux/serial_core.h> |
Yinghai Lu | b187f18 | 2007-07-18 00:49:10 -0700 | [diff] [blame] | 17 | #include <linux/serial_8250.h> |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 18 | #include <linux/pm.h> |
| 19 | |
| 20 | #include <asm/io.h> |
| 21 | #include <asm/bootinfo.h> |
| 22 | #include <asm/reboot.h> |
| 23 | #include <asm/time.h> |
| 24 | #include <asm/gt64120.h> |
| 25 | |
| 26 | unsigned long gt64120_base = KSEG1ADDR(0x14000000); |
| 27 | |
| 28 | #ifdef WRPPMC_EARLY_DEBUG |
| 29 | |
| 30 | static volatile unsigned char * wrppmc_led = \ |
| 31 | (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE); |
| 32 | |
| 33 | /* |
| 34 | * PPMC LED control register: |
| 35 | * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON) |
| 36 | * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON) |
| 37 | * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON) |
| 38 | */ |
| 39 | void wrppmc_led_on(int mask) |
| 40 | { |
| 41 | unsigned char value = *wrppmc_led; |
| 42 | |
| 43 | value &= (0xF8 | mask); |
| 44 | *wrppmc_led = value; |
| 45 | } |
| 46 | |
| 47 | /* If mask = 0, turn off all LEDs */ |
| 48 | void wrppmc_led_off(int mask) |
| 49 | { |
| 50 | unsigned char value = *wrppmc_led; |
| 51 | |
| 52 | value |= (0x7 & mask); |
| 53 | *wrppmc_led = value; |
| 54 | } |
| 55 | |
| 56 | /* |
| 57 | * We assume that bootloader has initialized UART16550 correctly |
| 58 | */ |
| 59 | void __init wrppmc_early_putc(char ch) |
| 60 | { |
| 61 | static volatile unsigned char *wrppmc_uart = \ |
| 62 | (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE); |
| 63 | unsigned char value; |
| 64 | |
| 65 | /* Wait until Transmit-Holding-Register is empty */ |
| 66 | while (1) { |
| 67 | value = *(wrppmc_uart + 5); |
| 68 | if (value & 0x20) |
| 69 | break; |
| 70 | } |
| 71 | |
| 72 | *wrppmc_uart = ch; |
| 73 | } |
| 74 | |
| 75 | void __init wrppmc_early_printk(const char *fmt, ...) |
| 76 | { |
| 77 | static char pbuf[256] = {'\0', }; |
| 78 | char *ch = pbuf; |
| 79 | va_list args; |
| 80 | unsigned int i; |
| 81 | |
| 82 | memset(pbuf, 0, 256); |
| 83 | va_start(args, fmt); |
| 84 | i = vsprintf(pbuf, fmt, args); |
| 85 | va_end(args); |
| 86 | |
| 87 | /* Print the string */ |
| 88 | while (*ch != '\0') { |
| 89 | wrppmc_early_putc(*ch); |
| 90 | /* if print '\n', also print '\r' */ |
| 91 | if (*ch++ == '\n') |
| 92 | wrppmc_early_putc('\r'); |
| 93 | } |
| 94 | } |
| 95 | #endif /* WRPPMC_EARLY_DEBUG */ |
| 96 | |
Atsushi Nemoto | c44e8d5 | 2006-12-30 00:43:59 +0900 | [diff] [blame] | 97 | void __init prom_free_prom_memory(void) |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 98 | { |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | #ifdef CONFIG_SERIAL_8250 |
| 102 | static void wrppmc_setup_serial(void) |
| 103 | { |
| 104 | struct uart_port up; |
| 105 | |
| 106 | memset(&up, 0x00, sizeof(struct uart_port)); |
| 107 | |
| 108 | /* |
| 109 | * A note about mapbase/membase |
| 110 | * -) mapbase is the physical address of the IO port. |
| 111 | * -) membase is an 'ioremapped' cookie. |
| 112 | */ |
| 113 | up.line = 0; |
| 114 | up.type = PORT_16550; |
| 115 | up.iotype = UPIO_MEM; |
| 116 | up.mapbase = WRPPMC_UART16550_BASE; |
| 117 | up.membase = ioremap(up.mapbase, 8); |
| 118 | up.irq = WRPPMC_UART16550_IRQ; |
| 119 | up.uartclk = WRPPMC_UART16550_CLOCK; |
| 120 | up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */; |
| 121 | up.regshift = 0; |
| 122 | |
| 123 | early_serial_setup(&up); |
| 124 | } |
| 125 | #endif |
| 126 | |
Mark.Zhan | 9247857 | 2006-06-20 18:15:02 +0800 | [diff] [blame] | 127 | void __init plat_mem_setup(void) |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 128 | { |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 129 | extern void wrppmc_machine_restart(char *command); |
| 130 | extern void wrppmc_machine_halt(void); |
| 131 | extern void wrppmc_machine_power_off(void); |
| 132 | |
| 133 | _machine_restart = wrppmc_machine_restart; |
| 134 | _machine_halt = wrppmc_machine_halt; |
| 135 | pm_power_off = wrppmc_machine_power_off; |
| 136 | |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 137 | /* This makes the operations of 'in/out[bwl]' to the |
| 138 | * physical address ( < KSEG0) can work via KSEG1 |
| 139 | */ |
| 140 | set_io_port_base(KSEG1); |
| 141 | |
| 142 | #ifdef CONFIG_SERIAL_8250 |
| 143 | wrppmc_setup_serial(); |
| 144 | #endif |
| 145 | } |
| 146 | |
| 147 | const char *get_system_type(void) |
| 148 | { |
| 149 | return "Wind River PPMC (GT64120)"; |
| 150 | } |
| 151 | |
| 152 | /* |
| 153 | * Initializes basic routines and structures pointers, memory size (as |
| 154 | * given by the bios and saves the command line. |
| 155 | */ |
| 156 | void __init prom_init(void) |
| 157 | { |
Ralf Baechle | 569fb75 | 2007-07-10 16:56:33 +0100 | [diff] [blame] | 158 | mips_machtype = MACH_WRPPMC; |
Mark.Zhan | a240a46 | 2006-05-06 17:04:20 +0800 | [diff] [blame] | 159 | |
| 160 | add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); |
| 161 | add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); |
| 162 | |
| 163 | wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n", |
| 164 | WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE)); |
| 165 | } |