Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Cobalt Qube/Raq PCI support |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU General Public |
| 5 | * License. See the file "COPYING" in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle |
| 9 | * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) |
| 10 | */ |
| 11 | #include <linux/types.h> |
| 12 | #include <linux/pci.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | |
| 16 | #include <asm/pci.h> |
| 17 | #include <asm/io.h> |
| 18 | #include <asm/gt64120.h> |
| 19 | |
Yoichi Yuasa | 44320f2 | 2007-05-10 20:00:55 +0900 | [diff] [blame] | 20 | #include <cobalt.h> |
Yoichi Yuasa | d5ab1a6 | 2007-09-13 23:51:26 +0900 | [diff] [blame] | 21 | #include <irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 23 | static void qube_raq_galileo_early_fixup(struct pci_dev *dev) |
| 24 | { |
| 25 | if (dev->devfn == PCI_DEVFN(0, 0) && |
| 26 | (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { |
| 27 | |
| 28 | dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); |
| 29 | |
| 30 | printk(KERN_INFO "Galileo: fixed bridge class\n"); |
| 31 | } |
| 32 | } |
| 33 | |
| 34 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, |
| 35 | qube_raq_galileo_early_fixup); |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) |
| 38 | { |
| 39 | unsigned short cfgword; |
| 40 | unsigned char lt; |
| 41 | |
| 42 | /* Enable Bus Mastering and fast back to back. */ |
| 43 | pci_read_config_word(dev, PCI_COMMAND, &cfgword); |
| 44 | cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER); |
| 45 | pci_write_config_word(dev, PCI_COMMAND, cfgword); |
| 46 | |
| 47 | /* Enable both ide interfaces. ROM only enables primary one. */ |
| 48 | pci_write_config_byte(dev, 0x40, 0xb); |
| 49 | |
| 50 | /* Set latency timer to reasonable value. */ |
| 51 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); |
| 52 | if (lt < 64) |
| 53 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
Peter Horton | 5237844 | 2006-01-29 21:33:48 +0000 | [diff] [blame] | 54 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, |
| 58 | qube_raq_via_bmIDE_fixup); |
| 59 | |
| 60 | static void qube_raq_galileo_fixup(struct pci_dev *dev) |
| 61 | { |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 62 | if (dev->devfn != PCI_DEVFN(0, 0)) |
| 63 | return; |
| 64 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | /* Fix PCI latency-timer and cache-line-size values in Galileo |
| 66 | * host bridge. |
| 67 | */ |
| 68 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
Peter Horton | 5237844 | 2006-01-29 21:33:48 +0000 | [diff] [blame] | 69 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | |
| 71 | /* |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 72 | * The code described by the comment below has been removed |
| 73 | * as it causes bus mastering by the Ethernet controllers |
| 74 | * to break under any kind of network load. We always set |
| 75 | * the retry timeouts to their maximum. |
| 76 | * |
| 77 | * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- |
| 78 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | * On all machines prior to Q2, we had the STOP line disconnected |
| 80 | * from Galileo to VIA on PCI. The new Galileo does not function |
| 81 | * correctly unless we have it connected. |
| 82 | * |
| 83 | * Therefore we must set the disconnect/retry cycle values to |
| 84 | * something sensible when using the new Galileo. |
| 85 | */ |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 86 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 87 | printk(KERN_INFO "Galileo: revision %u\n", dev->revision); |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 88 | |
| 89 | #if 0 |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 90 | if (dev->revision >= 0x10) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | /* New Galileo, assumes PCI stop line to VIA is connected. */ |
Yoichi Yuasa | 56ae583 | 2006-10-14 00:25:04 +0900 | [diff] [blame] | 92 | GT_WRITE(GT_PCI0_TOR_OFS, 0x4020); |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 93 | } else if (dev->revision == 0x1 || dev->revision == 0x2) |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 94 | #endif |
| 95 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 96 | signed int timeo; |
| 97 | /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ |
Yoichi Yuasa | 56ae583 | 2006-10-14 00:25:04 +0900 | [diff] [blame] | 98 | timeo = GT_READ(GT_PCI0_TOR_OFS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ |
Yoichi Yuasa | 56ae583 | 2006-10-14 00:25:04 +0900 | [diff] [blame] | 100 | GT_WRITE(GT_PCI0_TOR_OFS, |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 101 | (0xff << 16) | /* retry count */ |
| 102 | (0xff << 8) | /* timeout 1 */ |
Yoichi Yuasa | 56ae583 | 2006-10-14 00:25:04 +0900 | [diff] [blame] | 103 | 0xff); /* timeout 0 */ |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 104 | |
| 105 | /* enable PCI retry exceeded interrupt */ |
Yoichi Yuasa | 56ae583 | 2006-10-14 00:25:04 +0900 | [diff] [blame] | 106 | GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | } |
| 108 | } |
| 109 | |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 110 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | qube_raq_galileo_fixup); |
| 112 | |
Yoichi Yuasa | 3f2d560 | 2007-05-11 21:43:09 +0900 | [diff] [blame] | 113 | int cobalt_board_id; |
| 114 | |
| 115 | static void qube_raq_via_board_id_fixup(struct pci_dev *dev) |
| 116 | { |
| 117 | u8 id; |
| 118 | int retval; |
| 119 | |
| 120 | retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id); |
| 121 | if (retval) { |
| 122 | panic("Cannot read board ID"); |
| 123 | return; |
| 124 | } |
| 125 | |
| 126 | cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id); |
| 127 | |
| 128 | printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id); |
| 129 | } |
| 130 | |
| 131 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, |
| 132 | qube_raq_via_board_id_fixup); |
| 133 | |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 134 | static char irq_tab_qube1[] __initdata = { |
| 135 | [COBALT_PCICONF_CPU] = 0, |
Yoichi Yuasa | d5ab1a6 | 2007-09-13 23:51:26 +0900 | [diff] [blame] | 136 | [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ, |
| 137 | [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 138 | [COBALT_PCICONF_VIA] = 0, |
Yoichi Yuasa | d5ab1a6 | 2007-09-13 23:51:26 +0900 | [diff] [blame] | 139 | [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 140 | [COBALT_PCICONF_ETH1] = 0 |
| 141 | }; |
| 142 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | static char irq_tab_cobalt[] __initdata = { |
| 144 | [COBALT_PCICONF_CPU] = 0, |
Yoichi Yuasa | d5ab1a6 | 2007-09-13 23:51:26 +0900 | [diff] [blame] | 145 | [COBALT_PCICONF_ETH0] = ETH0_IRQ, |
| 146 | [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | [COBALT_PCICONF_VIA] = 0, |
Yoichi Yuasa | d5ab1a6 | 2007-09-13 23:51:26 +0900 | [diff] [blame] | 148 | [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, |
| 149 | [COBALT_PCICONF_ETH1] = ETH1_IRQ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | static char irq_tab_raq2[] __initdata = { |
| 153 | [COBALT_PCICONF_CPU] = 0, |
Yoichi Yuasa | d5ab1a6 | 2007-09-13 23:51:26 +0900 | [diff] [blame] | 154 | [COBALT_PCICONF_ETH0] = ETH0_IRQ, |
| 155 | [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | [COBALT_PCICONF_VIA] = 0, |
Yoichi Yuasa | d5ab1a6 | 2007-09-13 23:51:26 +0900 | [diff] [blame] | 157 | [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, |
| 158 | [COBALT_PCICONF_ETH1] = ETH1_IRQ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | }; |
| 160 | |
Ralf Baechle | 19df0d1 | 2007-07-10 17:33:00 +0100 | [diff] [blame] | 161 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | { |
Ralf Baechle | c4ed38a | 2005-02-21 16:18:36 +0000 | [diff] [blame] | 163 | if (cobalt_board_id < COBALT_BRD_ID_QUBE2) |
| 164 | return irq_tab_qube1[slot]; |
| 165 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | if (cobalt_board_id == COBALT_BRD_ID_RAQ2) |
| 167 | return irq_tab_raq2[slot]; |
| 168 | |
| 169 | return irq_tab_cobalt[slot]; |
| 170 | } |
| 171 | |
| 172 | /* Do platform specific device initialization at pci_enable_device() time */ |
| 173 | int pcibios_plat_dev_init(struct pci_dev *dev) |
| 174 | { |
| 175 | return 0; |
| 176 | } |