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gerrit-public.fairphone.software / kernel / msm-4.9 / 90dc763fef4c869e60b2a7ad92e1a7dab68575ea / . / sound / oss / swarm_cs4297a.c
blob: 34b0838793a652ab4f34edb9d56406e34243ac1d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*******************************************************************************
2*
3* "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver.
4*
5* Copyright (C) 2001 Broadcom Corporation.
6* Copyright (C) 2000,2001 Cirrus Logic Corp.
7* -- adapted from drivers by Thomas Sailer,
8* -- but don't bug him; Problems should go to:
9* -- tom woller (twoller@crystal.cirrus.com) or
10* (audio@crystal.cirrus.com).
11* -- adapted from cs4281 PCI driver for cs4297a on
12* BCM1250 Synchronous Serial interface
13* (Kip Walker, Broadcom Corp.)
14* Copyright (C) 2004 Maciej W. Rozycki
15* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
16*
17* This program is free software; you can redistribute it and/or modify
18* it under the terms of the GNU General Public License as published by
19* the Free Software Foundation; either version 2 of the License, or
20* (at your option) any later version.
21*
22* This program is distributed in the hope that it will be useful,
23* but WITHOUT ANY WARRANTY; without even the implied warranty of
24* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25* GNU General Public License for more details.
26*
27* You should have received a copy of the GNU General Public License
28* along with this program; if not, write to the Free Software
29* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
30*
31* Module command line parameters:
32* none
33*
34* Supported devices:
35* /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
36* /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
37* /dev/midi simple MIDI UART interface, no ioctl
38*
39* Modification History
40* 08/20/00 trw - silence and no stopping DAC until release
41* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
42* 09/18/00 trw - added 16bit only record with conversion
43* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
44* capture/playback rates)
45* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
46* libOSSm.so)
47* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
48* 11/03/00 trw - fixed interrupt loss/stutter, added debug.
49* 11/10/00 bkz - added __devinit to cs4297a_hw_init()
50* 11/10/00 trw - fixed SMP and capture spinlock hang.
51* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
52* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
53* 12/08/00 trw - added PM support.
54* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
55* (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
56* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
57* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
58* defaultorder-100 as power of 2 for the buffer size. example:
59* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
60*
61*******************************************************************************/
62
63#include <linux/list.h>
64#include <linux/module.h>
65#include <linux/string.h>
66#include <linux/ioport.h>
67#include <linux/sched.h>
68#include <linux/delay.h>
69#include <linux/sound.h>
70#include <linux/slab.h>
Arnd Bergmann90dc7632010-07-11 12:16:36 +0200[diff] [blame^]71#include <linux/smp_lock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]72#include <linux/soundcard.h>
73#include <linux/ac97_codec.h>
74#include <linux/pci.h>
75#include <linux/bitops.h>
76#include <linux/interrupt.h>
77#include <linux/init.h>
78#include <linux/poll.h>
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]79#include <linux/mutex.h>
Ahmed S. Darwish8b5925f2007-02-12 00:52:08 -0800[diff] [blame]80#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]81
82#include <asm/byteorder.h>
83#include <asm/dma.h>
84#include <asm/io.h>
85#include <asm/uaccess.h>
86
87#include <asm/sibyte/sb1250_regs.h>
88#include <asm/sibyte/sb1250_int.h>
89#include <asm/sibyte/sb1250_dma.h>
90#include <asm/sibyte/sb1250_scd.h>
91#include <asm/sibyte/sb1250_syncser.h>
92#include <asm/sibyte/sb1250_mac.h>
93#include <asm/sibyte/sb1250.h>
94
95struct cs4297a_state;
96
97static void stop_dac(struct cs4297a_state *s);
98static void stop_adc(struct cs4297a_state *s);
99static void start_dac(struct cs4297a_state *s);
100static void start_adc(struct cs4297a_state *s);
101#undef OSS_DOCUMENTED_MIXER_SEMANTICS
102
103// ---------------------------------------------------------------------
104
105#define CS4297a_MAGIC 0xf00beef1
106
107// buffer order determines the size of the dma buffer for the driver.
108// under Linux, a smaller buffer allows more responsiveness from many of the
109// applications (e.g. games). A larger buffer allows some of the apps (esound)
110// to not underrun the dma buffer as easily. As default, use 32k (order=3)
111// rather than 64k as some of the games work more responsively.
112// log base 2( buff sz = 32k).
113
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]114//
115// Turn on/off debugging compilation by commenting out "#define CSDEBUG"
116//
117#define CSDEBUG 0
118#if CSDEBUG
119#define CSDEBUG_INTERFACE 1
120#else
121#undef CSDEBUG_INTERFACE
122#endif
123//
124// cs_debugmask areas
125//
126#define CS_INIT 0x00000001 // initialization and probe functions
127#define CS_ERROR 0x00000002 // tmp debugging bit placeholder
128#define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
129#define CS_FUNCTION 0x00000008 // enter/leave functions
130#define CS_WAVE_WRITE 0x00000010 // write information for wave
131#define CS_WAVE_READ 0x00000020 // read information for wave
132#define CS_AC97 0x00000040 // AC97 register access
133#define CS_DESCR 0x00000080 // descriptor management
134#define CS_OPEN 0x00000400 // all open functions in the driver
135#define CS_RELEASE 0x00000800 // all release functions in the driver
136#define CS_PARMS 0x00001000 // functional and operational parameters
137#define CS_IOCTL 0x00002000 // ioctl (non-mixer)
138#define CS_TMP 0x10000000 // tmp debug mask bit
139
140//
141// CSDEBUG is usual mode is set to 1, then use the
142// cs_debuglevel and cs_debugmask to turn on or off debugging.
143// Debug level of 1 has been defined to be kernel errors and info
144// that should be printed on any released driver.
145//
146#if CSDEBUG
147#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
148#else
149#define CS_DBGOUT(mask,level,x)
150#endif
151
152#if CSDEBUG
153static unsigned long cs_debuglevel = 4; // levels range from 1-9
154static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
Rusty Russell8d3b33f2006-03-25 03:07:05 -0800[diff] [blame]155module_param(cs_debuglevel, int, 0);
156module_param(cs_debugmask, int, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]157#endif
158#define CS_TRUE 1
159#define CS_FALSE 0
160
161#define CS_TYPE_ADC 0
162#define CS_TYPE_DAC 1
163
164#define SER_BASE (A_SER_BASE_1 + KSEG1)
165#define SS_CSR(t) (SER_BASE+t)
166#define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
167#define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
168
169#define FRAME_BYTES 32
170#define FRAME_SAMPLE_BYTES 4
171
172/* Should this be variable? */
173#define SAMPLE_BUF_SIZE (16*1024)
174#define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
175/* The driver can explode/shrink the frames to/from a smaller sample
176 buffer */
177#define DMA_BLOAT_FACTOR 1
178#define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
179#define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES)
180
181/* Use the maxmium count (255 == 5.1 ms between interrupts) */
182#define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1)
183
184/* Figure this out: how many TX DMAs ahead to schedule a reg access */
185#define REG_LATENCY 150
186
187#define FRAME_TX_US 20
188
189#define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
190
191static const char invalid_magic[] =
192 KERN_CRIT "cs4297a: invalid magic value\n";
193
194#define VALIDATE_STATE(s) \
195({ \
196 if (!(s) || (s)->magic != CS4297a_MAGIC) { \
197 printk(invalid_magic); \
198 return -ENXIO; \
199 } \
200})
201
202struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
203
204typedef struct serdma_descr_s {
205 u64 descr_a;
206 u64 descr_b;
207} serdma_descr_t;
208
209typedef unsigned long paddr_t;
210
211typedef struct serdma_s {
212 unsigned ringsz;
213 serdma_descr_t *descrtab;
214 serdma_descr_t *descrtab_end;
215 paddr_t descrtab_phys;
216
217 serdma_descr_t *descr_add;
218 serdma_descr_t *descr_rem;
219
220 u64 *dma_buf; // buffer for DMA contents (frames)
221 paddr_t dma_buf_phys;
222 u16 *sample_buf; // tmp buffer for sample conversions
223 u16 *sb_swptr;
224 u16 *sb_hwptr;
225 u16 *sb_end;
226
227 dma_addr_t dmaaddr;
228// unsigned buforder; // Log base 2 of 'dma_buf' size in bytes..
229 unsigned numfrag; // # of 'fragments' in the buffer.
230 unsigned fragshift; // Log base 2 of fragment size.
231 unsigned hwptr, swptr;
232 unsigned total_bytes; // # bytes process since open.
233 unsigned blocks; // last returned blocks value GETOPTR
234 unsigned wakeup; // interrupt occurred on block
235 int count;
236 unsigned underrun; // underrun flag
237 unsigned error; // over/underrun
238 wait_queue_head_t wait;
239 wait_queue_head_t reg_wait;
240 // redundant, but makes calculations easier
241 unsigned fragsize; // 2**fragshift..
242 unsigned sbufsz; // 2**buforder.
243 unsigned fragsamples;
244 // OSS stuff
245 unsigned mapped:1; // Buffer mapped in cs4297a_mmap()?
246 unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
247 unsigned endcleared:1;
248 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
249 unsigned ossfragshift;
250 int ossmaxfrags;
251 unsigned subdivision;
252} serdma_t;
253
254struct cs4297a_state {
255 // magic
256 unsigned int magic;
257
258 struct list_head list;
259
260 // soundcore stuff
261 int dev_audio;
262 int dev_mixer;
263
264 // hardware resources
265 unsigned int irq;
266
267 struct {
268 unsigned int rx_ovrrn; /* FIFO */
269 unsigned int rx_overflow; /* staging buffer */
270 unsigned int tx_underrun;
271 unsigned int rx_bad;
272 unsigned int rx_good;
273 } stats;
274
275 // mixer registers
276 struct {
277 unsigned short vol[10];
278 unsigned int recsrc;
279 unsigned int modcnt;
280 unsigned short micpreamp;
281 } mix;
282
283 // wave stuff
284 struct properties {
285 unsigned fmt;
286 unsigned fmt_original; // original requested format
287 unsigned channels;
288 unsigned rate;
289 } prop_dac, prop_adc;
290 unsigned conversion:1; // conversion from 16 to 8 bit in progress
291 unsigned ena;
292 spinlock_t lock;
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]293 struct mutex open_mutex;
294 struct mutex open_sem_adc;
295 struct mutex open_sem_dac;
Al Viroaeb5d722008-09-02 15:28:45 -0400[diff] [blame]296 fmode_t open_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]297 wait_queue_head_t open_wait;
298 wait_queue_head_t open_wait_adc;
299 wait_queue_head_t open_wait_dac;
300
301 dma_addr_t dmaaddr_sample_buf;
302 unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes..
303
304 serdma_t dma_dac, dma_adc;
305
306 volatile u16 read_value;
307 volatile u16 read_reg;
308 volatile u64 reg_request;
309};
310
311#if 1
312#define prog_codec(a,b)
313#define dealloc_dmabuf(a,b);
314#endif
315
316static int prog_dmabuf_adc(struct cs4297a_state *s)
317{
318 s->dma_adc.ready = 1;
319 return 0;
320}
321
322
323static int prog_dmabuf_dac(struct cs4297a_state *s)
324{
325 s->dma_dac.ready = 1;
326 return 0;
327}
328
329static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
330 unsigned len, unsigned char c)
331{
332 if (bptr + len > bsize) {
333 unsigned x = bsize - bptr;
334 memset(((char *) buf) + bptr, c, x);
335 bptr = 0;
336 len -= x;
337 }
338 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
339 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
340 (unsigned)c, (unsigned)((char *) buf) + bptr, len));
341 memset(((char *) buf) + bptr, c, len);
342}
343
344#if CSDEBUG
345
346// DEBUG ROUTINES
347
348#define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
349#define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
350#define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
351#define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
352
353static void cs_printioctl(unsigned int x)
354{
355 unsigned int i;
356 unsigned char vidx;
357 // Index of mixtable1[] member is Device ID
358 // and must be <= SOUND_MIXER_NRDEVICES.
359 // Value of array member is index into s->mix.vol[]
360 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
361 [SOUND_MIXER_PCM] = 1, // voice
362 [SOUND_MIXER_LINE1] = 2, // AUX
363 [SOUND_MIXER_CD] = 3, // CD
364 [SOUND_MIXER_LINE] = 4, // Line
365 [SOUND_MIXER_SYNTH] = 5, // FM
366 [SOUND_MIXER_MIC] = 6, // Mic
367 [SOUND_MIXER_SPEAKER] = 7, // Speaker
368 [SOUND_MIXER_RECLEV] = 8, // Recording level
369 [SOUND_MIXER_VOLUME] = 9 // Master Volume
370 };
371
372 switch (x) {
373 case SOUND_MIXER_CS_GETDBGMASK:
374 CS_DBGOUT(CS_IOCTL, 4,
375 printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
376 break;
377 case SOUND_MIXER_CS_GETDBGLEVEL:
378 CS_DBGOUT(CS_IOCTL, 4,
379 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
380 break;
381 case SOUND_MIXER_CS_SETDBGMASK:
382 CS_DBGOUT(CS_IOCTL, 4,
383 printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
384 break;
385 case SOUND_MIXER_CS_SETDBGLEVEL:
386 CS_DBGOUT(CS_IOCTL, 4,
387 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
388 break;
389 case OSS_GETVERSION:
390 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
391 break;
392 case SNDCTL_DSP_SYNC:
393 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
394 break;
395 case SNDCTL_DSP_SETDUPLEX:
396 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
397 break;
398 case SNDCTL_DSP_GETCAPS:
399 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
400 break;
401 case SNDCTL_DSP_RESET:
402 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
403 break;
404 case SNDCTL_DSP_SPEED:
405 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
406 break;
407 case SNDCTL_DSP_STEREO:
408 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
409 break;
410 case SNDCTL_DSP_CHANNELS:
411 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
412 break;
413 case SNDCTL_DSP_GETFMTS:
414 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
415 break;
416 case SNDCTL_DSP_SETFMT:
417 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
418 break;
419 case SNDCTL_DSP_POST:
420 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
421 break;
422 case SNDCTL_DSP_GETTRIGGER:
423 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
424 break;
425 case SNDCTL_DSP_SETTRIGGER:
426 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
427 break;
428 case SNDCTL_DSP_GETOSPACE:
429 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
430 break;
431 case SNDCTL_DSP_GETISPACE:
432 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
433 break;
434 case SNDCTL_DSP_NONBLOCK:
435 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
436 break;
437 case SNDCTL_DSP_GETODELAY:
438 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
439 break;
440 case SNDCTL_DSP_GETIPTR:
441 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
442 break;
443 case SNDCTL_DSP_GETOPTR:
444 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
445 break;
446 case SNDCTL_DSP_GETBLKSIZE:
447 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
448 break;
449 case SNDCTL_DSP_SETFRAGMENT:
450 CS_DBGOUT(CS_IOCTL, 4,
451 printk("SNDCTL_DSP_SETFRAGMENT:\n"));
452 break;
453 case SNDCTL_DSP_SUBDIVIDE:
454 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
455 break;
456 case SOUND_PCM_READ_RATE:
457 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
458 break;
459 case SOUND_PCM_READ_CHANNELS:
460 CS_DBGOUT(CS_IOCTL, 4,
461 printk("SOUND_PCM_READ_CHANNELS:\n"));
462 break;
463 case SOUND_PCM_READ_BITS:
464 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
465 break;
466 case SOUND_PCM_WRITE_FILTER:
467 CS_DBGOUT(CS_IOCTL, 4,
468 printk("SOUND_PCM_WRITE_FILTER:\n"));
469 break;
470 case SNDCTL_DSP_SETSYNCRO:
471 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
472 break;
473 case SOUND_PCM_READ_FILTER:
474 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
475 break;
476 case SOUND_MIXER_PRIVATE1:
477 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
478 break;
479 case SOUND_MIXER_PRIVATE2:
480 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
481 break;
482 case SOUND_MIXER_PRIVATE3:
483 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
484 break;
485 case SOUND_MIXER_PRIVATE4:
486 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
487 break;
488 case SOUND_MIXER_PRIVATE5:
489 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
490 break;
491 case SOUND_MIXER_INFO:
492 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
493 break;
494 case SOUND_OLD_MIXER_INFO:
495 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
496 break;
497
498 default:
499 switch (_IOC_NR(x)) {
500 case SOUND_MIXER_VOLUME:
501 CS_DBGOUT(CS_IOCTL, 4,
502 printk("SOUND_MIXER_VOLUME:\n"));
503 break;
504 case SOUND_MIXER_SPEAKER:
505 CS_DBGOUT(CS_IOCTL, 4,
506 printk("SOUND_MIXER_SPEAKER:\n"));
507 break;
508 case SOUND_MIXER_RECLEV:
509 CS_DBGOUT(CS_IOCTL, 4,
510 printk("SOUND_MIXER_RECLEV:\n"));
511 break;
512 case SOUND_MIXER_MIC:
513 CS_DBGOUT(CS_IOCTL, 4,
514 printk("SOUND_MIXER_MIC:\n"));
515 break;
516 case SOUND_MIXER_SYNTH:
517 CS_DBGOUT(CS_IOCTL, 4,
518 printk("SOUND_MIXER_SYNTH:\n"));
519 break;
520 case SOUND_MIXER_RECSRC:
521 CS_DBGOUT(CS_IOCTL, 4,
522 printk("SOUND_MIXER_RECSRC:\n"));
523 break;
524 case SOUND_MIXER_DEVMASK:
525 CS_DBGOUT(CS_IOCTL, 4,
526 printk("SOUND_MIXER_DEVMASK:\n"));
527 break;
528 case SOUND_MIXER_RECMASK:
529 CS_DBGOUT(CS_IOCTL, 4,
530 printk("SOUND_MIXER_RECMASK:\n"));
531 break;
532 case SOUND_MIXER_STEREODEVS:
533 CS_DBGOUT(CS_IOCTL, 4,
534 printk("SOUND_MIXER_STEREODEVS:\n"));
535 break;
536 case SOUND_MIXER_CAPS:
537 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
538 break;
539 default:
540 i = _IOC_NR(x);
541 if (i >= SOUND_MIXER_NRDEVICES
542 || !(vidx = mixtable1[i])) {
543 CS_DBGOUT(CS_IOCTL, 4, printk
544 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
545 x, i));
546 } else {
547 CS_DBGOUT(CS_IOCTL, 4, printk
548 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
549 x, i));
550 }
551 break;
552 }
553 }
554}
555#endif
556
557
558static int ser_init(struct cs4297a_state *s)
559{
560 int i;
561
562 CS_DBGOUT(CS_INIT, 2,
563 printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
564
565 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
566
567 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
568 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
569 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
570
571 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
572 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
573 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
574
575 /* This looks good from experimentation */
576 __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
577 M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
578 SS_CSR(R_SER_LINE_MODE));
579
580 /* This looks good from experimentation */
581 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
582 SS_TXTBL(0));
583 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
584 SS_TXTBL(1));
585 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
586 SS_TXTBL(2));
587 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
588 M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
589
590 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
591 SS_RXTBL(0));
592 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
593 SS_RXTBL(1));
594 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
595 SS_RXTBL(2));
596 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
597 M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
598
599 for (i=4; i<16; i++) {
600 /* Just in case... */
601 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
602 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
603 }
604
605 return 0;
606}
607
608static int init_serdma(serdma_t *dma)
609{
610 CS_DBGOUT(CS_INIT, 2,
611 printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
612 DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
613
614 /* Descriptors */
615 dma->ringsz = DMA_DESCR;
Robert P. J. Day3159f062007-02-14 00:33:16 -0800[diff] [blame]616 dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]617 if (!dma->descrtab) {
Robert P. J. Day3159f062007-02-14 00:33:16 -0800[diff] [blame]618 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]619 return -1;
620 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]621 dma->descrtab_end = dma->descrtab + dma->ringsz;
622 /* XXX bloddy mess, use proper DMA API here ... */
623 dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
624 dma->descr_add = dma->descr_rem = dma->descrtab;
625
626 /* Frame buffer area */
Robert P. J. Day3159f062007-02-14 00:33:16 -0800[diff] [blame]627 dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]628 if (!dma->dma_buf) {
Robert P. J. Day3159f062007-02-14 00:33:16 -0800[diff] [blame]629 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]630 kfree(dma->descrtab);
631 return -1;
632 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]633 dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
634
635 /* Samples buffer area */
636 dma->sbufsz = SAMPLE_BUF_SIZE;
637 dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
638 if (!dma->sample_buf) {
639 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
640 kfree(dma->descrtab);
641 kfree(dma->dma_buf);
642 return -1;
643 }
644 dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
645 dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
646 dma->fragsize = dma->sbufsz >> 1;
647
648 CS_DBGOUT(CS_INIT, 4,
649 printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
650 (int)dma->descrtab, (int)dma->dma_buf,
651 (int)dma->sample_buf));
652
653 return 0;
654}
655
656static int dma_init(struct cs4297a_state *s)
657{
658 int i;
659
660 CS_DBGOUT(CS_INIT, 2,
661 printk(KERN_INFO "cs4297a: Setting up DMA\n"));
662
663 if (init_serdma(&s->dma_adc) ||
664 init_serdma(&s->dma_dac))
665 return -1;
666
667 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
668 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
669 panic("DMA state corrupted?!");
670 }
671
672 /* Initialize now - the descr/buffer pairings will never
673 change... */
674 for (i=0; i<DMA_DESCR; i++) {
675 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
676 (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
677 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
678 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
679 (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
680 s->dma_adc.descrtab[i].descr_b = 0;
681 }
682
683 __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
684 V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
685 SS_CSR(R_SER_DMA_CONFIG0_RX));
686 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
687 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
688
689 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
690 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
691 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
692
693 /* Prep the receive DMA descriptor ring */
694 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
695
696 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
697
698 __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
699 SS_CSR(R_SER_INT_MASK));
700
701 /* Enable the rx/tx; let the codec warm up to the sync and
702 start sending good frames before the receive FIFO is
703 enabled */
704 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
705 udelay(1000);
706 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
707
708 /* XXXKW is this magic? (the "1" part) */
709 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
710 ;
711
712 CS_DBGOUT(CS_INIT, 4,
713 printk(KERN_INFO "cs4297a: status: %08x\n",
714 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
715
716 return 0;
717}
718
719static int serdma_reg_access(struct cs4297a_state *s, u64 data)
720{
721 serdma_t *d = &s->dma_dac;
722 u64 *data_p;
723 unsigned swptr;
Alexey Dobriyanc53421b2006-09-30 23:27:37 -0700[diff] [blame]724 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]725 serdma_descr_t *descr;
726
727 if (s->reg_request) {
728 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
729 return -1;
730 }
731
732 if (s->ena & FMODE_WRITE) {
733 /* Since a writer has the DSP open, we have to mux the
734 request in */
735 s->reg_request = data;
736 interruptible_sleep_on(&s->dma_dac.reg_wait);
737 /* XXXKW how can I deal with the starvation case where
738 the opener isn't writing? */
739 } else {
740 /* Be safe when changing ring pointers */
741 spin_lock_irqsave(&s->lock, flags);
742 if (d->hwptr != d->swptr) {
743 printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
744 d->hwptr, d->swptr);
745 spin_unlock_irqrestore(&s->lock, flags);
746 return -1;
747 }
748 swptr = d->swptr;
749 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
750 spin_unlock_irqrestore(&s->lock, flags);
751
752 descr = &d->descrtab[swptr];
753 data_p = &d->dma_buf[swptr * 4];
754 *data_p = cpu_to_be64(data);
755 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
756 CS_DBGOUT(CS_DESCR, 4,
757 printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n",
758 data_p, swptr, d->hwptr));
759 }
760
761 CS_DBGOUT(CS_FUNCTION, 6,
762 printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
763
764 return 0;
765}
766
767//****************************************************************************
768// "cs4297a_read_ac97" -- Reads an AC97 register
769//****************************************************************************
770static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
771 u32 * value)
772{
773 CS_DBGOUT(CS_AC97, 1,
774 printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
775 if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
776 return -1;
777
778 interruptible_sleep_on(&s->dma_adc.reg_wait);
779 *value = s->read_value;
780 CS_DBGOUT(CS_AC97, 2,
781 printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
782
783 return 0;
784}
785
786
787//****************************************************************************
788// "cs4297a_write_ac97()"-- writes an AC97 register
789//****************************************************************************
790static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
791 u32 value)
792{
793 CS_DBGOUT(CS_AC97, 1,
794 printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
795 return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
796}
797
798static void stop_dac(struct cs4297a_state *s)
799{
800 unsigned long flags;
801
802 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
803 spin_lock_irqsave(&s->lock, flags);
804 s->ena &= ~FMODE_WRITE;
805#if 0
806 /* XXXKW what do I really want here? My theory for now is
807 that I just flip the "ena" bit, and the interrupt handler
808 will stop processing the xmit channel */
809 __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
810 SS_CSR(R_SER_DMA_ENABLE));
811#endif
812
813 spin_unlock_irqrestore(&s->lock, flags);
814}
815
816
817static void start_dac(struct cs4297a_state *s)
818{
819 unsigned long flags;
820
821 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
822 spin_lock_irqsave(&s->lock, flags);
823 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
824 (s->dma_dac.count > 0
825 && s->dma_dac.ready))) {
826 s->ena |= FMODE_WRITE;
827 /* XXXKW what do I really want here? My theory for
828 now is that I just flip the "ena" bit, and the
829 interrupt handler will start processing the xmit
830 channel */
831
832 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
833 "cs4297a: start_dac(): start dma\n"));
834
835 }
836 spin_unlock_irqrestore(&s->lock, flags);
837 CS_DBGOUT(CS_FUNCTION, 3,
838 printk(KERN_INFO "cs4297a: start_dac()-\n"));
839}
840
841
842static void stop_adc(struct cs4297a_state *s)
843{
844 unsigned long flags;
845
846 CS_DBGOUT(CS_FUNCTION, 3,
847 printk(KERN_INFO "cs4297a: stop_adc()+\n"));
848
849 spin_lock_irqsave(&s->lock, flags);
850 s->ena &= ~FMODE_READ;
851
852 if (s->conversion == 1) {
853 s->conversion = 0;
854 s->prop_adc.fmt = s->prop_adc.fmt_original;
855 }
856 /* Nothing to do really, I need to keep the DMA going
857 XXXKW when do I get here, and is there more I should do? */
858 spin_unlock_irqrestore(&s->lock, flags);
859 CS_DBGOUT(CS_FUNCTION, 3,
860 printk(KERN_INFO "cs4297a: stop_adc()-\n"));
861}
862
863
864static void start_adc(struct cs4297a_state *s)
865{
866 unsigned long flags;
867
868 CS_DBGOUT(CS_FUNCTION, 2,
869 printk(KERN_INFO "cs4297a: start_adc()+\n"));
870
871 if (!(s->ena & FMODE_READ) &&
872 (s->dma_adc.mapped || s->dma_adc.count <=
873 (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
874 && s->dma_adc.ready) {
875 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
876 //
877 // now only use 16 bit capture, due to truncation issue
878 // in the chip, noticable distortion occurs.
879 // allocate buffer and then convert from 16 bit to
880 // 8 bit for the user buffer.
881 //
882 s->prop_adc.fmt_original = s->prop_adc.fmt;
883 if (s->prop_adc.fmt & AFMT_S8) {
884 s->prop_adc.fmt &= ~AFMT_S8;
885 s->prop_adc.fmt |= AFMT_S16_LE;
886 }
887 if (s->prop_adc.fmt & AFMT_U8) {
888 s->prop_adc.fmt &= ~AFMT_U8;
889 s->prop_adc.fmt |= AFMT_U16_LE;
890 }
891 //
892 // prog_dmabuf_adc performs a stop_adc() but that is
893 // ok since we really haven't started the DMA yet.
894 //
895 prog_codec(s, CS_TYPE_ADC);
896
897 prog_dmabuf_adc(s);
898 s->conversion = 1;
899 }
900 spin_lock_irqsave(&s->lock, flags);
901 s->ena |= FMODE_READ;
902 /* Nothing to do really, I am probably already
903 DMAing... XXXKW when do I get here, and is there
904 more I should do? */
905 spin_unlock_irqrestore(&s->lock, flags);
906
907 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
908 "cs4297a: start_adc(): start adc\n"));
909 }
910 CS_DBGOUT(CS_FUNCTION, 2,
911 printk(KERN_INFO "cs4297a: start_adc()-\n"));
912
913}
914
915
916// call with spinlock held!
917static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
918{
919 int good_diff, diff, diff2;
920 u64 *data_p, data;
921 u32 *s_ptr;
922 unsigned hwptr;
923 u32 status;
924 serdma_t *d;
925 serdma_descr_t *descr;
926
927 // update ADC pointer
928 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
929
930 if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
931 d = &s->dma_adc;
932 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
933 d->descrtab_phys) / sizeof(serdma_descr_t));
934
935 if (s->ena & FMODE_READ) {
936 CS_DBGOUT(CS_FUNCTION, 2,
937 printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
938 d->swptr, d->hwptr, hwptr, intflag));
939 /* Number of DMA buffers available for software: */
940 diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
941 d->hwptr = hwptr;
942 good_diff = 0;
943 s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
944 descr = &d->descrtab[d->swptr];
945 while (diff2--) {
946 u64 data = be64_to_cpu(*(u64 *)s_ptr);
947 u64 descr_a;
948 u16 left, right;
949 descr_a = descr->descr_a;
950 descr->descr_a &= ~M_DMA_SERRX_SOP;
951 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
952 printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
953 }
954 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
955 (!(descr_a & M_DMA_SERRX_SOP)) ||
956 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
957 s->stats.rx_bad++;
958 printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
959 continue;
960 }
961 s->stats.rx_good++;
962 if ((data >> 61) == 7) {
963 s->read_value = (data >> 12) & 0xffff;
964 s->read_reg = (data >> 40) & 0x7f;
965 wake_up(&d->reg_wait);
966 }
967 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
968 s->stats.rx_overflow++;
969 printk(KERN_DEBUG "cs4297a: RX overflow\n");
970 continue;
971 }
972 good_diff++;
973 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
974 ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
975 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
976 *d->sb_hwptr++ = cpu_to_be16(left);
977 *d->sb_hwptr++ = cpu_to_be16(right);
978 if (d->sb_hwptr == d->sb_end)
979 d->sb_hwptr = d->sample_buf;
980 descr++;
981 if (descr == d->descrtab_end) {
982 descr = d->descrtab;
983 s_ptr = (u32 *)s->dma_adc.dma_buf;
984 } else {
985 s_ptr += 8;
986 }
987 }
988 d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
989 d->count += good_diff * FRAME_SAMPLE_BYTES;
990 if (d->count > d->sbufsz) {
991 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
992 }
993 d->swptr = (d->swptr + diff) % d->ringsz;
994 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
995 if (d->mapped) {
996 if (d->count >= (signed) d->fragsize)
997 wake_up(&d->wait);
998 } else {
999 if (d->count > 0) {
1000 CS_DBGOUT(CS_WAVE_READ, 4,
1001 printk(KERN_INFO
1002 "cs4297a: update count -> %d\n", d->count));
1003 wake_up(&d->wait);
1004 }
1005 }
1006 } else {
1007 /* Receive is going even if no one is
1008 listening (for register accesses and to
1009 avoid FIFO overrun) */
1010 diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1011 if (!diff) {
1012 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1013 }
1014
1015 descr = &d->descrtab[d->swptr];
1016 data_p = &d->dma_buf[d->swptr*4];
1017
1018 /* Force this to happen at least once; I got
1019 here because of an interrupt, so there must
1020 be a buffer to process. */
1021 do {
1022 data = be64_to_cpu(*data_p);
1023 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
1024 printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1025 (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1026 (long)CPHYSADDR((long)data_p));
1027 }
1028 if (!(data & (1LL << 63)) ||
1029 !(descr->descr_a & M_DMA_SERRX_SOP) ||
1030 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1031 s->stats.rx_bad++;
1032 printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1033 } else {
1034 s->stats.rx_good++;
1035 if ((data >> 61) == 7) {
1036 s->read_value = (data >> 12) & 0xffff;
1037 s->read_reg = (data >> 40) & 0x7f;
1038 wake_up(&d->reg_wait);
1039 }
1040 }
1041 descr->descr_a &= ~M_DMA_SERRX_SOP;
1042 descr++;
1043 d->swptr++;
1044 data_p += 4;
1045 if (descr == d->descrtab_end) {
1046 descr = d->descrtab;
1047 d->swptr = 0;
1048 data_p = d->dma_buf;
1049 }
1050 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1051 } while (--diff);
1052 d->hwptr = hwptr;
1053
1054 CS_DBGOUT(CS_DESCR, 6,
1055 printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1056 }
1057
1058 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1059 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1060 (unsigned)s, d->hwptr,
1061 d->total_bytes, d->count));
1062 }
1063
1064 /* XXXKW worry about s->reg_request -- there is a starvation
1065 case if s->ena has FMODE_WRITE on, but the client isn't
1066 doing writes */
1067
1068 // update DAC pointer
1069 //
1070 // check for end of buffer, means that we are going to wait for another interrupt
1071 // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1072 //
1073 if (s->ena & FMODE_WRITE) {
1074 serdma_t *d = &s->dma_dac;
1075 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1076 d->descrtab_phys) / sizeof(serdma_descr_t));
1077 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1078 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1079 "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1080 d->hwptr, hwptr, d->swptr, diff, d->count));
1081 d->hwptr = hwptr;
1082 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1083 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1084 if (d->mapped) {
1085 d->count += diff * FRAME_SAMPLE_BYTES;
1086 if (d->count >= d->fragsize) {
1087 d->wakeup = 1;
1088 wake_up(&d->wait);
1089 if (d->count > d->sbufsz)
1090 d->count &= d->sbufsz - 1;
1091 }
1092 } else {
1093 d->count -= diff * FRAME_SAMPLE_BYTES;
1094 if (d->count <= 0) {
1095 //
1096 // fill with silence, and do not shut down the DAC.
1097 // Continue to play silence until the _release.
1098 //
1099 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1100 "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1101 (unsigned)(s->prop_dac.fmt &
1102 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1103 (unsigned)d->dma_buf,
1104 d->ringsz));
1105 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1106 if (d->count < 0) {
1107 d->underrun = 1;
1108 s->stats.tx_underrun++;
1109 d->count = 0;
1110 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1111 "cs4297a: cs4297a_update_ptr(): underrun\n"));
1112 }
1113 } else if (d->count <=
1114 (signed) d->fragsize
1115 && !d->endcleared) {
1116 /* XXXKW what is this for? */
1117 clear_advance(d->dma_buf,
1118 d->sbufsz,
1119 d->swptr,
1120 d->fragsize,
1121 0);
1122 d->endcleared = 1;
1123 }
1124 if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1125 {
1126 CS_DBGOUT(CS_WAVE_WRITE, 4,
1127 printk(KERN_INFO
1128 "cs4297a: update count -> %d\n", d->count));
1129 wake_up(&d->wait);
1130 }
1131 }
1132 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1133 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1134 (unsigned) s, d->hwptr,
1135 d->total_bytes, d->count));
1136 }
1137}
1138
1139static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1140 unsigned long arg)
1141{
1142 // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1143 // Value of array member is recording source Device ID Mask.
1144 static const unsigned int mixer_src[8] = {
1145 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1146 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1147 };
1148
1149 // Index of mixtable1[] member is Device ID
1150 // and must be <= SOUND_MIXER_NRDEVICES.
1151 // Value of array member is index into s->mix.vol[]
1152 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1153 [SOUND_MIXER_PCM] = 1, // voice
1154 [SOUND_MIXER_LINE1] = 2, // AUX
1155 [SOUND_MIXER_CD] = 3, // CD
1156 [SOUND_MIXER_LINE] = 4, // Line
1157 [SOUND_MIXER_SYNTH] = 5, // FM
1158 [SOUND_MIXER_MIC] = 6, // Mic
1159 [SOUND_MIXER_SPEAKER] = 7, // Speaker
1160 [SOUND_MIXER_RECLEV] = 8, // Recording level
1161 [SOUND_MIXER_VOLUME] = 9 // Master Volume
1162 };
1163
1164 static const unsigned mixreg[] = {
1165 AC97_PCMOUT_VOL,
1166 AC97_AUX_VOL,
1167 AC97_CD_VOL,
1168 AC97_LINEIN_VOL
1169 };
1170 unsigned char l, r, rl, rr, vidx;
1171 unsigned char attentbl[11] =
1172 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1173 unsigned temp1;
1174 int i, val;
1175
1176 VALIDATE_STATE(s);
1177 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1178 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1179 (unsigned) s, cmd));
1180#if CSDEBUG
1181 cs_printioctl(cmd);
1182#endif
1183#if CSDEBUG_INTERFACE
1184
1185 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1186 (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1187 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1188 (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1189 {
1190 switch (cmd) {
1191
1192 case SOUND_MIXER_CS_GETDBGMASK:
1193 return put_user(cs_debugmask,
1194 (unsigned long *) arg);
1195
1196 case SOUND_MIXER_CS_GETDBGLEVEL:
1197 return put_user(cs_debuglevel,
1198 (unsigned long *) arg);
1199
1200 case SOUND_MIXER_CS_SETDBGMASK:
1201 if (get_user(val, (unsigned long *) arg))
1202 return -EFAULT;
1203 cs_debugmask = val;
1204 return 0;
1205
1206 case SOUND_MIXER_CS_SETDBGLEVEL:
1207 if (get_user(val, (unsigned long *) arg))
1208 return -EFAULT;
1209 cs_debuglevel = val;
1210 return 0;
1211 default:
1212 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1213 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1214 return 0;
1215 }
1216 }
1217#endif
1218
1219 if (cmd == SOUND_MIXER_PRIVATE1) {
1220 return -EINVAL;
1221 }
1222 if (cmd == SOUND_MIXER_PRIVATE2) {
1223 // enable/disable/query spatializer
1224 if (get_user(val, (int *) arg))
1225 return -EFAULT;
1226 if (val != -1) {
1227 temp1 = (val & 0x3f) >> 2;
1228 cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1229 cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1230 &temp1);
1231 cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1232 temp1 | 0x2000);
1233 }
1234 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1235 return put_user((temp1 << 2) | 3, (int *) arg);
1236 }
1237 if (cmd == SOUND_MIXER_INFO) {
1238 mixer_info info;
1239 memset(&info, 0, sizeof(info));
1240 strlcpy(info.id, "CS4297a", sizeof(info.id));
1241 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1242 info.modify_counter = s->mix.modcnt;
1243 if (copy_to_user((void *) arg, &info, sizeof(info)))
1244 return -EFAULT;
1245 return 0;
1246 }
1247 if (cmd == SOUND_OLD_MIXER_INFO) {
1248 _old_mixer_info info;
1249 memset(&info, 0, sizeof(info));
1250 strlcpy(info.id, "CS4297a", sizeof(info.id));
1251 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1252 if (copy_to_user((void *) arg, &info, sizeof(info)))
1253 return -EFAULT;
1254 return 0;
1255 }
1256 if (cmd == OSS_GETVERSION)
1257 return put_user(SOUND_VERSION, (int *) arg);
1258
1259 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1260 return -EINVAL;
1261
1262 // If ioctl has only the SIOC_READ bit(bit 31)
1263 // on, process the only-read commands.
1264 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1265 switch (_IOC_NR(cmd)) {
1266 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1267 cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1268 &temp1);
1269 return put_user(mixer_src[temp1 & 7], (int *) arg);
1270
1271 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
1272 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1273 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1274 (int *) arg);
1275
1276 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
1277 return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1278 (int *) arg);
1279
1280 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
1281 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1282 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1283 (int *) arg);
1284
1285 case SOUND_MIXER_CAPS:
1286 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1287
1288 default:
1289 i = _IOC_NR(cmd);
1290 if (i >= SOUND_MIXER_NRDEVICES
1291 || !(vidx = mixtable1[i]))
1292 return -EINVAL;
1293 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1294 }
1295 }
1296 // If ioctl doesn't have both the SIOC_READ and
1297 // the SIOC_WRITE bit set, return invalid.
1298 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1299 return -EINVAL;
1300
1301 // Increment the count of volume writes.
1302 s->mix.modcnt++;
1303
1304 // Isolate the command; it must be a write.
1305 switch (_IOC_NR(cmd)) {
1306
1307 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1308 if (get_user(val, (int *) arg))
1309 return -EFAULT;
1310 i = hweight32(val); // i = # bits on in val.
1311 if (i != 1) // One & only 1 bit must be on.
1312 return 0;
1313 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1314 if (val == mixer_src[i]) {
1315 temp1 = (i << 8) | i;
1316 cs4297a_write_ac97(s,
1317 AC97_RECORD_SELECT,
1318 temp1);
1319 return 0;
1320 }
1321 }
1322 return 0;
1323
1324 case SOUND_MIXER_VOLUME:
1325 if (get_user(val, (int *) arg))
1326 return -EFAULT;
1327 l = val & 0xff;
1328 if (l > 100)
1329 l = 100; // Max soundcard.h vol is 100.
1330 if (l < 6) {
1331 rl = 63;
1332 l = 0;
1333 } else
1334 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
1335
1336 r = (val >> 8) & 0xff;
1337 if (r > 100)
1338 r = 100; // Max right volume is 100, too
1339 if (r < 6) {
1340 rr = 63;
1341 r = 0;
1342 } else
1343 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
1344
1345 if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
1346 temp1 = 0x8000; // turn on the mute bit.
1347 else
1348 temp1 = 0;
1349
1350 temp1 |= (rl << 8) | rr;
1351
1352 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1353 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1354
1355#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1356 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1357#else
1358 s->mix.vol[8] = val;
1359#endif
1360 return put_user(s->mix.vol[8], (int *) arg);
1361
1362 case SOUND_MIXER_SPEAKER:
1363 if (get_user(val, (int *) arg))
1364 return -EFAULT;
1365 l = val & 0xff;
1366 if (l > 100)
1367 l = 100;
1368 if (l < 3) {
1369 rl = 0;
1370 l = 0;
1371 } else {
1372 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
1373 l = (rl * 13 + 5) / 2;
1374 }
1375
1376 if (rl < 3) {
1377 temp1 = 0x8000;
1378 rl = 0;
1379 } else
1380 temp1 = 0;
1381 rl = 15 - rl; // Convert volume to attenuation.
1382 temp1 |= rl << 1;
1383 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1384
1385#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1386 s->mix.vol[6] = l << 8;
1387#else
1388 s->mix.vol[6] = val;
1389#endif
1390 return put_user(s->mix.vol[6], (int *) arg);
1391
1392 case SOUND_MIXER_RECLEV:
1393 if (get_user(val, (int *) arg))
1394 return -EFAULT;
1395 l = val & 0xff;
1396 if (l > 100)
1397 l = 100;
1398 r = (val >> 8) & 0xff;
1399 if (r > 100)
1400 r = 100;
1401 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
1402 rr = (r * 2 - 5) / 13;
1403 if (rl < 3 && rr < 3)
1404 temp1 = 0x8000;
1405 else
1406 temp1 = 0;
1407
1408 temp1 = temp1 | (rl << 8) | rr;
1409 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1410
1411#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1412 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1413#else
1414 s->mix.vol[7] = val;
1415#endif
1416 return put_user(s->mix.vol[7], (int *) arg);
1417
1418 case SOUND_MIXER_MIC:
1419 if (get_user(val, (int *) arg))
1420 return -EFAULT;
1421 l = val & 0xff;
1422 if (l > 100)
1423 l = 100;
1424 if (l < 1) {
1425 l = 0;
1426 rl = 0;
1427 } else {
1428 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
1429 l = (rl * 16 + 4) / 5;
1430 }
1431 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1432 temp1 &= 0x40; // Isolate 20db gain bit.
1433 if (rl < 3) {
1434 temp1 |= 0x8000;
1435 rl = 0;
1436 }
1437 rl = 31 - rl; // Convert volume to attenuation.
1438 temp1 |= rl;
1439 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1440
1441#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1442 s->mix.vol[5] = val << 8;
1443#else
1444 s->mix.vol[5] = val;
1445#endif
1446 return put_user(s->mix.vol[5], (int *) arg);
1447
1448
1449 case SOUND_MIXER_SYNTH:
1450 if (get_user(val, (int *) arg))
1451 return -EFAULT;
1452 l = val & 0xff;
1453 if (l > 100)
1454 l = 100;
1455 if (get_user(val, (int *) arg))
1456 return -EFAULT;
1457 r = (val >> 8) & 0xff;
1458 if (r > 100)
1459 r = 100;
1460 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
1461 rr = (r * 2 - 11) / 3;
1462 if (rl < 3) // If l is low, turn on
1463 temp1 = 0x0080; // the mute bit.
1464 else
1465 temp1 = 0;
1466
1467 rl = 63 - rl; // Convert vol to attenuation.
1468// writel(temp1 | rl, s->pBA0 + FMLVC);
1469 if (rr < 3) // If rr is low, turn on
1470 temp1 = 0x0080; // the mute bit.
1471 else
1472 temp1 = 0;
1473 rr = 63 - rr; // Convert vol to attenuation.
1474// writel(temp1 | rr, s->pBA0 + FMRVC);
1475
1476#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1477 s->mix.vol[4] = (r << 8) | l;
1478#else
1479 s->mix.vol[4] = val;
1480#endif
1481 return put_user(s->mix.vol[4], (int *) arg);
1482
1483
1484 default:
1485 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1486 "cs4297a: mixer_ioctl(): default\n"));
1487
1488 i = _IOC_NR(cmd);
1489 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1490 return -EINVAL;
1491 if (get_user(val, (int *) arg))
1492 return -EFAULT;
1493 l = val & 0xff;
1494 if (l > 100)
1495 l = 100;
1496 if (l < 1) {
1497 l = 0;
1498 rl = 31;
1499 } else
1500 rl = (attentbl[(l * 10) / 100]) >> 1;
1501
1502 r = (val >> 8) & 0xff;
1503 if (r > 100)
1504 r = 100;
1505 if (r < 1) {
1506 r = 0;
1507 rr = 31;
1508 } else
1509 rr = (attentbl[(r * 10) / 100]) >> 1;
1510 if ((rl > 30) && (rr > 30))
1511 temp1 = 0x8000;
1512 else
1513 temp1 = 0;
1514 temp1 = temp1 | (rl << 8) | rr;
1515 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1516
1517#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1518 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1519#else
1520 s->mix.vol[vidx - 1] = val;
1521#endif
1522 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1523 }
1524}
1525
1526
1527// ---------------------------------------------------------------------
1528
1529static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1530{
1531 int minor = iminor(inode);
1532 struct cs4297a_state *s=NULL;
1533 struct list_head *entry;
1534
1535 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1536 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1537
Arnd Bergmann90dc7632010-07-11 12:16:36 +0200[diff] [blame^]1538 lock_kernel();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1539 list_for_each(entry, &cs4297a_devs)
1540 {
1541 s = list_entry(entry, struct cs4297a_state, list);
1542 if(s->dev_mixer == minor)
1543 break;
1544 }
1545 if (!s)
1546 {
1547 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1548 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
Arnd Bergmann90dc7632010-07-11 12:16:36 +0200[diff] [blame^]1549
1550 unlock_kernel();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1551 return -ENODEV;
1552 }
1553 VALIDATE_STATE(s);
1554 file->private_data = s;
1555
1556 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1557 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
Arnd Bergmann90dc7632010-07-11 12:16:36 +0200[diff] [blame^]1558 unlock_kernel();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1559
1560 return nonseekable_open(inode, file);
1561}
1562
1563
1564static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1565{
1566 struct cs4297a_state *s =
1567 (struct cs4297a_state *) file->private_data;
1568
1569 VALIDATE_STATE(s);
1570 return 0;
1571}
1572
1573
1574static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1575 unsigned int cmd, unsigned long arg)
1576{
1577 return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1578 arg);
1579}
1580
1581
1582// ******************************************************************************************
1583// Mixer file operations struct.
1584// ******************************************************************************************
Jan Engelhardtc8cece82008-02-08 04:21:20 -0800[diff] [blame]1585static const struct file_operations cs4297a_mixer_fops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1586 .owner = THIS_MODULE,
1587 .llseek = no_llseek,
1588 .ioctl = cs4297a_ioctl_mixdev,
1589 .open = cs4297a_open_mixdev,
1590 .release = cs4297a_release_mixdev,
1591};
1592
1593// ---------------------------------------------------------------------
1594
1595
1596static int drain_adc(struct cs4297a_state *s, int nonblock)
1597{
1598 /* This routine serves no purpose currently - any samples
1599 sitting in the receive queue will just be processed by the
1600 background consumer. This would be different if DMA
1601 actually stopped when there were no clients. */
1602 return 0;
1603}
1604
1605static int drain_dac(struct cs4297a_state *s, int nonblock)
1606{
1607 DECLARE_WAITQUEUE(wait, current);
1608 unsigned long flags;
1609 unsigned hwptr;
1610 unsigned tmo;
1611 int count;
1612
1613 if (s->dma_dac.mapped)
1614 return 0;
1615 if (nonblock)
1616 return -EBUSY;
1617 add_wait_queue(&s->dma_dac.wait, &wait);
1618 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1619 (s->dma_dac.count > 0)) {
1620 if (!signal_pending(current)) {
1621 set_current_state(TASK_INTERRUPTIBLE);
1622 /* XXXKW is this calculation working? */
1623 tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1624 schedule_timeout(tmo + 1);
1625 } else {
1626 /* XXXKW do I care if there is a signal pending? */
1627 }
1628 }
1629 spin_lock_irqsave(&s->lock, flags);
1630 /* Reset the bookkeeping */
1631 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1632 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1633 s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1634 spin_unlock_irqrestore(&s->lock, flags);
1635 remove_wait_queue(&s->dma_dac.wait, &wait);
1636 current->state = TASK_RUNNING;
1637 return 0;
1638}
1639
1640
1641// ---------------------------------------------------------------------
1642
1643static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1644 loff_t * ppos)
1645{
1646 struct cs4297a_state *s =
1647 (struct cs4297a_state *) file->private_data;
1648 ssize_t ret;
1649 unsigned long flags;
1650 int cnt, count_fr, cnt_by;
1651 unsigned copied = 0;
1652
1653 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1654 printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1655
1656 VALIDATE_STATE(s);
1657 if (s->dma_adc.mapped)
1658 return -ENXIO;
1659 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1660 return ret;
1661 if (!access_ok(VERIFY_WRITE, buffer, count))
1662 return -EFAULT;
1663 ret = 0;
1664//
1665// "count" is the amount of bytes to read (from app), is decremented each loop
1666// by the amount of bytes that have been returned to the user buffer.
1667// "cnt" is the running total of each read from the buffer (changes each loop)
1668// "buffer" points to the app's buffer
1669// "ret" keeps a running total of the amount of bytes that have been copied
1670// to the user buffer.
1671// "copied" is the total bytes copied into the user buffer for each loop.
1672//
1673 while (count > 0) {
1674 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1675 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1676 count, s->dma_adc.count,
1677 s->dma_adc.swptr, s->dma_adc.hwptr));
1678 spin_lock_irqsave(&s->lock, flags);
1679
1680 /* cnt will be the number of available samples (16-bit
1681 stereo); it starts out as the maxmimum consequetive
1682 samples */
1683 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1684 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1685
1686 // dma_adc.count is the current total bytes that have not been read.
1687 // if the amount of unread bytes from the current sw pointer to the
1688 // end of the buffer is greater than the current total bytes that
1689 // have not been read, then set the "cnt" (unread bytes) to the
1690 // amount of unread bytes.
1691
1692 if (count_fr < cnt)
1693 cnt = count_fr;
1694 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1695 spin_unlock_irqrestore(&s->lock, flags);
1696 //
1697 // if we are converting from 8/16 then we need to copy
1698 // twice the number of 16 bit bytes then 8 bit bytes.
1699 //
1700 if (s->conversion) {
1701 if (cnt_by > (count * 2)) {
1702 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1703 cnt_by = count * 2;
1704 }
1705 } else {
1706 if (cnt_by > count) {
1707 cnt = count / FRAME_SAMPLE_BYTES;
1708 cnt_by = count;
1709 }
1710 }
1711 //
1712 // "cnt" NOW is the smaller of the amount that will be read,
1713 // and the amount that is requested in this read (or partial).
1714 // if there are no bytes in the buffer to read, then start the
1715 // ADC and wait for the interrupt handler to wake us up.
1716 //
1717 if (cnt <= 0) {
1718
1719 // start up the dma engine and then continue back to the top of
1720 // the loop when wake up occurs.
1721 start_adc(s);
1722 if (file->f_flags & O_NONBLOCK)
1723 return ret ? ret : -EAGAIN;
1724 interruptible_sleep_on(&s->dma_adc.wait);
1725 if (signal_pending(current))
1726 return ret ? ret : -ERESTARTSYS;
1727 continue;
1728 }
1729 // there are bytes in the buffer to read.
1730 // copy from the hw buffer over to the user buffer.
1731 // user buffer is designated by "buffer"
1732 // virtual address to copy from is dma_buf+swptr
1733 // the "cnt" is the number of bytes to read.
1734
1735 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1736 "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1737 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1738 " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1739 s->dma_adc.sbufsz, s->dma_adc.count,
1740 (unsigned) buffer, ret));
1741
1742 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1743 return ret ? ret : -EFAULT;
1744 copied = cnt_by;
1745
1746 /* Return the descriptors */
1747 spin_lock_irqsave(&s->lock, flags);
1748 CS_DBGOUT(CS_FUNCTION, 2,
1749 printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1750 s->dma_adc.count -= cnt_by;
1751 s->dma_adc.sb_swptr += cnt * 2;
1752 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1753 s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1754 spin_unlock_irqrestore(&s->lock, flags);
1755 count -= copied;
1756 buffer += copied;
1757 ret += copied;
1758 start_adc(s);
1759 }
1760 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1761 printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1762 return ret;
1763}
1764
1765
1766static ssize_t cs4297a_write(struct file *file, const char *buffer,
1767 size_t count, loff_t * ppos)
1768{
1769 struct cs4297a_state *s =
1770 (struct cs4297a_state *) file->private_data;
1771 ssize_t ret;
1772 unsigned long flags;
1773 unsigned swptr, hwptr;
1774 int cnt;
1775
1776 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1777 printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1778 count));
1779 VALIDATE_STATE(s);
1780
1781 if (s->dma_dac.mapped)
1782 return -ENXIO;
1783 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1784 return ret;
1785 if (!access_ok(VERIFY_READ, buffer, count))
1786 return -EFAULT;
1787 ret = 0;
1788 while (count > 0) {
1789 serdma_t *d = &s->dma_dac;
1790 int copy_cnt;
1791 u32 *s_tmpl;
1792 u32 *t_tmpl;
1793 u32 left, right;
1794 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1795
1796 /* XXXXXX this is broken for BLOAT_FACTOR */
1797 spin_lock_irqsave(&s->lock, flags);
1798 if (d->count < 0) {
1799 d->count = 0;
1800 d->swptr = d->hwptr;
1801 }
1802 if (d->underrun) {
1803 d->underrun = 0;
1804 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1805 d->descrtab_phys) / sizeof(serdma_descr_t));
1806 d->swptr = d->hwptr = hwptr;
1807 }
1808 swptr = d->swptr;
1809 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1810 /* Will this write fill up the buffer? */
1811 if (d->count + cnt > d->sbufsz)
1812 cnt = d->sbufsz - d->count;
1813 spin_unlock_irqrestore(&s->lock, flags);
1814 if (cnt > count)
1815 cnt = count;
1816 if (cnt <= 0) {
1817 start_dac(s);
1818 if (file->f_flags & O_NONBLOCK)
1819 return ret ? ret : -EAGAIN;
1820 interruptible_sleep_on(&d->wait);
1821 if (signal_pending(current))
1822 return ret ? ret : -ERESTARTSYS;
1823 continue;
1824 }
1825 if (copy_from_user(d->sample_buf, buffer, cnt))
1826 return ret ? ret : -EFAULT;
1827
1828 copy_cnt = cnt;
1829 s_tmpl = (u32 *)d->sample_buf;
1830 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1831
1832 /* XXXKW assuming 16-bit stereo! */
1833 do {
1834 u32 tmp;
1835
1836 t_tmpl[0] = cpu_to_be32(0x98000000);
1837
1838 tmp = be32_to_cpu(s_tmpl[0]);
1839 left = tmp & 0xffff;
1840 right = tmp >> 16;
1841 if (swap) {
1842 left = swab16(left);
1843 right = swab16(right);
1844 }
1845 t_tmpl[1] = cpu_to_be32(left >> 8);
1846 t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1847 (right << 4));
1848
1849 s_tmpl++;
1850 t_tmpl += 8;
1851 copy_cnt -= 4;
1852 } while (copy_cnt);
1853
1854 /* Mux in any pending read/write accesses */
1855 if (s->reg_request) {
1856 *(u64 *)(d->dma_buf + (swptr * 4)) |=
1857 cpu_to_be64(s->reg_request);
1858 s->reg_request = 0;
1859 wake_up(&s->dma_dac.reg_wait);
1860 }
1861
1862 CS_DBGOUT(CS_WAVE_WRITE, 4,
1863 printk(KERN_INFO
1864 "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1865
1866 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1867 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1868 spin_lock_irqsave(&s->lock, flags);
1869 d->swptr = swptr;
1870 d->count += cnt;
1871 d->endcleared = 0;
1872 spin_unlock_irqrestore(&s->lock, flags);
1873 count -= cnt;
1874 buffer += cnt;
1875 ret += cnt;
1876 start_dac(s);
1877 }
1878 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1879 printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1880 return ret;
1881}
1882
1883
1884static unsigned int cs4297a_poll(struct file *file,
1885 struct poll_table_struct *wait)
1886{
1887 struct cs4297a_state *s =
1888 (struct cs4297a_state *) file->private_data;
1889 unsigned long flags;
1890 unsigned int mask = 0;
1891
1892 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1893 printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1894 VALIDATE_STATE(s);
1895 if (file->f_mode & FMODE_WRITE) {
1896 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1897 printk(KERN_INFO
1898 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1899 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1900 return 0;
1901 poll_wait(file, &s->dma_dac.wait, wait);
1902 }
1903 if (file->f_mode & FMODE_READ) {
1904 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1905 printk(KERN_INFO
1906 "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1907 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1908 return 0;
1909 poll_wait(file, &s->dma_adc.wait, wait);
1910 }
1911 spin_lock_irqsave(&s->lock, flags);
1912 cs4297a_update_ptr(s,CS_FALSE);
1913 if (file->f_mode & FMODE_WRITE) {
1914 if (s->dma_dac.mapped) {
1915 if (s->dma_dac.count >=
1916 (signed) s->dma_dac.fragsize) {
1917 if (s->dma_dac.wakeup)
1918 mask |= POLLOUT | POLLWRNORM;
1919 else
1920 mask = 0;
1921 s->dma_dac.wakeup = 0;
1922 }
1923 } else {
1924 if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1925 mask |= POLLOUT | POLLWRNORM;
1926 }
1927 } else if (file->f_mode & FMODE_READ) {
1928 if (s->dma_adc.mapped) {
1929 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1930 mask |= POLLIN | POLLRDNORM;
1931 } else {
1932 if (s->dma_adc.count > 0)
1933 mask |= POLLIN | POLLRDNORM;
1934 }
1935 }
1936 spin_unlock_irqrestore(&s->lock, flags);
1937 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1938 printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1939 mask));
1940 return mask;
1941}
1942
1943
1944static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1945{
1946 /* XXXKW currently no mmap support */
1947 return -EINVAL;
1948 return 0;
1949}
1950
1951
1952static int cs4297a_ioctl(struct inode *inode, struct file *file,
1953 unsigned int cmd, unsigned long arg)
1954{
1955 struct cs4297a_state *s =
1956 (struct cs4297a_state *) file->private_data;
1957 unsigned long flags;
1958 audio_buf_info abinfo;
1959 count_info cinfo;
1960 int val, mapped, ret;
1961
1962 CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1963 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1964 (unsigned) file, cmd));
1965#if CSDEBUG
1966 cs_printioctl(cmd);
1967#endif
1968 VALIDATE_STATE(s);
1969 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1970 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1971 switch (cmd) {
1972 case OSS_GETVERSION:
1973 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1974 "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1975 SOUND_VERSION));
1976 return put_user(SOUND_VERSION, (int *) arg);
1977
1978 case SNDCTL_DSP_SYNC:
1979 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1980 "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1981 if (file->f_mode & FMODE_WRITE)
1982 return drain_dac(s,
1983 0 /*file->f_flags & O_NONBLOCK */
1984 );
1985 return 0;
1986
1987 case SNDCTL_DSP_SETDUPLEX:
1988 return 0;
1989
1990 case SNDCTL_DSP_GETCAPS:
1991 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1992 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
1993 (int *) arg);
1994
1995 case SNDCTL_DSP_RESET:
1996 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1997 "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
1998 if (file->f_mode & FMODE_WRITE) {
1999 stop_dac(s);
2000 synchronize_irq(s->irq);
2001 s->dma_dac.count = s->dma_dac.total_bytes =
2002 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2003 s->dma_dac.swptr = s->dma_dac.hwptr =
2004 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2005 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2006 }
2007 if (file->f_mode & FMODE_READ) {
2008 stop_adc(s);
2009 synchronize_irq(s->irq);
2010 s->dma_adc.count = s->dma_adc.total_bytes =
2011 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2012 s->dma_adc.swptr = s->dma_adc.hwptr =
2013 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2014 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2015 }
2016 return 0;
2017
2018 case SNDCTL_DSP_SPEED:
2019 if (get_user(val, (int *) arg))
2020 return -EFAULT;
2021 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2022 "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2023 val = 48000;
2024 return put_user(val, (int *) arg);
2025
2026 case SNDCTL_DSP_STEREO:
2027 if (get_user(val, (int *) arg))
2028 return -EFAULT;
2029 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2030 "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2031 if (file->f_mode & FMODE_READ) {
2032 stop_adc(s);
2033 s->dma_adc.ready = 0;
2034 s->prop_adc.channels = val ? 2 : 1;
2035 }
2036 if (file->f_mode & FMODE_WRITE) {
2037 stop_dac(s);
2038 s->dma_dac.ready = 0;
2039 s->prop_dac.channels = val ? 2 : 1;
2040 }
2041 return 0;
2042
2043 case SNDCTL_DSP_CHANNELS:
2044 if (get_user(val, (int *) arg))
2045 return -EFAULT;
2046 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2047 "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2048 val));
2049 if (val != 0) {
2050 if (file->f_mode & FMODE_READ) {
2051 stop_adc(s);
2052 s->dma_adc.ready = 0;
2053 if (val >= 2)
2054 s->prop_adc.channels = 2;
2055 else
2056 s->prop_adc.channels = 1;
2057 }
2058 if (file->f_mode & FMODE_WRITE) {
2059 stop_dac(s);
2060 s->dma_dac.ready = 0;
2061 if (val >= 2)
2062 s->prop_dac.channels = 2;
2063 else
2064 s->prop_dac.channels = 1;
2065 }
2066 }
2067
2068 if (file->f_mode & FMODE_WRITE)
2069 val = s->prop_dac.channels;
2070 else if (file->f_mode & FMODE_READ)
2071 val = s->prop_adc.channels;
2072
2073 return put_user(val, (int *) arg);
2074
2075 case SNDCTL_DSP_GETFMTS: // Returns a mask
2076 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2077 "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2078 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2079 AFMT_U8));
2080 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2081 AFMT_U8, (int *) arg);
2082
2083 case SNDCTL_DSP_SETFMT:
2084 if (get_user(val, (int *) arg))
2085 return -EFAULT;
2086 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2087 "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2088 val));
2089 if (val != AFMT_QUERY) {
2090 if (file->f_mode & FMODE_READ) {
2091 stop_adc(s);
2092 s->dma_adc.ready = 0;
2093 if (val != AFMT_S16_LE
2094 && val != AFMT_U16_LE && val != AFMT_S8
2095 && val != AFMT_U8)
2096 val = AFMT_U8;
2097 s->prop_adc.fmt = val;
2098 s->prop_adc.fmt_original = s->prop_adc.fmt;
2099 }
2100 if (file->f_mode & FMODE_WRITE) {
2101 stop_dac(s);
2102 s->dma_dac.ready = 0;
2103 if (val != AFMT_S16_LE
2104 && val != AFMT_U16_LE && val != AFMT_S8
2105 && val != AFMT_U8)
2106 val = AFMT_U8;
2107 s->prop_dac.fmt = val;
2108 s->prop_dac.fmt_original = s->prop_dac.fmt;
2109 }
2110 } else {
2111 if (file->f_mode & FMODE_WRITE)
2112 val = s->prop_dac.fmt_original;
2113 else if (file->f_mode & FMODE_READ)
2114 val = s->prop_adc.fmt_original;
2115 }
2116 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2117 "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2118 val));
2119 return put_user(val, (int *) arg);
2120
2121 case SNDCTL_DSP_POST:
2122 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2123 "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2124 return 0;
2125
2126 case SNDCTL_DSP_GETTRIGGER:
2127 val = 0;
2128 if (file->f_mode & s->ena & FMODE_READ)
2129 val |= PCM_ENABLE_INPUT;
2130 if (file->f_mode & s->ena & FMODE_WRITE)
2131 val |= PCM_ENABLE_OUTPUT;
2132 return put_user(val, (int *) arg);
2133
2134 case SNDCTL_DSP_SETTRIGGER:
2135 if (get_user(val, (int *) arg))
2136 return -EFAULT;
2137 if (file->f_mode & FMODE_READ) {
2138 if (val & PCM_ENABLE_INPUT) {
2139 if (!s->dma_adc.ready
2140 && (ret = prog_dmabuf_adc(s)))
2141 return ret;
2142 start_adc(s);
2143 } else
2144 stop_adc(s);
2145 }
2146 if (file->f_mode & FMODE_WRITE) {
2147 if (val & PCM_ENABLE_OUTPUT) {
2148 if (!s->dma_dac.ready
2149 && (ret = prog_dmabuf_dac(s)))
2150 return ret;
2151 start_dac(s);
2152 } else
2153 stop_dac(s);
2154 }
2155 return 0;
2156
2157 case SNDCTL_DSP_GETOSPACE:
2158 if (!(file->f_mode & FMODE_WRITE))
2159 return -EINVAL;
2160 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2161 return val;
2162 spin_lock_irqsave(&s->lock, flags);
2163 cs4297a_update_ptr(s,CS_FALSE);
2164 abinfo.fragsize = s->dma_dac.fragsize;
2165 if (s->dma_dac.mapped)
2166 abinfo.bytes = s->dma_dac.sbufsz;
2167 else
2168 abinfo.bytes =
2169 s->dma_dac.sbufsz - s->dma_dac.count;
2170 abinfo.fragstotal = s->dma_dac.numfrag;
2171 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2172 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2173 "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2174 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2175 abinfo.fragments));
2176 spin_unlock_irqrestore(&s->lock, flags);
2177 return copy_to_user((void *) arg, &abinfo,
2178 sizeof(abinfo)) ? -EFAULT : 0;
2179
2180 case SNDCTL_DSP_GETISPACE:
2181 if (!(file->f_mode & FMODE_READ))
2182 return -EINVAL;
2183 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2184 return val;
2185 spin_lock_irqsave(&s->lock, flags);
2186 cs4297a_update_ptr(s,CS_FALSE);
2187 if (s->conversion) {
2188 abinfo.fragsize = s->dma_adc.fragsize / 2;
2189 abinfo.bytes = s->dma_adc.count / 2;
2190 abinfo.fragstotal = s->dma_adc.numfrag;
2191 abinfo.fragments =
2192 abinfo.bytes >> (s->dma_adc.fragshift - 1);
2193 } else {
2194 abinfo.fragsize = s->dma_adc.fragsize;
2195 abinfo.bytes = s->dma_adc.count;
2196 abinfo.fragstotal = s->dma_adc.numfrag;
2197 abinfo.fragments =
2198 abinfo.bytes >> s->dma_adc.fragshift;
2199 }
2200 spin_unlock_irqrestore(&s->lock, flags);
2201 return copy_to_user((void *) arg, &abinfo,
2202 sizeof(abinfo)) ? -EFAULT : 0;
2203
2204 case SNDCTL_DSP_NONBLOCK:
Jonathan Corbetdb1dd4d2009-02-06 15:25:24 -0700[diff] [blame]2205 spin_lock(&file->f_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2206 file->f_flags |= O_NONBLOCK;
Jonathan Corbetdb1dd4d2009-02-06 15:25:24 -0700[diff] [blame]2207 spin_unlock(&file->f_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2208 return 0;
2209
2210 case SNDCTL_DSP_GETODELAY:
2211 if (!(file->f_mode & FMODE_WRITE))
2212 return -EINVAL;
2213 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2214 return 0;
2215 spin_lock_irqsave(&s->lock, flags);
2216 cs4297a_update_ptr(s,CS_FALSE);
2217 val = s->dma_dac.count;
2218 spin_unlock_irqrestore(&s->lock, flags);
2219 return put_user(val, (int *) arg);
2220
2221 case SNDCTL_DSP_GETIPTR:
2222 if (!(file->f_mode & FMODE_READ))
2223 return -EINVAL;
2224 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2225 return 0;
2226 spin_lock_irqsave(&s->lock, flags);
2227 cs4297a_update_ptr(s,CS_FALSE);
2228 cinfo.bytes = s->dma_adc.total_bytes;
2229 if (s->dma_adc.mapped) {
2230 cinfo.blocks =
2231 (cinfo.bytes >> s->dma_adc.fragshift) -
2232 s->dma_adc.blocks;
2233 s->dma_adc.blocks =
2234 cinfo.bytes >> s->dma_adc.fragshift;
2235 } else {
2236 if (s->conversion) {
2237 cinfo.blocks =
2238 s->dma_adc.count /
2239 2 >> (s->dma_adc.fragshift - 1);
2240 } else
2241 cinfo.blocks =
2242 s->dma_adc.count >> s->dma_adc.
2243 fragshift;
2244 }
2245 if (s->conversion)
2246 cinfo.ptr = s->dma_adc.hwptr / 2;
2247 else
2248 cinfo.ptr = s->dma_adc.hwptr;
2249 if (s->dma_adc.mapped)
2250 s->dma_adc.count &= s->dma_adc.fragsize - 1;
2251 spin_unlock_irqrestore(&s->lock, flags);
2252 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2253
2254 case SNDCTL_DSP_GETOPTR:
2255 if (!(file->f_mode & FMODE_WRITE))
2256 return -EINVAL;
2257 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2258 return 0;
2259 spin_lock_irqsave(&s->lock, flags);
2260 cs4297a_update_ptr(s,CS_FALSE);
2261 cinfo.bytes = s->dma_dac.total_bytes;
2262 if (s->dma_dac.mapped) {
2263 cinfo.blocks =
2264 (cinfo.bytes >> s->dma_dac.fragshift) -
2265 s->dma_dac.blocks;
2266 s->dma_dac.blocks =
2267 cinfo.bytes >> s->dma_dac.fragshift;
2268 } else {
2269 cinfo.blocks =
2270 s->dma_dac.count >> s->dma_dac.fragshift;
2271 }
2272 cinfo.ptr = s->dma_dac.hwptr;
2273 if (s->dma_dac.mapped)
2274 s->dma_dac.count &= s->dma_dac.fragsize - 1;
2275 spin_unlock_irqrestore(&s->lock, flags);
2276 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2277
2278 case SNDCTL_DSP_GETBLKSIZE:
2279 if (file->f_mode & FMODE_WRITE) {
2280 if ((val = prog_dmabuf_dac(s)))
2281 return val;
2282 return put_user(s->dma_dac.fragsize, (int *) arg);
2283 }
2284 if ((val = prog_dmabuf_adc(s)))
2285 return val;
2286 if (s->conversion)
2287 return put_user(s->dma_adc.fragsize / 2,
2288 (int *) arg);
2289 else
2290 return put_user(s->dma_adc.fragsize, (int *) arg);
2291
2292 case SNDCTL_DSP_SETFRAGMENT:
2293 if (get_user(val, (int *) arg))
2294 return -EFAULT;
2295 return 0; // Say OK, but do nothing.
2296
2297 case SNDCTL_DSP_SUBDIVIDE:
2298 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2299 || (file->f_mode & FMODE_WRITE
2300 && s->dma_dac.subdivision)) return -EINVAL;
2301 if (get_user(val, (int *) arg))
2302 return -EFAULT;
2303 if (val != 1 && val != 2 && val != 4)
2304 return -EINVAL;
2305 if (file->f_mode & FMODE_READ)
2306 s->dma_adc.subdivision = val;
2307 else if (file->f_mode & FMODE_WRITE)
2308 s->dma_dac.subdivision = val;
2309 return 0;
2310
2311 case SOUND_PCM_READ_RATE:
2312 if (file->f_mode & FMODE_READ)
2313 return put_user(s->prop_adc.rate, (int *) arg);
2314 else if (file->f_mode & FMODE_WRITE)
2315 return put_user(s->prop_dac.rate, (int *) arg);
2316
2317 case SOUND_PCM_READ_CHANNELS:
2318 if (file->f_mode & FMODE_READ)
2319 return put_user(s->prop_adc.channels, (int *) arg);
2320 else if (file->f_mode & FMODE_WRITE)
2321 return put_user(s->prop_dac.channels, (int *) arg);
2322
2323 case SOUND_PCM_READ_BITS:
2324 if (file->f_mode & FMODE_READ)
2325 return
2326 put_user(
2327 (s->prop_adc.
2328 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2329 (int *) arg);
2330 else if (file->f_mode & FMODE_WRITE)
2331 return
2332 put_user(
2333 (s->prop_dac.
2334 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2335 (int *) arg);
2336
2337 case SOUND_PCM_WRITE_FILTER:
2338 case SNDCTL_DSP_SETSYNCRO:
2339 case SOUND_PCM_READ_FILTER:
2340 return -EINVAL;
2341 }
2342 return mixer_ioctl(s, cmd, arg);
2343}
2344
2345
2346static int cs4297a_release(struct inode *inode, struct file *file)
2347{
2348 struct cs4297a_state *s =
2349 (struct cs4297a_state *) file->private_data;
2350
2351 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2352 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2353 (unsigned) inode, (unsigned) file, file->f_mode));
2354 VALIDATE_STATE(s);
2355
2356 if (file->f_mode & FMODE_WRITE) {
2357 drain_dac(s, file->f_flags & O_NONBLOCK);
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2358 mutex_lock(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2359 stop_dac(s);
2360 dealloc_dmabuf(s, &s->dma_dac);
2361 s->open_mode &= ~FMODE_WRITE;
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2362 mutex_unlock(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2363 wake_up(&s->open_wait_dac);
2364 }
2365 if (file->f_mode & FMODE_READ) {
2366 drain_adc(s, file->f_flags & O_NONBLOCK);
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2367 mutex_lock(&s->open_sem_adc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2368 stop_adc(s);
2369 dealloc_dmabuf(s, &s->dma_adc);
2370 s->open_mode &= ~FMODE_READ;
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2371 mutex_unlock(&s->open_sem_adc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2372 wake_up(&s->open_wait_adc);
2373 }
2374 return 0;
2375}
2376
Arnd Bergmann90dc7632010-07-11 12:16:36 +0200[diff] [blame^]2377static int cs4297a_locked_open(struct inode *inode, struct file *file)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2378{
2379 int minor = iminor(inode);
2380 struct cs4297a_state *s=NULL;
2381 struct list_head *entry;
2382
2383 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2384 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2385 (unsigned) inode, (unsigned) file, file->f_mode));
2386 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2387 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2388
2389 list_for_each(entry, &cs4297a_devs)
2390 {
2391 s = list_entry(entry, struct cs4297a_state, list);
2392
2393 if (!((s->dev_audio ^ minor) & ~0xf))
2394 break;
2395 }
2396 if (entry == &cs4297a_devs)
2397 return -ENODEV;
2398 if (!s) {
2399 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2400 "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2401 return -ENODEV;
2402 }
2403 VALIDATE_STATE(s);
2404 file->private_data = s;
2405
2406 // wait for device to become free
2407 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2408 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2409 "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2410 return -ENODEV;
2411 }
2412 if (file->f_mode & FMODE_WRITE) {
2413 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2414 printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2415 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2416 ;
2417 }
2418
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2419 mutex_lock(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2420 while (s->open_mode & FMODE_WRITE) {
2421 if (file->f_flags & O_NONBLOCK) {
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2422 mutex_unlock(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2423 return -EBUSY;
2424 }
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2425 mutex_unlock(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2426 interruptible_sleep_on(&s->open_wait_dac);
2427
2428 if (signal_pending(current)) {
2429 printk("open - sig pending\n");
2430 return -ERESTARTSYS;
2431 }
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2432 mutex_lock(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2433 }
2434 }
2435 if (file->f_mode & FMODE_READ) {
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2436 mutex_lock(&s->open_sem_adc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2437 while (s->open_mode & FMODE_READ) {
2438 if (file->f_flags & O_NONBLOCK) {
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2439 mutex_unlock(&s->open_sem_adc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2440 return -EBUSY;
2441 }
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2442 mutex_unlock(&s->open_sem_adc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2443 interruptible_sleep_on(&s->open_wait_adc);
2444
2445 if (signal_pending(current)) {
2446 printk("open - sig pending\n");
2447 return -ERESTARTSYS;
2448 }
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2449 mutex_lock(&s->open_sem_adc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2450 }
2451 }
2452 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2453 if (file->f_mode & FMODE_READ) {
2454 s->prop_adc.fmt = AFMT_S16_BE;
2455 s->prop_adc.fmt_original = s->prop_adc.fmt;
2456 s->prop_adc.channels = 2;
2457 s->prop_adc.rate = 48000;
2458 s->conversion = 0;
2459 s->ena &= ~FMODE_READ;
2460 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2461 s->dma_adc.subdivision = 0;
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2462 mutex_unlock(&s->open_sem_adc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2463
2464 if (prog_dmabuf_adc(s)) {
2465 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2466 "cs4297a: adc Program dmabufs failed.\n"));
2467 cs4297a_release(inode, file);
2468 return -ENOMEM;
2469 }
2470 }
2471 if (file->f_mode & FMODE_WRITE) {
2472 s->prop_dac.fmt = AFMT_S16_BE;
2473 s->prop_dac.fmt_original = s->prop_dac.fmt;
2474 s->prop_dac.channels = 2;
2475 s->prop_dac.rate = 48000;
2476 s->conversion = 0;
2477 s->ena &= ~FMODE_WRITE;
2478 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2479 s->dma_dac.subdivision = 0;
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2480 mutex_unlock(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2481
2482 if (prog_dmabuf_dac(s)) {
2483 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2484 "cs4297a: dac Program dmabufs failed.\n"));
2485 cs4297a_release(inode, file);
2486 return -ENOMEM;
2487 }
2488 }
2489 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2490 printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2491 return nonseekable_open(inode, file);
2492}
2493
Arnd Bergmann90dc7632010-07-11 12:16:36 +0200[diff] [blame^]2494static int cs4297a_open(struct inode *inode, struct file *file)
2495{
2496 int ret;
2497
2498 lock_kernel();
2499 ret = cs4297a_open(inode, file);
2500 unlock_kernel();
2501
2502 return ret;
2503}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2504
2505// ******************************************************************************************
2506// Wave (audio) file operations struct.
2507// ******************************************************************************************
Jan Engelhardtc8cece82008-02-08 04:21:20 -0800[diff] [blame]2508static const struct file_operations cs4297a_audio_fops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2509 .owner = THIS_MODULE,
2510 .llseek = no_llseek,
2511 .read = cs4297a_read,
2512 .write = cs4297a_write,
2513 .poll = cs4297a_poll,
2514 .ioctl = cs4297a_ioctl,
2515 .mmap = cs4297a_mmap,
2516 .open = cs4297a_open,
2517 .release = cs4297a_release,
2518};
2519
David Howells7d12e782006-10-05 14:55:46 +0100[diff] [blame]2520static void cs4297a_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2521{
2522 struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2523 u32 status;
2524
2525 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2526
2527 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2528 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2529
2530#if 0
2531 /* XXXKW what check *should* be done here? */
2532 if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2533 status = __raw_readq(SS_CSR(R_SER_STATUS));
2534 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2535 return;
2536 }
2537#endif
2538
2539 if (status & M_SYNCSER_RX_SYNC_ERR) {
2540 status = __raw_readq(SS_CSR(R_SER_STATUS));
2541 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2542 return;
2543 }
2544
2545 if (status & M_SYNCSER_RX_OVERRUN) {
2546 int newptr, i;
2547 s->stats.rx_ovrrn++;
2548 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2549
2550 /* Fix things up: get the receive descriptor pool
2551 clean and give them back to the hardware */
2552 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2553 ;
2554 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2555 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2556 for (i=0; i<DMA_DESCR; i++) {
2557 s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2558 }
2559 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2560 s->dma_adc.count = 0;
2561 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2562 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2563 }
2564
2565 spin_lock(&s->lock);
2566 cs4297a_update_ptr(s,CS_TRUE);
2567 spin_unlock(&s->lock);
2568
2569 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2570 "cs4297a: cs4297a_interrupt()-\n"));
2571}
2572
2573#if 0
2574static struct initvol {
2575 int mixch;
2576 int vol;
2577} initvol[] __initdata = {
2578
2579 {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2580 {SOUND_MIXER_WRITE_PCM, 0x4040},
2581 {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2582 {SOUND_MIXER_WRITE_CD, 0x4040},
2583 {SOUND_MIXER_WRITE_LINE, 0x4040},
2584 {SOUND_MIXER_WRITE_LINE1, 0x4040},
2585 {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2586 {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2587 {SOUND_MIXER_WRITE_MIC, 0x0000}
2588};
2589#endif
2590
2591static int __init cs4297a_init(void)
2592{
2593 struct cs4297a_state *s;
2594 u32 pwr, id;
2595 mm_segment_t fs;
2596 int rval;
2597#ifndef CONFIG_BCM_CS4297A_CSWARM
2598 u64 cfg;
2599 int mdio_val;
2600#endif
2601
2602 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2603 "cs4297a: cs4297a_init_module()+ \n"));
2604
2605#ifndef CONFIG_BCM_CS4297A_CSWARM
2606 mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2607 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2608
2609 /* Check syscfg for synchronous serial on port 1 */
2610 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2611 if (!(cfg & M_SYS_SER1_ENABLE)) {
2612 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2613 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2614 if (!(cfg & M_SYS_SER1_ENABLE)) {
2615 printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2616 return -1;
2617 }
2618
2619 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2620
2621 /* Force the codec (on SWARM) to reset by clearing
2622 GENO, preserving MDIO (no effect on CSWARM) */
2623 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2624 udelay(10);
2625 }
2626
2627 /* Now set GENO */
2628 __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2629 /* Give the codec some time to finish resetting (start the bit clock) */
2630 udelay(100);
2631#endif
2632
Robert P. J. Day3159f062007-02-14 00:33:16 -0800[diff] [blame]2633 if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2634 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2635 "cs4297a: probe() no memory for state struct.\n"));
2636 return -1;
2637 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2638 s->magic = CS4297a_MAGIC;
2639 init_waitqueue_head(&s->dma_adc.wait);
2640 init_waitqueue_head(&s->dma_dac.wait);
2641 init_waitqueue_head(&s->dma_adc.reg_wait);
2642 init_waitqueue_head(&s->dma_dac.reg_wait);
2643 init_waitqueue_head(&s->open_wait);
2644 init_waitqueue_head(&s->open_wait_adc);
2645 init_waitqueue_head(&s->open_wait_dac);
Ingo Molnar910f5d22006-03-23 03:00:39 -0800[diff] [blame]2646 mutex_init(&s->open_sem_adc);
2647 mutex_init(&s->open_sem_dac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2648 spin_lock_init(&s->lock);
2649
2650 s->irq = K_INT_SER_1;
2651
2652 if (request_irq
2653 (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2654 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2655 printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2656 goto err_irq;
2657 }
2658 if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2659 0) {
2660 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2661 "cs4297a: probe() register_sound_dsp() failed.\n"));
2662 goto err_dev1;
2663 }
2664 if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2665 0) {
2666 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2667 "cs4297a: probe() register_sound_mixer() failed.\n"));
2668 goto err_dev2;
2669 }
2670
2671 if (ser_init(s) || dma_init(s)) {
2672 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2673 "cs4297a: ser_init failed.\n"));
2674 goto err_dev3;
2675 }
2676
2677 do {
2678 udelay(4000);
2679 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2680 } while (!rval && (pwr != 0xf));
2681
2682 if (!rval) {
2683 char *sb1250_duart_present;
2684
2685 fs = get_fs();
2686 set_fs(KERNEL_DS);
2687#if 0
2688 val = SOUND_MASK_LINE;
2689 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
Ahmed S. Darwish8b5925f2007-02-12 00:52:08 -0800[diff] [blame]2690 for (i = 0; i < ARRAY_SIZE(initvol); i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2691 val = initvol[i].vol;
2692 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2693 }
2694// cs4297a_write_ac97(s, 0x18, 0x0808);
2695#else
2696 // cs4297a_write_ac97(s, 0x5e, 0x180);
2697 cs4297a_write_ac97(s, 0x02, 0x0808);
2698 cs4297a_write_ac97(s, 0x18, 0x0808);
2699#endif
2700 set_fs(fs);
2701
2702 list_add(&s->list, &cs4297a_devs);
2703
2704 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2705
2706 sb1250_duart_present = symbol_get(sb1250_duart_present);
2707 if (sb1250_duart_present)
2708 sb1250_duart_present[1] = 0;
2709
2710 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2711
2712 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2713 printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2714
2715 return 0;
2716 }
2717
2718 err_dev3:
2719 unregister_sound_mixer(s->dev_mixer);
2720 err_dev2:
2721 unregister_sound_dsp(s->dev_audio);
2722 err_dev1:
2723 free_irq(s->irq, s);
2724 err_irq:
2725 kfree(s);
2726
2727 printk(KERN_INFO "cs4297a: initialization failed\n");
2728
2729 return -1;
2730}
2731
2732static void __exit cs4297a_cleanup(void)
2733{
2734 /*
2735 XXXKW
2736 disable_irq, free_irq
2737 drain DMA queue
2738 disable DMA
2739 disable TX/RX
2740 free memory
2741 */
2742 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2743 printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2744}
2745
2746// ---------------------------------------------------------------------
2747
2748MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2749MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2750
2751// ---------------------------------------------------------------------
2752
2753module_init(cs4297a_init);
2754module_exit(cs4297a_cleanup);