Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
| 4 | * |
| 5 | * ######################################################################## |
| 6 | * |
| 7 | * This program is free software; you can distribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License (Version 2) as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 19 | * |
| 20 | * ######################################################################## |
| 21 | * |
| 22 | * Defines for the Malta interrupt controller. |
| 23 | * |
| 24 | */ |
| 25 | #ifndef _MIPS_MALTAINT_H |
| 26 | #define _MIPS_MALTAINT_H |
| 27 | |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 28 | #include <irq.h> |
| 29 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 30 | /* |
| 31 | * Interrupts 0..15 are used for Malta ISA compatible interrupts |
| 32 | */ |
| 33 | #define MALTA_INT_BASE 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 35 | /* CPU interrupt offsets */ |
| 36 | #define MIPSCPU_INT_SW0 0 |
| 37 | #define MIPSCPU_INT_SW1 1 |
| 38 | #define MIPSCPU_INT_MB0 2 |
| 39 | #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 |
| 40 | #define MIPSCPU_INT_MB1 3 |
| 41 | #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 42 | #define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 43 | #define MIPSCPU_INT_MB2 4 |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 44 | #define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 45 | #define MIPSCPU_INT_MB3 5 |
| 46 | #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 |
| 47 | #define MIPSCPU_INT_MB4 6 |
| 48 | #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 49 | |
| 50 | /* |
| 51 | * Interrupts 64..127 are used for Soc-it Classic interrupts |
| 52 | */ |
| 53 | #define MSC01C_INT_BASE 64 |
| 54 | |
| 55 | /* SOC-it Classic interrupt offsets */ |
| 56 | #define MSC01C_INT_TMR 0 |
| 57 | #define MSC01C_INT_PCI 1 |
| 58 | |
| 59 | /* |
| 60 | * Interrupts 64..127 are used for Soc-it EIC interrupts |
| 61 | */ |
| 62 | #define MSC01E_INT_BASE 64 |
| 63 | |
| 64 | /* SOC-it EIC interrupt offsets */ |
| 65 | #define MSC01E_INT_SW0 1 |
| 66 | #define MSC01E_INT_SW1 2 |
| 67 | #define MSC01E_INT_MB0 3 |
| 68 | #define MSC01E_INT_I8259A MSC01E_INT_MB0 |
| 69 | #define MSC01E_INT_MB1 4 |
| 70 | #define MSC01E_INT_SMI MSC01E_INT_MB1 |
| 71 | #define MSC01E_INT_MB2 5 |
| 72 | #define MSC01E_INT_MB3 6 |
| 73 | #define MSC01E_INT_COREHI MSC01E_INT_MB3 |
| 74 | #define MSC01E_INT_MB4 7 |
| 75 | #define MSC01E_INT_CORELO MSC01E_INT_MB4 |
| 76 | #define MSC01E_INT_TMR 8 |
| 77 | #define MSC01E_INT_PCI 9 |
| 78 | #define MSC01E_INT_PERFCTR 10 |
| 79 | #define MSC01E_INT_CPUCTR 11 |
| 80 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 81 | /* GIC's Nomenclature for Core Interrupt Pins on the Malta */ |
| 82 | #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ |
| 83 | #define GIC_CPU_INT1 1 /* . */ |
| 84 | #define GIC_CPU_INT2 2 /* . */ |
| 85 | #define GIC_CPU_INT3 3 /* . */ |
| 86 | #define GIC_CPU_INT4 4 /* . */ |
| 87 | #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ |
| 88 | |
| 89 | #define GIC_EXT_INTR(x) x |
| 90 | |
| 91 | /* Dummy data */ |
| 92 | #define X 0xdead |
| 93 | |
| 94 | /* External Interrupts used for IPI */ |
| 95 | #define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 |
| 96 | #define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 |
| 97 | #define GIC_IPI_EXT_INTR_RESCHED_VPE1 18 |
| 98 | #define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19 |
| 99 | #define GIC_IPI_EXT_INTR_RESCHED_VPE2 20 |
| 100 | #define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21 |
| 101 | #define GIC_IPI_EXT_INTR_RESCHED_VPE3 22 |
| 102 | #define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23 |
| 103 | |
| 104 | #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) |
| 105 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 106 | #ifndef __ASSEMBLY__ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | extern void maltaint_init(void); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 108 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | |
| 110 | #endif /* !(_MIPS_MALTAINT_H) */ |