blob: 7939387f7f80644db263cf1ab32efaf8b3299dac [file] [log] [blame]
Ben Skeggsa11c3192010-08-27 10:00:25 +10001/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_vm.h"
29
30void
31nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 type, u32 pde,
32 struct nouveau_gpuobj *pgt)
33{
34 struct drm_nouveau_private *dev_priv = pgd->dev->dev_private;
35 u32 coverage = (pgt->size >> 3) << type;
36 u64 phys;
37
38 phys = pgt->vinst;
39 phys |= 0x01; /* present */
40 phys |= (type == 12) ? 0x02 : 0x00; /* 4KiB pages */
41 if (dev_priv->vram_sys_base) {
42 phys += dev_priv->vram_sys_base;
43 phys |= 0x30;
44 }
45
46 if (coverage <= 32 * 1024 * 1024)
47 phys |= 0x60;
48 else if (coverage <= 64 * 1024 * 1024)
49 phys |= 0x40;
50 else if (coverage < 128 * 1024 * 1024)
51 phys |= 0x20;
52
53 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
54 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
55}
56
57void
58nv50_vm_unmap_pgt(struct nouveau_gpuobj *pgd, u32 pde)
59{
60 nv_wo32(pgd, (pde * 8) + 0, 0x00000000);
61 nv_wo32(pgd, (pde * 8) + 4, 0xdeadcafe);
62}
63
64static inline u64
65nv50_vm_addr(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
66 u64 phys, u32 memtype, u32 target)
67{
68 struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;
69
70 phys |= 1; /* present */
71 phys |= (u64)memtype << 40;
72
73 /* IGPs don't have real VRAM, re-target to stolen system memory */
74 if (target == 0 && dev_priv->vram_sys_base) {
75 phys += dev_priv->vram_sys_base;
76 target = 3;
77 }
78
79 phys |= target << 4;
80
81 if (vma->access & NV_MEM_ACCESS_SYS)
82 phys |= (1 << 6);
83
84 if (!(vma->access & NV_MEM_ACCESS_WO))
85 phys |= (1 << 3);
86
87 return phys;
88}
89
90void
91nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
92 struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
93{
Ben Skeggs910d1b32010-12-21 11:15:44 +100094 u32 block;
95 int i;
Ben Skeggsa11c3192010-08-27 10:00:25 +100096
97 phys = nv50_vm_addr(vma, pgt, phys, mem->memtype, 0);
98 pte <<= 3;
99 cnt <<= 3;
100
101 while (cnt) {
102 u32 offset_h = upper_32_bits(phys);
103 u32 offset_l = lower_32_bits(phys);
104
105 for (i = 7; i >= 0; i--) {
106 block = 1 << (i + 3);
107 if (cnt >= block && !(pte & (block - 1)))
108 break;
109 }
110 offset_l |= (i << 7);
111
112 phys += block << (vma->node->type - 3);
113 cnt -= block;
114
115 while (block) {
116 nv_wo32(pgt, pte + 0, offset_l);
117 nv_wo32(pgt, pte + 4, offset_h);
118 pte += 8;
119 block -= 8;
120 }
121 }
122}
123
124void
125nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
126 u32 pte, dma_addr_t *list, u32 cnt)
127{
128 pte <<= 3;
129 while (cnt--) {
130 u64 phys = nv50_vm_addr(vma, pgt, (u64)*list++, 0, 2);
131 nv_wo32(pgt, pte + 0, lower_32_bits(phys));
132 nv_wo32(pgt, pte + 4, upper_32_bits(phys));
133 pte += 8;
134 }
135}
136
137void
138nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
139{
140 pte <<= 3;
141 while (cnt--) {
142 nv_wo32(pgt, pte + 0, 0x00000000);
143 nv_wo32(pgt, pte + 4, 0x00000000);
144 pte += 8;
145 }
146}
147
148void
149nv50_vm_flush(struct nouveau_vm *vm)
150{
151 struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
152 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
Ben Skeggs4c1361422010-11-15 11:54:21 +1000153 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
154 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
155 struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
Ben Skeggsa11c3192010-08-27 10:00:25 +1000156
157 pinstmem->flush(vm->dev);
Ben Skeggs4c1361422010-11-15 11:54:21 +1000158
159 /* BAR */
160 if (vm != dev_priv->chan_vm) {
161 nv50_vm_flush_engine(vm->dev, 6);
162 return;
163 }
164
165 pfifo->tlb_flush(vm->dev);
166
167 if (atomic_read(&vm->pgraph_refs))
168 pgraph->tlb_flush(vm->dev);
169 if (atomic_read(&vm->pcrypt_refs))
170 pcrypt->tlb_flush(vm->dev);
Ben Skeggsa11c3192010-08-27 10:00:25 +1000171}
172
173void
174nv50_vm_flush_engine(struct drm_device *dev, int engine)
175{
176 nv_wr32(dev, 0x100c80, (engine << 16) | 1);
177 if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
178 NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
179}