Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1 | /* |
| 2 | * rt5677.c -- RT5677 ALSA SoC audio codec driver |
| 3 | * |
| 4 | * Copyright 2013 Realtek Semiconductor Corp. |
| 5 | * Author: Oder Chiou <oder_chiou@realtek.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/fs.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/moduleparam.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/pm.h> |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 18 | #include <linux/of_gpio.h> |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 19 | #include <linux/regmap.h> |
| 20 | #include <linux/i2c.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/spi/spi.h> |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 23 | #include <linux/firmware.h> |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 24 | #include <linux/gpio.h> |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 25 | #include <sound/core.h> |
| 26 | #include <sound/pcm.h> |
| 27 | #include <sound/pcm_params.h> |
| 28 | #include <sound/soc.h> |
| 29 | #include <sound/soc-dapm.h> |
| 30 | #include <sound/initval.h> |
| 31 | #include <sound/tlv.h> |
| 32 | |
Axel Lin | 30f14b4 | 2014-06-10 08:57:36 +0800 | [diff] [blame] | 33 | #include "rl6231.h" |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 34 | #include "rt5677.h" |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 35 | #include "rt5677-spi.h" |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 36 | |
| 37 | #define RT5677_DEVICE_ID 0x6327 |
| 38 | |
| 39 | #define RT5677_PR_RANGE_BASE (0xff + 1) |
| 40 | #define RT5677_PR_SPACING 0x100 |
| 41 | |
| 42 | #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) |
| 43 | |
| 44 | static const struct regmap_range_cfg rt5677_ranges[] = { |
| 45 | { |
| 46 | .name = "PR", |
| 47 | .range_min = RT5677_PR_BASE, |
| 48 | .range_max = RT5677_PR_BASE + 0xfd, |
| 49 | .selector_reg = RT5677_PRIV_INDEX, |
| 50 | .selector_mask = 0xff, |
| 51 | .selector_shift = 0x0, |
| 52 | .window_start = RT5677_PRIV_DATA, |
| 53 | .window_len = 0x1, |
| 54 | }, |
| 55 | }; |
| 56 | |
| 57 | static const struct reg_default init_list[] = { |
| 58 | {RT5677_PR_BASE + 0x3d, 0x364d}, |
| 59 | {RT5677_PR_BASE + 0x17, 0x4fc0}, |
| 60 | {RT5677_PR_BASE + 0x13, 0x0312}, |
| 61 | {RT5677_PR_BASE + 0x1e, 0x0000}, |
| 62 | {RT5677_PR_BASE + 0x12, 0x0eaa}, |
| 63 | {RT5677_PR_BASE + 0x14, 0x018a}, |
| 64 | }; |
| 65 | #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) |
| 66 | |
| 67 | static const struct reg_default rt5677_reg[] = { |
| 68 | {RT5677_RESET , 0x0000}, |
| 69 | {RT5677_LOUT1 , 0xa800}, |
| 70 | {RT5677_IN1 , 0x0000}, |
| 71 | {RT5677_MICBIAS , 0x0000}, |
| 72 | {RT5677_SLIMBUS_PARAM , 0x0000}, |
| 73 | {RT5677_SLIMBUS_RX , 0x0000}, |
| 74 | {RT5677_SLIMBUS_CTRL , 0x0000}, |
| 75 | {RT5677_SIDETONE_CTRL , 0x000b}, |
| 76 | {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, |
| 77 | {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, |
| 78 | {RT5677_DAC4_DIG_VOL , 0xafaf}, |
| 79 | {RT5677_DAC3_DIG_VOL , 0xafaf}, |
| 80 | {RT5677_DAC1_DIG_VOL , 0xafaf}, |
| 81 | {RT5677_DAC2_DIG_VOL , 0xafaf}, |
| 82 | {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, |
| 83 | {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, |
| 84 | {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, |
| 85 | {RT5677_STO1_2_ADC_BST , 0x0000}, |
| 86 | {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, |
| 87 | {RT5677_ADC_BST_CTRL2 , 0x0000}, |
| 88 | {RT5677_STO3_4_ADC_BST , 0x0000}, |
| 89 | {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, |
| 90 | {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, |
| 91 | {RT5677_STO4_ADC_MIXER , 0xd4c0}, |
| 92 | {RT5677_STO3_ADC_MIXER , 0xd4c0}, |
| 93 | {RT5677_STO2_ADC_MIXER , 0xd4c0}, |
| 94 | {RT5677_STO1_ADC_MIXER , 0xd4c0}, |
| 95 | {RT5677_MONO_ADC_MIXER , 0xd4d1}, |
| 96 | {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, |
| 97 | {RT5677_STO1_DAC_MIXER , 0xaaaa}, |
| 98 | {RT5677_MONO_DAC_MIXER , 0xaaaa}, |
| 99 | {RT5677_DD1_MIXER , 0xaaaa}, |
| 100 | {RT5677_DD2_MIXER , 0xaaaa}, |
| 101 | {RT5677_IF3_DATA , 0x0000}, |
| 102 | {RT5677_IF4_DATA , 0x0000}, |
| 103 | {RT5677_PDM_OUT_CTRL , 0x8888}, |
| 104 | {RT5677_PDM_DATA_CTRL1 , 0x0000}, |
| 105 | {RT5677_PDM_DATA_CTRL2 , 0x0000}, |
| 106 | {RT5677_PDM1_DATA_CTRL2 , 0x0000}, |
| 107 | {RT5677_PDM1_DATA_CTRL3 , 0x0000}, |
| 108 | {RT5677_PDM1_DATA_CTRL4 , 0x0000}, |
| 109 | {RT5677_PDM2_DATA_CTRL2 , 0x0000}, |
| 110 | {RT5677_PDM2_DATA_CTRL3 , 0x0000}, |
| 111 | {RT5677_PDM2_DATA_CTRL4 , 0x0000}, |
| 112 | {RT5677_TDM1_CTRL1 , 0x0300}, |
| 113 | {RT5677_TDM1_CTRL2 , 0x0000}, |
| 114 | {RT5677_TDM1_CTRL3 , 0x4000}, |
| 115 | {RT5677_TDM1_CTRL4 , 0x0123}, |
| 116 | {RT5677_TDM1_CTRL5 , 0x4567}, |
| 117 | {RT5677_TDM2_CTRL1 , 0x0300}, |
| 118 | {RT5677_TDM2_CTRL2 , 0x0000}, |
| 119 | {RT5677_TDM2_CTRL3 , 0x4000}, |
| 120 | {RT5677_TDM2_CTRL4 , 0x0123}, |
| 121 | {RT5677_TDM2_CTRL5 , 0x4567}, |
| 122 | {RT5677_I2C_MASTER_CTRL1 , 0x0001}, |
| 123 | {RT5677_I2C_MASTER_CTRL2 , 0x0000}, |
| 124 | {RT5677_I2C_MASTER_CTRL3 , 0x0000}, |
| 125 | {RT5677_I2C_MASTER_CTRL4 , 0x0000}, |
| 126 | {RT5677_I2C_MASTER_CTRL5 , 0x0000}, |
| 127 | {RT5677_I2C_MASTER_CTRL6 , 0x0000}, |
| 128 | {RT5677_I2C_MASTER_CTRL7 , 0x0000}, |
| 129 | {RT5677_I2C_MASTER_CTRL8 , 0x0000}, |
| 130 | {RT5677_DMIC_CTRL1 , 0x1505}, |
| 131 | {RT5677_DMIC_CTRL2 , 0x0055}, |
| 132 | {RT5677_HAP_GENE_CTRL1 , 0x0111}, |
| 133 | {RT5677_HAP_GENE_CTRL2 , 0x0064}, |
| 134 | {RT5677_HAP_GENE_CTRL3 , 0xef0e}, |
| 135 | {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, |
| 136 | {RT5677_HAP_GENE_CTRL5 , 0xef0e}, |
| 137 | {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, |
| 138 | {RT5677_HAP_GENE_CTRL7 , 0xef0e}, |
| 139 | {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, |
| 140 | {RT5677_HAP_GENE_CTRL9 , 0xf000}, |
| 141 | {RT5677_HAP_GENE_CTRL10 , 0x0000}, |
| 142 | {RT5677_PWR_DIG1 , 0x0000}, |
| 143 | {RT5677_PWR_DIG2 , 0x0000}, |
| 144 | {RT5677_PWR_ANLG1 , 0x0055}, |
| 145 | {RT5677_PWR_ANLG2 , 0x0000}, |
| 146 | {RT5677_PWR_DSP1 , 0x0001}, |
| 147 | {RT5677_PWR_DSP_ST , 0x0000}, |
| 148 | {RT5677_PWR_DSP2 , 0x0000}, |
| 149 | {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, |
| 150 | {RT5677_PRIV_INDEX , 0x0000}, |
| 151 | {RT5677_PRIV_DATA , 0x0000}, |
| 152 | {RT5677_I2S4_SDP , 0x8000}, |
| 153 | {RT5677_I2S1_SDP , 0x8000}, |
| 154 | {RT5677_I2S2_SDP , 0x8000}, |
| 155 | {RT5677_I2S3_SDP , 0x8000}, |
| 156 | {RT5677_CLK_TREE_CTRL1 , 0x1111}, |
| 157 | {RT5677_CLK_TREE_CTRL2 , 0x1111}, |
| 158 | {RT5677_CLK_TREE_CTRL3 , 0x0000}, |
| 159 | {RT5677_PLL1_CTRL1 , 0x0000}, |
| 160 | {RT5677_PLL1_CTRL2 , 0x0000}, |
| 161 | {RT5677_PLL2_CTRL1 , 0x0c60}, |
| 162 | {RT5677_PLL2_CTRL2 , 0x2000}, |
| 163 | {RT5677_GLB_CLK1 , 0x0000}, |
| 164 | {RT5677_GLB_CLK2 , 0x0000}, |
| 165 | {RT5677_ASRC_1 , 0x0000}, |
| 166 | {RT5677_ASRC_2 , 0x0000}, |
| 167 | {RT5677_ASRC_3 , 0x0000}, |
| 168 | {RT5677_ASRC_4 , 0x0000}, |
| 169 | {RT5677_ASRC_5 , 0x0000}, |
| 170 | {RT5677_ASRC_6 , 0x0000}, |
| 171 | {RT5677_ASRC_7 , 0x0000}, |
| 172 | {RT5677_ASRC_8 , 0x0000}, |
| 173 | {RT5677_ASRC_9 , 0x0000}, |
| 174 | {RT5677_ASRC_10 , 0x0000}, |
| 175 | {RT5677_ASRC_11 , 0x0000}, |
| 176 | {RT5677_ASRC_12 , 0x0008}, |
| 177 | {RT5677_ASRC_13 , 0x0000}, |
| 178 | {RT5677_ASRC_14 , 0x0000}, |
| 179 | {RT5677_ASRC_15 , 0x0000}, |
| 180 | {RT5677_ASRC_16 , 0x0000}, |
| 181 | {RT5677_ASRC_17 , 0x0000}, |
| 182 | {RT5677_ASRC_18 , 0x0000}, |
| 183 | {RT5677_ASRC_19 , 0x0000}, |
| 184 | {RT5677_ASRC_20 , 0x0000}, |
| 185 | {RT5677_ASRC_21 , 0x000c}, |
| 186 | {RT5677_ASRC_22 , 0x0000}, |
| 187 | {RT5677_ASRC_23 , 0x0000}, |
| 188 | {RT5677_VAD_CTRL1 , 0x2184}, |
| 189 | {RT5677_VAD_CTRL2 , 0x010a}, |
| 190 | {RT5677_VAD_CTRL3 , 0x0aea}, |
| 191 | {RT5677_VAD_CTRL4 , 0x000c}, |
| 192 | {RT5677_VAD_CTRL5 , 0x0000}, |
| 193 | {RT5677_DSP_INB_CTRL1 , 0x0000}, |
| 194 | {RT5677_DSP_INB_CTRL2 , 0x0000}, |
| 195 | {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, |
| 196 | {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, |
| 197 | {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, |
| 198 | {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, |
| 199 | {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, |
| 200 | {RT5677_ADC_EQ_CTRL1 , 0x6000}, |
| 201 | {RT5677_ADC_EQ_CTRL2 , 0x0000}, |
| 202 | {RT5677_EQ_CTRL1 , 0xc000}, |
| 203 | {RT5677_EQ_CTRL2 , 0x0000}, |
| 204 | {RT5677_EQ_CTRL3 , 0x0000}, |
| 205 | {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, |
| 206 | {RT5677_JD_CTRL1 , 0x0000}, |
| 207 | {RT5677_JD_CTRL2 , 0x0000}, |
| 208 | {RT5677_JD_CTRL3 , 0x0000}, |
| 209 | {RT5677_IRQ_CTRL1 , 0x0000}, |
| 210 | {RT5677_IRQ_CTRL2 , 0x0000}, |
| 211 | {RT5677_GPIO_ST , 0x0000}, |
| 212 | {RT5677_GPIO_CTRL1 , 0x0000}, |
| 213 | {RT5677_GPIO_CTRL2 , 0x0000}, |
| 214 | {RT5677_GPIO_CTRL3 , 0x0000}, |
| 215 | {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, |
| 216 | {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, |
| 217 | {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, |
| 218 | {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, |
| 219 | {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, |
| 220 | {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, |
| 221 | {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, |
| 222 | {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, |
| 223 | {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, |
| 224 | {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, |
| 225 | {RT5677_MB_DRC_CTRL1 , 0x0f20}, |
| 226 | {RT5677_DRC1_CTRL1 , 0x001f}, |
| 227 | {RT5677_DRC1_CTRL2 , 0x020c}, |
| 228 | {RT5677_DRC1_CTRL3 , 0x1f00}, |
| 229 | {RT5677_DRC1_CTRL4 , 0x0000}, |
| 230 | {RT5677_DRC1_CTRL5 , 0x0000}, |
| 231 | {RT5677_DRC1_CTRL6 , 0x0029}, |
| 232 | {RT5677_DRC2_CTRL1 , 0x001f}, |
| 233 | {RT5677_DRC2_CTRL2 , 0x020c}, |
| 234 | {RT5677_DRC2_CTRL3 , 0x1f00}, |
| 235 | {RT5677_DRC2_CTRL4 , 0x0000}, |
| 236 | {RT5677_DRC2_CTRL5 , 0x0000}, |
| 237 | {RT5677_DRC2_CTRL6 , 0x0029}, |
| 238 | {RT5677_DRC1_HL_CTRL1 , 0x8000}, |
| 239 | {RT5677_DRC1_HL_CTRL2 , 0x0200}, |
| 240 | {RT5677_DRC2_HL_CTRL1 , 0x8000}, |
| 241 | {RT5677_DRC2_HL_CTRL2 , 0x0200}, |
| 242 | {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, |
| 243 | {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, |
| 244 | {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, |
| 245 | {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, |
| 246 | {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, |
| 247 | {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, |
| 248 | {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, |
| 249 | {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, |
| 250 | {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, |
| 251 | {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, |
| 252 | {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, |
| 253 | {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, |
| 254 | {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, |
| 255 | {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, |
| 256 | {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, |
| 257 | {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, |
| 258 | {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, |
| 259 | {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, |
| 260 | {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, |
| 261 | {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, |
| 262 | {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, |
| 263 | {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, |
| 264 | {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, |
| 265 | {RT5677_DIG_MISC , 0x0000}, |
| 266 | {RT5677_GEN_CTRL1 , 0x0000}, |
| 267 | {RT5677_GEN_CTRL2 , 0x0000}, |
| 268 | {RT5677_VENDOR_ID , 0x0000}, |
| 269 | {RT5677_VENDOR_ID1 , 0x10ec}, |
| 270 | {RT5677_VENDOR_ID2 , 0x6327}, |
| 271 | }; |
| 272 | |
| 273 | static bool rt5677_volatile_register(struct device *dev, unsigned int reg) |
| 274 | { |
| 275 | int i; |
| 276 | |
| 277 | for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { |
| 278 | if (reg >= rt5677_ranges[i].range_min && |
| 279 | reg <= rt5677_ranges[i].range_max) { |
| 280 | return true; |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | switch (reg) { |
| 285 | case RT5677_RESET: |
| 286 | case RT5677_SLIMBUS_PARAM: |
| 287 | case RT5677_PDM_DATA_CTRL1: |
| 288 | case RT5677_PDM_DATA_CTRL2: |
| 289 | case RT5677_PDM1_DATA_CTRL4: |
| 290 | case RT5677_PDM2_DATA_CTRL4: |
| 291 | case RT5677_I2C_MASTER_CTRL1: |
| 292 | case RT5677_I2C_MASTER_CTRL7: |
| 293 | case RT5677_I2C_MASTER_CTRL8: |
| 294 | case RT5677_HAP_GENE_CTRL2: |
| 295 | case RT5677_PWR_DSP_ST: |
| 296 | case RT5677_PRIV_DATA: |
| 297 | case RT5677_PLL1_CTRL2: |
| 298 | case RT5677_PLL2_CTRL2: |
| 299 | case RT5677_ASRC_22: |
| 300 | case RT5677_ASRC_23: |
| 301 | case RT5677_VAD_CTRL5: |
| 302 | case RT5677_ADC_EQ_CTRL1: |
| 303 | case RT5677_EQ_CTRL1: |
| 304 | case RT5677_IRQ_CTRL1: |
| 305 | case RT5677_IRQ_CTRL2: |
| 306 | case RT5677_GPIO_ST: |
| 307 | case RT5677_DSP_INB1_SRC_CTRL4: |
| 308 | case RT5677_DSP_INB2_SRC_CTRL4: |
| 309 | case RT5677_DSP_INB3_SRC_CTRL4: |
| 310 | case RT5677_DSP_OUTB1_SRC_CTRL4: |
| 311 | case RT5677_DSP_OUTB2_SRC_CTRL4: |
| 312 | case RT5677_VENDOR_ID: |
| 313 | case RT5677_VENDOR_ID1: |
| 314 | case RT5677_VENDOR_ID2: |
| 315 | return true; |
| 316 | default: |
| 317 | return false; |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | static bool rt5677_readable_register(struct device *dev, unsigned int reg) |
| 322 | { |
| 323 | int i; |
| 324 | |
| 325 | for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { |
| 326 | if (reg >= rt5677_ranges[i].range_min && |
| 327 | reg <= rt5677_ranges[i].range_max) { |
| 328 | return true; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | switch (reg) { |
| 333 | case RT5677_RESET: |
| 334 | case RT5677_LOUT1: |
| 335 | case RT5677_IN1: |
| 336 | case RT5677_MICBIAS: |
| 337 | case RT5677_SLIMBUS_PARAM: |
| 338 | case RT5677_SLIMBUS_RX: |
| 339 | case RT5677_SLIMBUS_CTRL: |
| 340 | case RT5677_SIDETONE_CTRL: |
| 341 | case RT5677_ANA_DAC1_2_3_SRC: |
| 342 | case RT5677_IF_DSP_DAC3_4_MIXER: |
| 343 | case RT5677_DAC4_DIG_VOL: |
| 344 | case RT5677_DAC3_DIG_VOL: |
| 345 | case RT5677_DAC1_DIG_VOL: |
| 346 | case RT5677_DAC2_DIG_VOL: |
| 347 | case RT5677_IF_DSP_DAC2_MIXER: |
| 348 | case RT5677_STO1_ADC_DIG_VOL: |
| 349 | case RT5677_MONO_ADC_DIG_VOL: |
| 350 | case RT5677_STO1_2_ADC_BST: |
| 351 | case RT5677_STO2_ADC_DIG_VOL: |
| 352 | case RT5677_ADC_BST_CTRL2: |
| 353 | case RT5677_STO3_4_ADC_BST: |
| 354 | case RT5677_STO3_ADC_DIG_VOL: |
| 355 | case RT5677_STO4_ADC_DIG_VOL: |
| 356 | case RT5677_STO4_ADC_MIXER: |
| 357 | case RT5677_STO3_ADC_MIXER: |
| 358 | case RT5677_STO2_ADC_MIXER: |
| 359 | case RT5677_STO1_ADC_MIXER: |
| 360 | case RT5677_MONO_ADC_MIXER: |
| 361 | case RT5677_ADC_IF_DSP_DAC1_MIXER: |
| 362 | case RT5677_STO1_DAC_MIXER: |
| 363 | case RT5677_MONO_DAC_MIXER: |
| 364 | case RT5677_DD1_MIXER: |
| 365 | case RT5677_DD2_MIXER: |
| 366 | case RT5677_IF3_DATA: |
| 367 | case RT5677_IF4_DATA: |
| 368 | case RT5677_PDM_OUT_CTRL: |
| 369 | case RT5677_PDM_DATA_CTRL1: |
| 370 | case RT5677_PDM_DATA_CTRL2: |
| 371 | case RT5677_PDM1_DATA_CTRL2: |
| 372 | case RT5677_PDM1_DATA_CTRL3: |
| 373 | case RT5677_PDM1_DATA_CTRL4: |
| 374 | case RT5677_PDM2_DATA_CTRL2: |
| 375 | case RT5677_PDM2_DATA_CTRL3: |
| 376 | case RT5677_PDM2_DATA_CTRL4: |
| 377 | case RT5677_TDM1_CTRL1: |
| 378 | case RT5677_TDM1_CTRL2: |
| 379 | case RT5677_TDM1_CTRL3: |
| 380 | case RT5677_TDM1_CTRL4: |
| 381 | case RT5677_TDM1_CTRL5: |
| 382 | case RT5677_TDM2_CTRL1: |
| 383 | case RT5677_TDM2_CTRL2: |
| 384 | case RT5677_TDM2_CTRL3: |
| 385 | case RT5677_TDM2_CTRL4: |
| 386 | case RT5677_TDM2_CTRL5: |
| 387 | case RT5677_I2C_MASTER_CTRL1: |
| 388 | case RT5677_I2C_MASTER_CTRL2: |
| 389 | case RT5677_I2C_MASTER_CTRL3: |
| 390 | case RT5677_I2C_MASTER_CTRL4: |
| 391 | case RT5677_I2C_MASTER_CTRL5: |
| 392 | case RT5677_I2C_MASTER_CTRL6: |
| 393 | case RT5677_I2C_MASTER_CTRL7: |
| 394 | case RT5677_I2C_MASTER_CTRL8: |
| 395 | case RT5677_DMIC_CTRL1: |
| 396 | case RT5677_DMIC_CTRL2: |
| 397 | case RT5677_HAP_GENE_CTRL1: |
| 398 | case RT5677_HAP_GENE_CTRL2: |
| 399 | case RT5677_HAP_GENE_CTRL3: |
| 400 | case RT5677_HAP_GENE_CTRL4: |
| 401 | case RT5677_HAP_GENE_CTRL5: |
| 402 | case RT5677_HAP_GENE_CTRL6: |
| 403 | case RT5677_HAP_GENE_CTRL7: |
| 404 | case RT5677_HAP_GENE_CTRL8: |
| 405 | case RT5677_HAP_GENE_CTRL9: |
| 406 | case RT5677_HAP_GENE_CTRL10: |
| 407 | case RT5677_PWR_DIG1: |
| 408 | case RT5677_PWR_DIG2: |
| 409 | case RT5677_PWR_ANLG1: |
| 410 | case RT5677_PWR_ANLG2: |
| 411 | case RT5677_PWR_DSP1: |
| 412 | case RT5677_PWR_DSP_ST: |
| 413 | case RT5677_PWR_DSP2: |
| 414 | case RT5677_ADC_DAC_HPF_CTRL1: |
| 415 | case RT5677_PRIV_INDEX: |
| 416 | case RT5677_PRIV_DATA: |
| 417 | case RT5677_I2S4_SDP: |
| 418 | case RT5677_I2S1_SDP: |
| 419 | case RT5677_I2S2_SDP: |
| 420 | case RT5677_I2S3_SDP: |
| 421 | case RT5677_CLK_TREE_CTRL1: |
| 422 | case RT5677_CLK_TREE_CTRL2: |
| 423 | case RT5677_CLK_TREE_CTRL3: |
| 424 | case RT5677_PLL1_CTRL1: |
| 425 | case RT5677_PLL1_CTRL2: |
| 426 | case RT5677_PLL2_CTRL1: |
| 427 | case RT5677_PLL2_CTRL2: |
| 428 | case RT5677_GLB_CLK1: |
| 429 | case RT5677_GLB_CLK2: |
| 430 | case RT5677_ASRC_1: |
| 431 | case RT5677_ASRC_2: |
| 432 | case RT5677_ASRC_3: |
| 433 | case RT5677_ASRC_4: |
| 434 | case RT5677_ASRC_5: |
| 435 | case RT5677_ASRC_6: |
| 436 | case RT5677_ASRC_7: |
| 437 | case RT5677_ASRC_8: |
| 438 | case RT5677_ASRC_9: |
| 439 | case RT5677_ASRC_10: |
| 440 | case RT5677_ASRC_11: |
| 441 | case RT5677_ASRC_12: |
| 442 | case RT5677_ASRC_13: |
| 443 | case RT5677_ASRC_14: |
| 444 | case RT5677_ASRC_15: |
| 445 | case RT5677_ASRC_16: |
| 446 | case RT5677_ASRC_17: |
| 447 | case RT5677_ASRC_18: |
| 448 | case RT5677_ASRC_19: |
| 449 | case RT5677_ASRC_20: |
| 450 | case RT5677_ASRC_21: |
| 451 | case RT5677_ASRC_22: |
| 452 | case RT5677_ASRC_23: |
| 453 | case RT5677_VAD_CTRL1: |
| 454 | case RT5677_VAD_CTRL2: |
| 455 | case RT5677_VAD_CTRL3: |
| 456 | case RT5677_VAD_CTRL4: |
| 457 | case RT5677_VAD_CTRL5: |
| 458 | case RT5677_DSP_INB_CTRL1: |
| 459 | case RT5677_DSP_INB_CTRL2: |
| 460 | case RT5677_DSP_IN_OUTB_CTRL: |
| 461 | case RT5677_DSP_OUTB0_1_DIG_VOL: |
| 462 | case RT5677_DSP_OUTB2_3_DIG_VOL: |
| 463 | case RT5677_DSP_OUTB4_5_DIG_VOL: |
| 464 | case RT5677_DSP_OUTB6_7_DIG_VOL: |
| 465 | case RT5677_ADC_EQ_CTRL1: |
| 466 | case RT5677_ADC_EQ_CTRL2: |
| 467 | case RT5677_EQ_CTRL1: |
| 468 | case RT5677_EQ_CTRL2: |
| 469 | case RT5677_EQ_CTRL3: |
| 470 | case RT5677_SOFT_VOL_ZERO_CROSS1: |
| 471 | case RT5677_JD_CTRL1: |
| 472 | case RT5677_JD_CTRL2: |
| 473 | case RT5677_JD_CTRL3: |
| 474 | case RT5677_IRQ_CTRL1: |
| 475 | case RT5677_IRQ_CTRL2: |
| 476 | case RT5677_GPIO_ST: |
| 477 | case RT5677_GPIO_CTRL1: |
| 478 | case RT5677_GPIO_CTRL2: |
| 479 | case RT5677_GPIO_CTRL3: |
| 480 | case RT5677_STO1_ADC_HI_FILTER1: |
| 481 | case RT5677_STO1_ADC_HI_FILTER2: |
| 482 | case RT5677_MONO_ADC_HI_FILTER1: |
| 483 | case RT5677_MONO_ADC_HI_FILTER2: |
| 484 | case RT5677_STO2_ADC_HI_FILTER1: |
| 485 | case RT5677_STO2_ADC_HI_FILTER2: |
| 486 | case RT5677_STO3_ADC_HI_FILTER1: |
| 487 | case RT5677_STO3_ADC_HI_FILTER2: |
| 488 | case RT5677_STO4_ADC_HI_FILTER1: |
| 489 | case RT5677_STO4_ADC_HI_FILTER2: |
| 490 | case RT5677_MB_DRC_CTRL1: |
| 491 | case RT5677_DRC1_CTRL1: |
| 492 | case RT5677_DRC1_CTRL2: |
| 493 | case RT5677_DRC1_CTRL3: |
| 494 | case RT5677_DRC1_CTRL4: |
| 495 | case RT5677_DRC1_CTRL5: |
| 496 | case RT5677_DRC1_CTRL6: |
| 497 | case RT5677_DRC2_CTRL1: |
| 498 | case RT5677_DRC2_CTRL2: |
| 499 | case RT5677_DRC2_CTRL3: |
| 500 | case RT5677_DRC2_CTRL4: |
| 501 | case RT5677_DRC2_CTRL5: |
| 502 | case RT5677_DRC2_CTRL6: |
| 503 | case RT5677_DRC1_HL_CTRL1: |
| 504 | case RT5677_DRC1_HL_CTRL2: |
| 505 | case RT5677_DRC2_HL_CTRL1: |
| 506 | case RT5677_DRC2_HL_CTRL2: |
| 507 | case RT5677_DSP_INB1_SRC_CTRL1: |
| 508 | case RT5677_DSP_INB1_SRC_CTRL2: |
| 509 | case RT5677_DSP_INB1_SRC_CTRL3: |
| 510 | case RT5677_DSP_INB1_SRC_CTRL4: |
| 511 | case RT5677_DSP_INB2_SRC_CTRL1: |
| 512 | case RT5677_DSP_INB2_SRC_CTRL2: |
| 513 | case RT5677_DSP_INB2_SRC_CTRL3: |
| 514 | case RT5677_DSP_INB2_SRC_CTRL4: |
| 515 | case RT5677_DSP_INB3_SRC_CTRL1: |
| 516 | case RT5677_DSP_INB3_SRC_CTRL2: |
| 517 | case RT5677_DSP_INB3_SRC_CTRL3: |
| 518 | case RT5677_DSP_INB3_SRC_CTRL4: |
| 519 | case RT5677_DSP_OUTB1_SRC_CTRL1: |
| 520 | case RT5677_DSP_OUTB1_SRC_CTRL2: |
| 521 | case RT5677_DSP_OUTB1_SRC_CTRL3: |
| 522 | case RT5677_DSP_OUTB1_SRC_CTRL4: |
| 523 | case RT5677_DSP_OUTB2_SRC_CTRL1: |
| 524 | case RT5677_DSP_OUTB2_SRC_CTRL2: |
| 525 | case RT5677_DSP_OUTB2_SRC_CTRL3: |
| 526 | case RT5677_DSP_OUTB2_SRC_CTRL4: |
| 527 | case RT5677_DSP_OUTB_0123_MIXER_CTRL: |
| 528 | case RT5677_DSP_OUTB_45_MIXER_CTRL: |
| 529 | case RT5677_DSP_OUTB_67_MIXER_CTRL: |
| 530 | case RT5677_DIG_MISC: |
| 531 | case RT5677_GEN_CTRL1: |
| 532 | case RT5677_GEN_CTRL2: |
| 533 | case RT5677_VENDOR_ID: |
| 534 | case RT5677_VENDOR_ID1: |
| 535 | case RT5677_VENDOR_ID2: |
| 536 | return true; |
| 537 | default: |
| 538 | return false; |
| 539 | } |
| 540 | } |
| 541 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 542 | /** |
| 543 | * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 544 | * @rt5677: Private Data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 545 | * @addr: Address index. |
| 546 | * @value: Address data. |
| 547 | * |
| 548 | * |
| 549 | * Returns 0 for success or negative error code. |
| 550 | */ |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 551 | static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 552 | unsigned int addr, unsigned int value, unsigned int opcode) |
| 553 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 554 | struct snd_soc_codec *codec = rt5677->codec; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 555 | int ret; |
| 556 | |
| 557 | mutex_lock(&rt5677->dsp_cmd_lock); |
| 558 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 559 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, |
| 560 | addr >> 16); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 561 | if (ret < 0) { |
| 562 | dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); |
| 563 | goto err; |
| 564 | } |
| 565 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 566 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 567 | addr & 0xffff); |
| 568 | if (ret < 0) { |
| 569 | dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); |
| 570 | goto err; |
| 571 | } |
| 572 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 573 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 574 | value >> 16); |
| 575 | if (ret < 0) { |
| 576 | dev_err(codec->dev, "Failed to set data msb value: %d\n", ret); |
| 577 | goto err; |
| 578 | } |
| 579 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 580 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 581 | value & 0xffff); |
| 582 | if (ret < 0) { |
| 583 | dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret); |
| 584 | goto err; |
| 585 | } |
| 586 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 587 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, |
| 588 | opcode); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 589 | if (ret < 0) { |
| 590 | dev_err(codec->dev, "Failed to set op code value: %d\n", ret); |
| 591 | goto err; |
| 592 | } |
| 593 | |
| 594 | err: |
| 595 | mutex_unlock(&rt5677->dsp_cmd_lock); |
| 596 | |
| 597 | return ret; |
| 598 | } |
| 599 | |
| 600 | /** |
| 601 | * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 602 | * rt5677: Private Data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 603 | * @addr: Address index. |
| 604 | * @value: Address data. |
| 605 | * |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 606 | * |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 607 | * Returns 0 for success or negative error code. |
| 608 | */ |
| 609 | static int rt5677_dsp_mode_i2c_read_addr( |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 610 | struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 611 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 612 | struct snd_soc_codec *codec = rt5677->codec; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 613 | int ret; |
| 614 | unsigned int msb, lsb; |
| 615 | |
| 616 | mutex_lock(&rt5677->dsp_cmd_lock); |
| 617 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 618 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, |
| 619 | addr >> 16); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 620 | if (ret < 0) { |
| 621 | dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); |
| 622 | goto err; |
| 623 | } |
| 624 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 625 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 626 | addr & 0xffff); |
| 627 | if (ret < 0) { |
| 628 | dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); |
| 629 | goto err; |
| 630 | } |
| 631 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 632 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, |
| 633 | 0x0002); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 634 | if (ret < 0) { |
| 635 | dev_err(codec->dev, "Failed to set op code value: %d\n", ret); |
| 636 | goto err; |
| 637 | } |
| 638 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 639 | regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); |
| 640 | regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 641 | *value = (msb << 16) | lsb; |
| 642 | |
| 643 | err: |
| 644 | mutex_unlock(&rt5677->dsp_cmd_lock); |
| 645 | |
| 646 | return ret; |
| 647 | } |
| 648 | |
| 649 | /** |
| 650 | * rt5677_dsp_mode_i2c_write - Write register on DSP mode. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 651 | * rt5677: Private Data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 652 | * @reg: Register index. |
| 653 | * @value: Register data. |
| 654 | * |
| 655 | * |
| 656 | * Returns 0 for success or negative error code. |
| 657 | */ |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 658 | static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 659 | unsigned int reg, unsigned int value) |
| 660 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 661 | return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 662 | value, 0x0001); |
| 663 | } |
| 664 | |
| 665 | /** |
| 666 | * rt5677_dsp_mode_i2c_read - Read register on DSP mode. |
| 667 | * @codec: SoC audio codec device. |
| 668 | * @reg: Register index. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 669 | * @value: Register data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 670 | * |
| 671 | * |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 672 | * Returns 0 for success or negative error code. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 673 | */ |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 674 | static int rt5677_dsp_mode_i2c_read( |
| 675 | struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 676 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 677 | int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, |
| 678 | value); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 679 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 680 | *value &= 0xffff; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 681 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 682 | return ret; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 683 | } |
| 684 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 685 | static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on) |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 686 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 687 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 688 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 689 | if (on) { |
| 690 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2); |
| 691 | rt5677->is_dsp_mode = true; |
| 692 | } else { |
| 693 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0); |
| 694 | rt5677->is_dsp_mode = false; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 695 | } |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 696 | } |
| 697 | |
| 698 | static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on) |
| 699 | { |
| 700 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 701 | static bool activity; |
| 702 | int ret; |
| 703 | |
| 704 | if (on && !activity) { |
| 705 | activity = true; |
| 706 | |
| 707 | regcache_cache_only(rt5677->regmap, false); |
| 708 | regcache_cache_bypass(rt5677->regmap, true); |
| 709 | |
| 710 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); |
| 711 | regmap_update_bits(rt5677->regmap, |
| 712 | RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00); |
| 713 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
| 714 | RT5677_LDO1_SEL_MASK, 0x0); |
| 715 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 716 | RT5677_PWR_LDO1, RT5677_PWR_LDO1); |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 717 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 718 | RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC); |
| 719 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, |
| 720 | RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK, |
| 721 | RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 722 | regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 723 | regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); |
| 724 | rt5677_set_dsp_mode(codec, true); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 725 | |
| 726 | ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, |
| 727 | codec->dev); |
| 728 | if (ret == 0) { |
| 729 | rt5677_spi_burst_write(0x50000000, rt5677->fw1); |
| 730 | release_firmware(rt5677->fw1); |
| 731 | } |
| 732 | |
| 733 | ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, |
| 734 | codec->dev); |
| 735 | if (ret == 0) { |
| 736 | rt5677_spi_burst_write(0x60000000, rt5677->fw2); |
| 737 | release_firmware(rt5677->fw2); |
| 738 | } |
| 739 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 740 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 741 | |
| 742 | regcache_cache_bypass(rt5677->regmap, false); |
| 743 | regcache_cache_only(rt5677->regmap, true); |
| 744 | } else if (!on && activity) { |
| 745 | activity = false; |
| 746 | |
| 747 | regcache_cache_only(rt5677->regmap, false); |
| 748 | regcache_cache_bypass(rt5677->regmap, true); |
| 749 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 750 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); |
| 751 | rt5677_set_dsp_mode(codec, false); |
| 752 | regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 753 | |
| 754 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); |
| 755 | |
| 756 | regcache_cache_bypass(rt5677->regmap, false); |
| 757 | regcache_mark_dirty(rt5677->regmap); |
| 758 | regcache_sync(rt5677->regmap); |
| 759 | } |
| 760 | |
| 761 | return 0; |
| 762 | } |
| 763 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 764 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); |
| 765 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); |
| 766 | static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); |
| 767 | static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); |
| 768 | static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 769 | static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 770 | |
| 771 | /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ |
| 772 | static unsigned int bst_tlv[] = { |
| 773 | TLV_DB_RANGE_HEAD(7), |
| 774 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
| 775 | 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), |
| 776 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), |
| 777 | 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), |
| 778 | 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), |
| 779 | 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), |
| 780 | 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0), |
| 781 | }; |
| 782 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 783 | static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, |
| 784 | struct snd_ctl_elem_value *ucontrol) |
| 785 | { |
| 786 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 787 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 788 | |
| 789 | ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; |
| 790 | |
| 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, |
| 795 | struct snd_ctl_elem_value *ucontrol) |
| 796 | { |
| 797 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 798 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 799 | |
| 800 | rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0]; |
| 801 | |
| 802 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) |
| 803 | rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en); |
| 804 | |
| 805 | return 0; |
| 806 | } |
| 807 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 808 | static const struct snd_kcontrol_new rt5677_snd_controls[] = { |
| 809 | /* OUTPUT Control */ |
| 810 | SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, |
| 811 | RT5677_LOUT1_L_MUTE_SFT, 1, 1), |
| 812 | SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, |
| 813 | RT5677_LOUT2_L_MUTE_SFT, 1, 1), |
| 814 | SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, |
| 815 | RT5677_LOUT3_L_MUTE_SFT, 1, 1), |
| 816 | |
| 817 | /* DAC Digital Volume */ |
| 818 | SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, |
| 819 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), |
| 820 | SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, |
| 821 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), |
| 822 | SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, |
| 823 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), |
| 824 | SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, |
| 825 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), |
| 826 | |
| 827 | /* IN1/IN2 Control */ |
| 828 | SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), |
| 829 | SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), |
| 830 | |
| 831 | /* ADC Digital Volume Control */ |
| 832 | SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, |
| 833 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 834 | SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, |
| 835 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 836 | SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, |
| 837 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 838 | SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, |
| 839 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 840 | SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, |
| 841 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 842 | |
| 843 | SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, |
| 844 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, |
| 845 | adc_vol_tlv), |
| 846 | SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, |
| 847 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, |
| 848 | adc_vol_tlv), |
| 849 | SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, |
| 850 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, |
| 851 | adc_vol_tlv), |
| 852 | SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, |
| 853 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, |
| 854 | adc_vol_tlv), |
| 855 | SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, |
| 856 | RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0, |
| 857 | adc_vol_tlv), |
| 858 | |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 859 | /* Sidetone Control */ |
| 860 | SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, |
| 861 | RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), |
| 862 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 863 | /* ADC Boost Volume Control */ |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 864 | SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 865 | RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, |
| 866 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 867 | SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 868 | RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, |
| 869 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 870 | SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 871 | RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, |
| 872 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 873 | SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 874 | RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, |
| 875 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 876 | SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 877 | RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, |
| 878 | adc_bst_tlv), |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 879 | |
| 880 | SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, |
| 881 | rt5677_dsp_vad_get, rt5677_dsp_vad_put), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 882 | }; |
| 883 | |
| 884 | /** |
| 885 | * set_dmic_clk - Set parameter of dmic. |
| 886 | * |
| 887 | * @w: DAPM widget. |
| 888 | * @kcontrol: The kcontrol of this widget. |
| 889 | * @event: Event id. |
| 890 | * |
| 891 | * Choose dmic clock between 1MHz and 3MHz. |
| 892 | * It is better for clock to approximate 3MHz. |
| 893 | */ |
| 894 | static int set_dmic_clk(struct snd_soc_dapm_widget *w, |
| 895 | struct snd_kcontrol *kcontrol, int event) |
| 896 | { |
| 897 | struct snd_soc_codec *codec = w->codec; |
| 898 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Axel Lin | 9a53581 | 2014-06-03 10:58:58 +0800 | [diff] [blame] | 899 | int idx = rl6231_calc_dmic_clk(rt5677->sysclk); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 900 | |
| 901 | if (idx < 0) |
| 902 | dev_err(codec->dev, "Failed to set DMIC clock\n"); |
| 903 | else |
| 904 | regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, |
| 905 | RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); |
| 906 | return idx; |
| 907 | } |
| 908 | |
| 909 | static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, |
| 910 | struct snd_soc_dapm_widget *sink) |
| 911 | { |
| 912 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec); |
| 913 | unsigned int val; |
| 914 | |
| 915 | regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); |
| 916 | val &= RT5677_SCLK_SRC_MASK; |
| 917 | if (val == RT5677_SCLK_SRC_PLL1) |
| 918 | return 1; |
| 919 | else |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | /* Digital Mixer */ |
| 924 | static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { |
| 925 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, |
| 926 | RT5677_M_STO1_ADC_L1_SFT, 1, 1), |
| 927 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, |
| 928 | RT5677_M_STO1_ADC_L2_SFT, 1, 1), |
| 929 | }; |
| 930 | |
| 931 | static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { |
| 932 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, |
| 933 | RT5677_M_STO1_ADC_R1_SFT, 1, 1), |
| 934 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, |
| 935 | RT5677_M_STO1_ADC_R2_SFT, 1, 1), |
| 936 | }; |
| 937 | |
| 938 | static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { |
| 939 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, |
| 940 | RT5677_M_STO2_ADC_L1_SFT, 1, 1), |
| 941 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, |
| 942 | RT5677_M_STO2_ADC_L2_SFT, 1, 1), |
| 943 | }; |
| 944 | |
| 945 | static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { |
| 946 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, |
| 947 | RT5677_M_STO2_ADC_R1_SFT, 1, 1), |
| 948 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, |
| 949 | RT5677_M_STO2_ADC_R2_SFT, 1, 1), |
| 950 | }; |
| 951 | |
| 952 | static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { |
| 953 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, |
| 954 | RT5677_M_STO3_ADC_L1_SFT, 1, 1), |
| 955 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, |
| 956 | RT5677_M_STO3_ADC_L2_SFT, 1, 1), |
| 957 | }; |
| 958 | |
| 959 | static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { |
| 960 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, |
| 961 | RT5677_M_STO3_ADC_R1_SFT, 1, 1), |
| 962 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, |
| 963 | RT5677_M_STO3_ADC_R2_SFT, 1, 1), |
| 964 | }; |
| 965 | |
| 966 | static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { |
| 967 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, |
| 968 | RT5677_M_STO4_ADC_L1_SFT, 1, 1), |
| 969 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, |
| 970 | RT5677_M_STO4_ADC_L2_SFT, 1, 1), |
| 971 | }; |
| 972 | |
| 973 | static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { |
| 974 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, |
| 975 | RT5677_M_STO4_ADC_R1_SFT, 1, 1), |
| 976 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, |
| 977 | RT5677_M_STO4_ADC_R2_SFT, 1, 1), |
| 978 | }; |
| 979 | |
| 980 | static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { |
| 981 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, |
| 982 | RT5677_M_MONO_ADC_L1_SFT, 1, 1), |
| 983 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, |
| 984 | RT5677_M_MONO_ADC_L2_SFT, 1, 1), |
| 985 | }; |
| 986 | |
| 987 | static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { |
| 988 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, |
| 989 | RT5677_M_MONO_ADC_R1_SFT, 1, 1), |
| 990 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, |
| 991 | RT5677_M_MONO_ADC_R2_SFT, 1, 1), |
| 992 | }; |
| 993 | |
| 994 | static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { |
| 995 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 996 | RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), |
| 997 | SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 998 | RT5677_M_DAC1_L_SFT, 1, 1), |
| 999 | }; |
| 1000 | |
| 1001 | static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { |
| 1002 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1003 | RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), |
| 1004 | SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1005 | RT5677_M_DAC1_R_SFT, 1, 1), |
| 1006 | }; |
| 1007 | |
| 1008 | static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { |
| 1009 | SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER, |
| 1010 | RT5677_M_ST_DAC1_L_SFT, 1, 1), |
| 1011 | SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, |
| 1012 | RT5677_M_DAC1_L_STO_L_SFT, 1, 1), |
| 1013 | SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, |
| 1014 | RT5677_M_DAC2_L_STO_L_SFT, 1, 1), |
| 1015 | SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, |
| 1016 | RT5677_M_DAC1_R_STO_L_SFT, 1, 1), |
| 1017 | }; |
| 1018 | |
| 1019 | static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { |
| 1020 | SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER, |
| 1021 | RT5677_M_ST_DAC1_R_SFT, 1, 1), |
| 1022 | SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, |
| 1023 | RT5677_M_DAC1_R_STO_R_SFT, 1, 1), |
| 1024 | SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, |
| 1025 | RT5677_M_DAC2_R_STO_R_SFT, 1, 1), |
| 1026 | SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, |
| 1027 | RT5677_M_DAC1_L_STO_R_SFT, 1, 1), |
| 1028 | }; |
| 1029 | |
| 1030 | static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { |
| 1031 | SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER, |
| 1032 | RT5677_M_ST_DAC2_L_SFT, 1, 1), |
| 1033 | SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, |
| 1034 | RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), |
| 1035 | SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, |
| 1036 | RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), |
| 1037 | SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, |
| 1038 | RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), |
| 1039 | }; |
| 1040 | |
| 1041 | static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { |
| 1042 | SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER, |
| 1043 | RT5677_M_ST_DAC2_R_SFT, 1, 1), |
| 1044 | SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, |
| 1045 | RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), |
| 1046 | SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, |
| 1047 | RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), |
| 1048 | SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, |
| 1049 | RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), |
| 1050 | }; |
| 1051 | |
| 1052 | static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { |
| 1053 | SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, |
| 1054 | RT5677_M_STO_L_DD1_L_SFT, 1, 1), |
| 1055 | SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, |
| 1056 | RT5677_M_MONO_L_DD1_L_SFT, 1, 1), |
| 1057 | SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, |
| 1058 | RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), |
| 1059 | SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, |
| 1060 | RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), |
| 1061 | }; |
| 1062 | |
| 1063 | static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { |
| 1064 | SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, |
| 1065 | RT5677_M_STO_R_DD1_R_SFT, 1, 1), |
| 1066 | SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, |
| 1067 | RT5677_M_MONO_R_DD1_R_SFT, 1, 1), |
| 1068 | SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, |
| 1069 | RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), |
| 1070 | SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, |
| 1071 | RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), |
| 1072 | }; |
| 1073 | |
| 1074 | static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { |
| 1075 | SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, |
| 1076 | RT5677_M_STO_L_DD2_L_SFT, 1, 1), |
| 1077 | SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, |
| 1078 | RT5677_M_MONO_L_DD2_L_SFT, 1, 1), |
| 1079 | SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, |
| 1080 | RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), |
| 1081 | SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, |
| 1082 | RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), |
| 1083 | }; |
| 1084 | |
| 1085 | static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { |
| 1086 | SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, |
| 1087 | RT5677_M_STO_R_DD2_R_SFT, 1, 1), |
| 1088 | SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, |
| 1089 | RT5677_M_MONO_R_DD2_R_SFT, 1, 1), |
| 1090 | SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, |
| 1091 | RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), |
| 1092 | SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, |
| 1093 | RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), |
| 1094 | }; |
| 1095 | |
| 1096 | static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { |
| 1097 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1098 | RT5677_DSP_IB_01_H_SFT, 1, 1), |
| 1099 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1100 | RT5677_DSP_IB_23_H_SFT, 1, 1), |
| 1101 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1102 | RT5677_DSP_IB_45_H_SFT, 1, 1), |
| 1103 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1104 | RT5677_DSP_IB_6_H_SFT, 1, 1), |
| 1105 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1106 | RT5677_DSP_IB_7_H_SFT, 1, 1), |
| 1107 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1108 | RT5677_DSP_IB_8_H_SFT, 1, 1), |
| 1109 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1110 | RT5677_DSP_IB_9_H_SFT, 1, 1), |
| 1111 | }; |
| 1112 | |
| 1113 | static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { |
| 1114 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1115 | RT5677_DSP_IB_01_L_SFT, 1, 1), |
| 1116 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1117 | RT5677_DSP_IB_23_L_SFT, 1, 1), |
| 1118 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1119 | RT5677_DSP_IB_45_L_SFT, 1, 1), |
| 1120 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1121 | RT5677_DSP_IB_6_L_SFT, 1, 1), |
| 1122 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1123 | RT5677_DSP_IB_7_L_SFT, 1, 1), |
| 1124 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1125 | RT5677_DSP_IB_8_L_SFT, 1, 1), |
| 1126 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1127 | RT5677_DSP_IB_9_L_SFT, 1, 1), |
| 1128 | }; |
| 1129 | |
| 1130 | static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { |
| 1131 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1132 | RT5677_DSP_IB_01_H_SFT, 1, 1), |
| 1133 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1134 | RT5677_DSP_IB_23_H_SFT, 1, 1), |
| 1135 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1136 | RT5677_DSP_IB_45_H_SFT, 1, 1), |
| 1137 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1138 | RT5677_DSP_IB_6_H_SFT, 1, 1), |
| 1139 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1140 | RT5677_DSP_IB_7_H_SFT, 1, 1), |
| 1141 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1142 | RT5677_DSP_IB_8_H_SFT, 1, 1), |
| 1143 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1144 | RT5677_DSP_IB_9_H_SFT, 1, 1), |
| 1145 | }; |
| 1146 | |
| 1147 | static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { |
| 1148 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1149 | RT5677_DSP_IB_01_L_SFT, 1, 1), |
| 1150 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1151 | RT5677_DSP_IB_23_L_SFT, 1, 1), |
| 1152 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1153 | RT5677_DSP_IB_45_L_SFT, 1, 1), |
| 1154 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1155 | RT5677_DSP_IB_6_L_SFT, 1, 1), |
| 1156 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1157 | RT5677_DSP_IB_7_L_SFT, 1, 1), |
| 1158 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1159 | RT5677_DSP_IB_8_L_SFT, 1, 1), |
| 1160 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1161 | RT5677_DSP_IB_9_L_SFT, 1, 1), |
| 1162 | }; |
| 1163 | |
| 1164 | static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { |
| 1165 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1166 | RT5677_DSP_IB_01_H_SFT, 1, 1), |
| 1167 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1168 | RT5677_DSP_IB_23_H_SFT, 1, 1), |
| 1169 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1170 | RT5677_DSP_IB_45_H_SFT, 1, 1), |
| 1171 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1172 | RT5677_DSP_IB_6_H_SFT, 1, 1), |
| 1173 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1174 | RT5677_DSP_IB_7_H_SFT, 1, 1), |
| 1175 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1176 | RT5677_DSP_IB_8_H_SFT, 1, 1), |
| 1177 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1178 | RT5677_DSP_IB_9_H_SFT, 1, 1), |
| 1179 | }; |
| 1180 | |
| 1181 | static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { |
| 1182 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1183 | RT5677_DSP_IB_01_L_SFT, 1, 1), |
| 1184 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1185 | RT5677_DSP_IB_23_L_SFT, 1, 1), |
| 1186 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1187 | RT5677_DSP_IB_45_L_SFT, 1, 1), |
| 1188 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1189 | RT5677_DSP_IB_6_L_SFT, 1, 1), |
| 1190 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1191 | RT5677_DSP_IB_7_L_SFT, 1, 1), |
| 1192 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1193 | RT5677_DSP_IB_8_L_SFT, 1, 1), |
| 1194 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1195 | RT5677_DSP_IB_9_L_SFT, 1, 1), |
| 1196 | }; |
| 1197 | |
| 1198 | |
| 1199 | /* Mux */ |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1200 | /* DAC1 L/R Source */ /* MX-29 [10:8] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1201 | static const char * const rt5677_dac1_src[] = { |
| 1202 | "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", |
| 1203 | "OB 01" |
| 1204 | }; |
| 1205 | |
| 1206 | static SOC_ENUM_SINGLE_DECL( |
| 1207 | rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1208 | RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); |
| 1209 | |
| 1210 | static const struct snd_kcontrol_new rt5677_dac1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1211 | SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1212 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1213 | /* ADDA1 L/R Source */ /* MX-29 [1:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1214 | static const char * const rt5677_adda1_src[] = { |
| 1215 | "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", |
| 1216 | }; |
| 1217 | |
| 1218 | static SOC_ENUM_SINGLE_DECL( |
| 1219 | rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1220 | RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); |
| 1221 | |
| 1222 | static const struct snd_kcontrol_new rt5677_adda1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1223 | SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1224 | |
| 1225 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1226 | /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1227 | static const char * const rt5677_dac2l_src[] = { |
| 1228 | "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", |
| 1229 | "OB 2", |
| 1230 | }; |
| 1231 | |
| 1232 | static SOC_ENUM_SINGLE_DECL( |
| 1233 | rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, |
| 1234 | RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); |
| 1235 | |
| 1236 | static const struct snd_kcontrol_new rt5677_dac2_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1237 | SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1238 | |
| 1239 | static const char * const rt5677_dac2r_src[] = { |
| 1240 | "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", |
| 1241 | "OB 3", "Haptic Generator", "VAD ADC" |
| 1242 | }; |
| 1243 | |
| 1244 | static SOC_ENUM_SINGLE_DECL( |
| 1245 | rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, |
| 1246 | RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); |
| 1247 | |
| 1248 | static const struct snd_kcontrol_new rt5677_dac2_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1249 | SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1250 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1251 | /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1252 | static const char * const rt5677_dac3l_src[] = { |
| 1253 | "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", |
| 1254 | "SLB DAC 4", "OB 4" |
| 1255 | }; |
| 1256 | |
| 1257 | static SOC_ENUM_SINGLE_DECL( |
| 1258 | rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1259 | RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); |
| 1260 | |
| 1261 | static const struct snd_kcontrol_new rt5677_dac3_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1262 | SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1263 | |
| 1264 | static const char * const rt5677_dac3r_src[] = { |
| 1265 | "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", |
| 1266 | "SLB DAC 5", "OB 5" |
| 1267 | }; |
| 1268 | |
| 1269 | static SOC_ENUM_SINGLE_DECL( |
| 1270 | rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1271 | RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); |
| 1272 | |
| 1273 | static const struct snd_kcontrol_new rt5677_dac3_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1274 | SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1275 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1276 | /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1277 | static const char * const rt5677_dac4l_src[] = { |
| 1278 | "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", |
| 1279 | "SLB DAC 6", "OB 6" |
| 1280 | }; |
| 1281 | |
| 1282 | static SOC_ENUM_SINGLE_DECL( |
| 1283 | rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1284 | RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); |
| 1285 | |
| 1286 | static const struct snd_kcontrol_new rt5677_dac4_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1287 | SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1288 | |
| 1289 | static const char * const rt5677_dac4r_src[] = { |
| 1290 | "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", |
| 1291 | "SLB DAC 7", "OB 7" |
| 1292 | }; |
| 1293 | |
| 1294 | static SOC_ENUM_SINGLE_DECL( |
| 1295 | rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1296 | RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); |
| 1297 | |
| 1298 | static const struct snd_kcontrol_new rt5677_dac4_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1299 | SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1300 | |
| 1301 | /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ |
| 1302 | static const char * const rt5677_iob_bypass_src[] = { |
| 1303 | "Bypass", "Pass SRC" |
| 1304 | }; |
| 1305 | |
| 1306 | static SOC_ENUM_SINGLE_DECL( |
| 1307 | rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1308 | RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); |
| 1309 | |
| 1310 | static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1311 | SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1312 | |
| 1313 | static SOC_ENUM_SINGLE_DECL( |
| 1314 | rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1315 | RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); |
| 1316 | |
| 1317 | static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1318 | SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1319 | |
| 1320 | static SOC_ENUM_SINGLE_DECL( |
| 1321 | rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1322 | RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); |
| 1323 | |
| 1324 | static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1325 | SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1326 | |
| 1327 | static SOC_ENUM_SINGLE_DECL( |
| 1328 | rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1329 | RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); |
| 1330 | |
| 1331 | static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1332 | SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1333 | |
| 1334 | static SOC_ENUM_SINGLE_DECL( |
| 1335 | rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1336 | RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); |
| 1337 | |
| 1338 | static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1339 | SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1340 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1341 | /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1342 | static const char * const rt5677_stereo_adc2_src[] = { |
| 1343 | "DD MIX1", "DMIC", "Stereo DAC MIX" |
| 1344 | }; |
| 1345 | |
| 1346 | static SOC_ENUM_SINGLE_DECL( |
| 1347 | rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, |
| 1348 | RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); |
| 1349 | |
| 1350 | static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1351 | SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1352 | |
| 1353 | static SOC_ENUM_SINGLE_DECL( |
| 1354 | rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, |
| 1355 | RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); |
| 1356 | |
| 1357 | static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1358 | SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1359 | |
| 1360 | static SOC_ENUM_SINGLE_DECL( |
| 1361 | rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, |
| 1362 | RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); |
| 1363 | |
| 1364 | static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1365 | SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1366 | |
| 1367 | /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ |
| 1368 | static const char * const rt5677_dmic_src[] = { |
| 1369 | "DMIC1", "DMIC2", "DMIC3", "DMIC4" |
| 1370 | }; |
| 1371 | |
| 1372 | static SOC_ENUM_SINGLE_DECL( |
| 1373 | rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, |
| 1374 | RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); |
| 1375 | |
| 1376 | static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1377 | SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1378 | |
| 1379 | static SOC_ENUM_SINGLE_DECL( |
| 1380 | rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, |
| 1381 | RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); |
| 1382 | |
| 1383 | static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1384 | SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1385 | |
| 1386 | static SOC_ENUM_SINGLE_DECL( |
| 1387 | rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, |
| 1388 | RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); |
| 1389 | |
| 1390 | static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1391 | SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1392 | |
| 1393 | static SOC_ENUM_SINGLE_DECL( |
| 1394 | rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, |
| 1395 | RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); |
| 1396 | |
| 1397 | static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1398 | SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1399 | |
| 1400 | static SOC_ENUM_SINGLE_DECL( |
| 1401 | rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, |
| 1402 | RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); |
| 1403 | |
| 1404 | static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1405 | SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1406 | |
| 1407 | static SOC_ENUM_SINGLE_DECL( |
| 1408 | rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, |
| 1409 | RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); |
| 1410 | |
| 1411 | static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1412 | SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1413 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1414 | /* Stereo2 ADC Source */ /* MX-26 [0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1415 | static const char * const rt5677_stereo2_adc_lr_src[] = { |
| 1416 | "L", "LR" |
| 1417 | }; |
| 1418 | |
| 1419 | static SOC_ENUM_SINGLE_DECL( |
| 1420 | rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, |
| 1421 | RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); |
| 1422 | |
| 1423 | static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1424 | SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1425 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1426 | /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1427 | static const char * const rt5677_stereo_adc1_src[] = { |
| 1428 | "DD MIX1", "ADC1/2", "Stereo DAC MIX" |
| 1429 | }; |
| 1430 | |
| 1431 | static SOC_ENUM_SINGLE_DECL( |
| 1432 | rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, |
| 1433 | RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); |
| 1434 | |
| 1435 | static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1436 | SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1437 | |
| 1438 | static SOC_ENUM_SINGLE_DECL( |
| 1439 | rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, |
| 1440 | RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); |
| 1441 | |
| 1442 | static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1443 | SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1444 | |
| 1445 | static SOC_ENUM_SINGLE_DECL( |
| 1446 | rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, |
| 1447 | RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); |
| 1448 | |
| 1449 | static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1450 | SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1451 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1452 | /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1453 | static const char * const rt5677_mono_adc2_l_src[] = { |
| 1454 | "DD MIX1L", "DMIC", "MONO DAC MIXL" |
| 1455 | }; |
| 1456 | |
| 1457 | static SOC_ENUM_SINGLE_DECL( |
| 1458 | rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, |
| 1459 | RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); |
| 1460 | |
| 1461 | static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1462 | SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1463 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1464 | /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1465 | static const char * const rt5677_mono_adc1_l_src[] = { |
| 1466 | "DD MIX1L", "ADC1", "MONO DAC MIXL" |
| 1467 | }; |
| 1468 | |
| 1469 | static SOC_ENUM_SINGLE_DECL( |
| 1470 | rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, |
| 1471 | RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); |
| 1472 | |
| 1473 | static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1474 | SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1475 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1476 | /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1477 | static const char * const rt5677_mono_adc2_r_src[] = { |
| 1478 | "DD MIX1R", "DMIC", "MONO DAC MIXR" |
| 1479 | }; |
| 1480 | |
| 1481 | static SOC_ENUM_SINGLE_DECL( |
| 1482 | rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, |
| 1483 | RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); |
| 1484 | |
| 1485 | static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1486 | SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1487 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1488 | /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1489 | static const char * const rt5677_mono_adc1_r_src[] = { |
| 1490 | "DD MIX1R", "ADC2", "MONO DAC MIXR" |
| 1491 | }; |
| 1492 | |
| 1493 | static SOC_ENUM_SINGLE_DECL( |
| 1494 | rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, |
| 1495 | RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); |
| 1496 | |
| 1497 | static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1498 | SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1499 | |
| 1500 | /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ |
| 1501 | static const char * const rt5677_stereo4_adc2_src[] = { |
| 1502 | "DD MIX1", "DMIC", "DD MIX2" |
| 1503 | }; |
| 1504 | |
| 1505 | static SOC_ENUM_SINGLE_DECL( |
| 1506 | rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, |
| 1507 | RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); |
| 1508 | |
| 1509 | static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1510 | SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1511 | |
| 1512 | |
| 1513 | /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ |
| 1514 | static const char * const rt5677_stereo4_adc1_src[] = { |
| 1515 | "DD MIX1", "ADC1/2", "DD MIX2" |
| 1516 | }; |
| 1517 | |
| 1518 | static SOC_ENUM_SINGLE_DECL( |
| 1519 | rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, |
| 1520 | RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); |
| 1521 | |
| 1522 | static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1523 | SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1524 | |
| 1525 | /* InBound0/1 Source */ /* MX-A3 [14:12] */ |
| 1526 | static const char * const rt5677_inbound01_src[] = { |
| 1527 | "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", |
| 1528 | "VAD ADC/DAC1 FS" |
| 1529 | }; |
| 1530 | |
| 1531 | static SOC_ENUM_SINGLE_DECL( |
| 1532 | rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, |
| 1533 | RT5677_IB01_SRC_SFT, rt5677_inbound01_src); |
| 1534 | |
| 1535 | static const struct snd_kcontrol_new rt5677_ib01_src_mux = |
| 1536 | SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); |
| 1537 | |
| 1538 | /* InBound2/3 Source */ /* MX-A3 [10:8] */ |
| 1539 | static const char * const rt5677_inbound23_src[] = { |
| 1540 | "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", |
| 1541 | "DAC1 FS", "IF4 DAC" |
| 1542 | }; |
| 1543 | |
| 1544 | static SOC_ENUM_SINGLE_DECL( |
| 1545 | rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, |
| 1546 | RT5677_IB23_SRC_SFT, rt5677_inbound23_src); |
| 1547 | |
| 1548 | static const struct snd_kcontrol_new rt5677_ib23_src_mux = |
| 1549 | SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); |
| 1550 | |
| 1551 | /* InBound4/5 Source */ /* MX-A3 [6:4] */ |
| 1552 | static const char * const rt5677_inbound45_src[] = { |
| 1553 | "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", |
| 1554 | "IF3 DAC" |
| 1555 | }; |
| 1556 | |
| 1557 | static SOC_ENUM_SINGLE_DECL( |
| 1558 | rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, |
| 1559 | RT5677_IB45_SRC_SFT, rt5677_inbound45_src); |
| 1560 | |
| 1561 | static const struct snd_kcontrol_new rt5677_ib45_src_mux = |
| 1562 | SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); |
| 1563 | |
| 1564 | /* InBound6 Source */ /* MX-A3 [2:0] */ |
| 1565 | static const char * const rt5677_inbound6_src[] = { |
| 1566 | "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", |
| 1567 | "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" |
| 1568 | }; |
| 1569 | |
| 1570 | static SOC_ENUM_SINGLE_DECL( |
| 1571 | rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, |
| 1572 | RT5677_IB6_SRC_SFT, rt5677_inbound6_src); |
| 1573 | |
| 1574 | static const struct snd_kcontrol_new rt5677_ib6_src_mux = |
| 1575 | SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); |
| 1576 | |
| 1577 | /* InBound7 Source */ /* MX-A4 [14:12] */ |
| 1578 | static const char * const rt5677_inbound7_src[] = { |
| 1579 | "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", |
| 1580 | "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" |
| 1581 | }; |
| 1582 | |
| 1583 | static SOC_ENUM_SINGLE_DECL( |
| 1584 | rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, |
| 1585 | RT5677_IB7_SRC_SFT, rt5677_inbound7_src); |
| 1586 | |
| 1587 | static const struct snd_kcontrol_new rt5677_ib7_src_mux = |
| 1588 | SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); |
| 1589 | |
| 1590 | /* InBound8 Source */ /* MX-A4 [10:8] */ |
| 1591 | static const char * const rt5677_inbound8_src[] = { |
| 1592 | "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", |
| 1593 | "MONO ADC MIX L", "DACL1 FS" |
| 1594 | }; |
| 1595 | |
| 1596 | static SOC_ENUM_SINGLE_DECL( |
| 1597 | rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, |
| 1598 | RT5677_IB8_SRC_SFT, rt5677_inbound8_src); |
| 1599 | |
| 1600 | static const struct snd_kcontrol_new rt5677_ib8_src_mux = |
| 1601 | SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); |
| 1602 | |
| 1603 | /* InBound9 Source */ /* MX-A4 [6:4] */ |
| 1604 | static const char * const rt5677_inbound9_src[] = { |
| 1605 | "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", |
| 1606 | "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" |
| 1607 | }; |
| 1608 | |
| 1609 | static SOC_ENUM_SINGLE_DECL( |
| 1610 | rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, |
| 1611 | RT5677_IB9_SRC_SFT, rt5677_inbound9_src); |
| 1612 | |
| 1613 | static const struct snd_kcontrol_new rt5677_ib9_src_mux = |
| 1614 | SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); |
| 1615 | |
| 1616 | /* VAD Source */ /* MX-9F [6:4] */ |
| 1617 | static const char * const rt5677_vad_src[] = { |
| 1618 | "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", |
| 1619 | "STO3 ADC MIX L" |
| 1620 | }; |
| 1621 | |
| 1622 | static SOC_ENUM_SINGLE_DECL( |
| 1623 | rt5677_vad_enum, RT5677_VAD_CTRL4, |
| 1624 | RT5677_VAD_SRC_SFT, rt5677_vad_src); |
| 1625 | |
| 1626 | static const struct snd_kcontrol_new rt5677_vad_src_mux = |
| 1627 | SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); |
| 1628 | |
| 1629 | /* Sidetone Source */ /* MX-13 [11:9] */ |
| 1630 | static const char * const rt5677_sidetone_src[] = { |
| 1631 | "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" |
| 1632 | }; |
| 1633 | |
| 1634 | static SOC_ENUM_SINGLE_DECL( |
| 1635 | rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, |
| 1636 | RT5677_ST_SEL_SFT, rt5677_sidetone_src); |
| 1637 | |
| 1638 | static const struct snd_kcontrol_new rt5677_sidetone_mux = |
| 1639 | SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); |
| 1640 | |
| 1641 | /* DAC1/2 Source */ /* MX-15 [1:0] */ |
| 1642 | static const char * const rt5677_dac12_src[] = { |
| 1643 | "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" |
| 1644 | }; |
| 1645 | |
| 1646 | static SOC_ENUM_SINGLE_DECL( |
| 1647 | rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, |
| 1648 | RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); |
| 1649 | |
| 1650 | static const struct snd_kcontrol_new rt5677_dac12_mux = |
| 1651 | SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); |
| 1652 | |
| 1653 | /* DAC3 Source */ /* MX-15 [5:4] */ |
| 1654 | static const char * const rt5677_dac3_src[] = { |
| 1655 | "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" |
| 1656 | }; |
| 1657 | |
| 1658 | static SOC_ENUM_SINGLE_DECL( |
| 1659 | rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, |
| 1660 | RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); |
| 1661 | |
| 1662 | static const struct snd_kcontrol_new rt5677_dac3_mux = |
| 1663 | SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); |
| 1664 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1665 | /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1666 | static const char * const rt5677_pdm_src[] = { |
| 1667 | "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" |
| 1668 | }; |
| 1669 | |
| 1670 | static SOC_ENUM_SINGLE_DECL( |
| 1671 | rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, |
| 1672 | RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); |
| 1673 | |
| 1674 | static const struct snd_kcontrol_new rt5677_pdm1_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1675 | SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1676 | |
| 1677 | static SOC_ENUM_SINGLE_DECL( |
| 1678 | rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, |
| 1679 | RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); |
| 1680 | |
| 1681 | static const struct snd_kcontrol_new rt5677_pdm2_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1682 | SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1683 | |
| 1684 | static SOC_ENUM_SINGLE_DECL( |
| 1685 | rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, |
| 1686 | RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); |
| 1687 | |
| 1688 | static const struct snd_kcontrol_new rt5677_pdm1_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1689 | SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1690 | |
| 1691 | static SOC_ENUM_SINGLE_DECL( |
| 1692 | rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, |
| 1693 | RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); |
| 1694 | |
| 1695 | static const struct snd_kcontrol_new rt5677_pdm2_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1696 | SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1697 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1698 | /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1699 | static const char * const rt5677_if12_adc1_src[] = { |
| 1700 | "STO1 ADC MIX", "OB01", "VAD ADC" |
| 1701 | }; |
| 1702 | |
| 1703 | static SOC_ENUM_SINGLE_DECL( |
| 1704 | rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, |
| 1705 | RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); |
| 1706 | |
| 1707 | static const struct snd_kcontrol_new rt5677_if1_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1708 | SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1709 | |
| 1710 | static SOC_ENUM_SINGLE_DECL( |
| 1711 | rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, |
| 1712 | RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); |
| 1713 | |
| 1714 | static const struct snd_kcontrol_new rt5677_if2_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1715 | SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1716 | |
| 1717 | static SOC_ENUM_SINGLE_DECL( |
| 1718 | rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, |
| 1719 | RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); |
| 1720 | |
| 1721 | static const struct snd_kcontrol_new rt5677_slb_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1722 | SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1723 | |
| 1724 | /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ |
| 1725 | static const char * const rt5677_if12_adc2_src[] = { |
| 1726 | "STO2 ADC MIX", "OB23" |
| 1727 | }; |
| 1728 | |
| 1729 | static SOC_ENUM_SINGLE_DECL( |
| 1730 | rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, |
| 1731 | RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); |
| 1732 | |
| 1733 | static const struct snd_kcontrol_new rt5677_if1_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1734 | SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1735 | |
| 1736 | static SOC_ENUM_SINGLE_DECL( |
| 1737 | rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, |
| 1738 | RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); |
| 1739 | |
| 1740 | static const struct snd_kcontrol_new rt5677_if2_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1741 | SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1742 | |
| 1743 | static SOC_ENUM_SINGLE_DECL( |
| 1744 | rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, |
| 1745 | RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); |
| 1746 | |
| 1747 | static const struct snd_kcontrol_new rt5677_slb_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1748 | SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1749 | |
| 1750 | /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ |
| 1751 | static const char * const rt5677_if12_adc3_src[] = { |
| 1752 | "STO3 ADC MIX", "MONO ADC MIX", "OB45" |
| 1753 | }; |
| 1754 | |
| 1755 | static SOC_ENUM_SINGLE_DECL( |
| 1756 | rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, |
| 1757 | RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); |
| 1758 | |
| 1759 | static const struct snd_kcontrol_new rt5677_if1_adc3_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1760 | SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1761 | |
| 1762 | static SOC_ENUM_SINGLE_DECL( |
| 1763 | rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, |
| 1764 | RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); |
| 1765 | |
| 1766 | static const struct snd_kcontrol_new rt5677_if2_adc3_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1767 | SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1768 | |
| 1769 | static SOC_ENUM_SINGLE_DECL( |
| 1770 | rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, |
| 1771 | RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); |
| 1772 | |
| 1773 | static const struct snd_kcontrol_new rt5677_slb_adc3_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1774 | SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1775 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1776 | /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1777 | static const char * const rt5677_if12_adc4_src[] = { |
| 1778 | "STO4 ADC MIX", "OB67", "OB01" |
| 1779 | }; |
| 1780 | |
| 1781 | static SOC_ENUM_SINGLE_DECL( |
| 1782 | rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, |
| 1783 | RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); |
| 1784 | |
| 1785 | static const struct snd_kcontrol_new rt5677_if1_adc4_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1786 | SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1787 | |
| 1788 | static SOC_ENUM_SINGLE_DECL( |
| 1789 | rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, |
| 1790 | RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); |
| 1791 | |
| 1792 | static const struct snd_kcontrol_new rt5677_if2_adc4_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1793 | SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1794 | |
| 1795 | static SOC_ENUM_SINGLE_DECL( |
| 1796 | rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, |
| 1797 | RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); |
| 1798 | |
| 1799 | static const struct snd_kcontrol_new rt5677_slb_adc4_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1800 | SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1801 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1802 | /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1803 | static const char * const rt5677_if34_adc_src[] = { |
| 1804 | "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", |
| 1805 | "MONO ADC MIX", "OB01", "OB23", "VAD ADC" |
| 1806 | }; |
| 1807 | |
| 1808 | static SOC_ENUM_SINGLE_DECL( |
| 1809 | rt5677_if3_adc_enum, RT5677_IF3_DATA, |
| 1810 | RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); |
| 1811 | |
| 1812 | static const struct snd_kcontrol_new rt5677_if3_adc_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1813 | SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1814 | |
| 1815 | static SOC_ENUM_SINGLE_DECL( |
| 1816 | rt5677_if4_adc_enum, RT5677_IF4_DATA, |
| 1817 | RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); |
| 1818 | |
| 1819 | static const struct snd_kcontrol_new rt5677_if4_adc_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1820 | SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1821 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 1822 | /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ |
| 1823 | static const char * const rt5677_if12_adc_swap_src[] = { |
| 1824 | "L/R", "R/L", "L/L", "R/R" |
| 1825 | }; |
| 1826 | |
| 1827 | static SOC_ENUM_SINGLE_DECL( |
| 1828 | rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, |
| 1829 | RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1830 | |
| 1831 | static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = |
| 1832 | SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); |
| 1833 | |
| 1834 | static SOC_ENUM_SINGLE_DECL( |
| 1835 | rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, |
| 1836 | RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1837 | |
| 1838 | static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = |
| 1839 | SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); |
| 1840 | |
| 1841 | static SOC_ENUM_SINGLE_DECL( |
| 1842 | rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, |
| 1843 | RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1844 | |
| 1845 | static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = |
| 1846 | SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); |
| 1847 | |
| 1848 | static SOC_ENUM_SINGLE_DECL( |
| 1849 | rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, |
| 1850 | RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1851 | |
| 1852 | static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = |
| 1853 | SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); |
| 1854 | |
| 1855 | static SOC_ENUM_SINGLE_DECL( |
| 1856 | rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, |
| 1857 | RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1858 | |
| 1859 | static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = |
| 1860 | SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); |
| 1861 | |
| 1862 | static SOC_ENUM_SINGLE_DECL( |
| 1863 | rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, |
| 1864 | RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1865 | |
| 1866 | static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = |
| 1867 | SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); |
| 1868 | |
| 1869 | static SOC_ENUM_SINGLE_DECL( |
| 1870 | rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, |
| 1871 | RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1872 | |
| 1873 | static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = |
| 1874 | SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); |
| 1875 | |
| 1876 | static SOC_ENUM_SINGLE_DECL( |
| 1877 | rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, |
| 1878 | RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 1879 | |
| 1880 | static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = |
| 1881 | SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); |
| 1882 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1883 | /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 1884 | static const char * const rt5677_if1_adc_tdm_swap_src[] = { |
| 1885 | "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", |
| 1886 | "3/1/2/4", "3/4/1/2" |
| 1887 | }; |
| 1888 | |
| 1889 | static SOC_ENUM_SINGLE_DECL( |
| 1890 | rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, |
| 1891 | RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); |
| 1892 | |
| 1893 | static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = |
| 1894 | SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); |
| 1895 | |
| 1896 | /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ |
| 1897 | static const char * const rt5677_if2_adc_tdm_swap_src[] = { |
| 1898 | "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", |
| 1899 | "2/3/1/4", "3/4/1/2" |
| 1900 | }; |
| 1901 | |
| 1902 | static SOC_ENUM_SINGLE_DECL( |
| 1903 | rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, |
| 1904 | RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); |
| 1905 | |
| 1906 | static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = |
| 1907 | SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); |
| 1908 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame^] | 1909 | /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] |
| 1910 | MX-3F[14:12][10:8][6:4][2:0] |
| 1911 | MX-43[14:12][10:8][6:4][2:0] |
| 1912 | MX-44[14:12][10:8][6:4][2:0] */ |
| 1913 | static const char * const rt5677_if12_dac_tdm_sel_src[] = { |
| 1914 | "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" |
| 1915 | }; |
| 1916 | |
| 1917 | static SOC_ENUM_SINGLE_DECL( |
| 1918 | rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 1919 | RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1920 | |
| 1921 | static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = |
| 1922 | SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); |
| 1923 | |
| 1924 | static SOC_ENUM_SINGLE_DECL( |
| 1925 | rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 1926 | RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1927 | |
| 1928 | static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = |
| 1929 | SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); |
| 1930 | |
| 1931 | static SOC_ENUM_SINGLE_DECL( |
| 1932 | rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 1933 | RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1934 | |
| 1935 | static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = |
| 1936 | SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); |
| 1937 | |
| 1938 | static SOC_ENUM_SINGLE_DECL( |
| 1939 | rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 1940 | RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1941 | |
| 1942 | static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = |
| 1943 | SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); |
| 1944 | |
| 1945 | static SOC_ENUM_SINGLE_DECL( |
| 1946 | rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 1947 | RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1948 | |
| 1949 | static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = |
| 1950 | SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); |
| 1951 | |
| 1952 | static SOC_ENUM_SINGLE_DECL( |
| 1953 | rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 1954 | RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1955 | |
| 1956 | static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = |
| 1957 | SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); |
| 1958 | |
| 1959 | static SOC_ENUM_SINGLE_DECL( |
| 1960 | rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 1961 | RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1962 | |
| 1963 | static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = |
| 1964 | SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); |
| 1965 | |
| 1966 | static SOC_ENUM_SINGLE_DECL( |
| 1967 | rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 1968 | RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1969 | |
| 1970 | static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = |
| 1971 | SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); |
| 1972 | |
| 1973 | static SOC_ENUM_SINGLE_DECL( |
| 1974 | rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 1975 | RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1976 | |
| 1977 | static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = |
| 1978 | SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); |
| 1979 | |
| 1980 | static SOC_ENUM_SINGLE_DECL( |
| 1981 | rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 1982 | RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1983 | |
| 1984 | static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = |
| 1985 | SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); |
| 1986 | |
| 1987 | static SOC_ENUM_SINGLE_DECL( |
| 1988 | rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 1989 | RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1990 | |
| 1991 | static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = |
| 1992 | SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); |
| 1993 | |
| 1994 | static SOC_ENUM_SINGLE_DECL( |
| 1995 | rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 1996 | RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); |
| 1997 | |
| 1998 | static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = |
| 1999 | SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); |
| 2000 | |
| 2001 | static SOC_ENUM_SINGLE_DECL( |
| 2002 | rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2003 | RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2004 | |
| 2005 | static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = |
| 2006 | SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); |
| 2007 | |
| 2008 | static SOC_ENUM_SINGLE_DECL( |
| 2009 | rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2010 | RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2011 | |
| 2012 | static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = |
| 2013 | SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); |
| 2014 | |
| 2015 | static SOC_ENUM_SINGLE_DECL( |
| 2016 | rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2017 | RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2018 | |
| 2019 | static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = |
| 2020 | SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); |
| 2021 | |
| 2022 | static SOC_ENUM_SINGLE_DECL( |
| 2023 | rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2024 | RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2025 | |
| 2026 | static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = |
| 2027 | SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); |
| 2028 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2029 | static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, |
| 2030 | struct snd_kcontrol *kcontrol, int event) |
| 2031 | { |
| 2032 | struct snd_soc_codec *codec = w->codec; |
| 2033 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2034 | |
| 2035 | switch (event) { |
| 2036 | case SND_SOC_DAPM_POST_PMU: |
| 2037 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2038 | RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); |
| 2039 | break; |
| 2040 | |
| 2041 | case SND_SOC_DAPM_PRE_PMD: |
| 2042 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2043 | RT5677_PWR_BST1_P, 0); |
| 2044 | break; |
| 2045 | |
| 2046 | default: |
| 2047 | return 0; |
| 2048 | } |
| 2049 | |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
| 2053 | static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, |
| 2054 | struct snd_kcontrol *kcontrol, int event) |
| 2055 | { |
| 2056 | struct snd_soc_codec *codec = w->codec; |
| 2057 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2058 | |
| 2059 | switch (event) { |
| 2060 | case SND_SOC_DAPM_POST_PMU: |
| 2061 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2062 | RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); |
| 2063 | break; |
| 2064 | |
| 2065 | case SND_SOC_DAPM_PRE_PMD: |
| 2066 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2067 | RT5677_PWR_BST2_P, 0); |
| 2068 | break; |
| 2069 | |
| 2070 | default: |
| 2071 | return 0; |
| 2072 | } |
| 2073 | |
| 2074 | return 0; |
| 2075 | } |
| 2076 | |
| 2077 | static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, |
| 2078 | struct snd_kcontrol *kcontrol, int event) |
| 2079 | { |
| 2080 | struct snd_soc_codec *codec = w->codec; |
| 2081 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2082 | |
| 2083 | switch (event) { |
| 2084 | case SND_SOC_DAPM_POST_PMU: |
| 2085 | regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); |
| 2086 | regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); |
| 2087 | break; |
| 2088 | default: |
| 2089 | return 0; |
| 2090 | } |
| 2091 | |
| 2092 | return 0; |
| 2093 | } |
| 2094 | |
| 2095 | static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, |
| 2096 | struct snd_kcontrol *kcontrol, int event) |
| 2097 | { |
| 2098 | struct snd_soc_codec *codec = w->codec; |
| 2099 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2100 | |
| 2101 | switch (event) { |
| 2102 | case SND_SOC_DAPM_POST_PMU: |
| 2103 | regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); |
| 2104 | regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); |
| 2105 | break; |
| 2106 | default: |
| 2107 | return 0; |
| 2108 | } |
| 2109 | |
| 2110 | return 0; |
| 2111 | } |
| 2112 | |
| 2113 | static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, |
| 2114 | struct snd_kcontrol *kcontrol, int event) |
| 2115 | { |
| 2116 | struct snd_soc_codec *codec = w->codec; |
| 2117 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2118 | |
| 2119 | switch (event) { |
| 2120 | case SND_SOC_DAPM_POST_PMU: |
| 2121 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2122 | RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | |
| 2123 | RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | |
| 2124 | RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); |
| 2125 | break; |
Oder Chiou | f58c3b9 | 2014-06-10 14:35:26 +0800 | [diff] [blame] | 2126 | |
| 2127 | case SND_SOC_DAPM_PRE_PMD: |
| 2128 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2129 | RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | |
| 2130 | RT5677_PWR_CLK_MB, 0); |
| 2131 | break; |
| 2132 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2133 | default: |
| 2134 | return 0; |
| 2135 | } |
| 2136 | |
| 2137 | return 0; |
| 2138 | } |
| 2139 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2140 | static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, |
| 2141 | struct snd_kcontrol *kcontrol, int event) |
| 2142 | { |
| 2143 | struct snd_soc_codec *codec = w->codec; |
| 2144 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2145 | unsigned int value; |
| 2146 | |
| 2147 | switch (event) { |
| 2148 | case SND_SOC_DAPM_PRE_PMU: |
| 2149 | regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); |
| 2150 | if (value & RT5677_IF1_ADC_CTRL_MASK) |
| 2151 | regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, |
| 2152 | RT5677_IF1_ADC_MODE_MASK, |
| 2153 | RT5677_IF1_ADC_MODE_TDM); |
| 2154 | break; |
| 2155 | |
| 2156 | default: |
| 2157 | return 0; |
| 2158 | } |
| 2159 | |
| 2160 | return 0; |
| 2161 | } |
| 2162 | |
| 2163 | static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, |
| 2164 | struct snd_kcontrol *kcontrol, int event) |
| 2165 | { |
| 2166 | struct snd_soc_codec *codec = w->codec; |
| 2167 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2168 | unsigned int value; |
| 2169 | |
| 2170 | switch (event) { |
| 2171 | case SND_SOC_DAPM_PRE_PMU: |
| 2172 | regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); |
| 2173 | if (value & RT5677_IF2_ADC_CTRL_MASK) |
| 2174 | regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, |
| 2175 | RT5677_IF2_ADC_MODE_MASK, |
| 2176 | RT5677_IF2_ADC_MODE_TDM); |
| 2177 | break; |
| 2178 | |
| 2179 | default: |
| 2180 | return 0; |
| 2181 | } |
| 2182 | |
| 2183 | return 0; |
| 2184 | } |
| 2185 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2186 | static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { |
| 2187 | SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, |
| 2188 | 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU), |
| 2189 | SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, |
| 2190 | 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU), |
| 2191 | |
| 2192 | /* Input Side */ |
| 2193 | /* micbias */ |
Oder Chiou | 3d0c03d | 2014-06-10 14:35:23 +0800 | [diff] [blame] | 2194 | SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, |
Oder Chiou | f58c3b9 | 2014-06-10 14:35:26 +0800 | [diff] [blame] | 2195 | 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | |
| 2196 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2197 | |
| 2198 | /* Input Lines */ |
| 2199 | SND_SOC_DAPM_INPUT("DMIC L1"), |
| 2200 | SND_SOC_DAPM_INPUT("DMIC R1"), |
| 2201 | SND_SOC_DAPM_INPUT("DMIC L2"), |
| 2202 | SND_SOC_DAPM_INPUT("DMIC R2"), |
| 2203 | SND_SOC_DAPM_INPUT("DMIC L3"), |
| 2204 | SND_SOC_DAPM_INPUT("DMIC R3"), |
| 2205 | SND_SOC_DAPM_INPUT("DMIC L4"), |
| 2206 | SND_SOC_DAPM_INPUT("DMIC R4"), |
| 2207 | |
| 2208 | SND_SOC_DAPM_INPUT("IN1P"), |
| 2209 | SND_SOC_DAPM_INPUT("IN1N"), |
| 2210 | SND_SOC_DAPM_INPUT("IN2P"), |
| 2211 | SND_SOC_DAPM_INPUT("IN2N"), |
| 2212 | |
| 2213 | SND_SOC_DAPM_INPUT("Haptic Generator"), |
| 2214 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 2215 | SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2216 | SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2217 | SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2218 | SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2219 | |
| 2220 | SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, |
| 2221 | RT5677_DMIC_1_EN_SFT, 0, NULL, 0), |
| 2222 | SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, |
| 2223 | RT5677_DMIC_2_EN_SFT, 0, NULL, 0), |
| 2224 | SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, |
| 2225 | RT5677_DMIC_3_EN_SFT, 0, NULL, 0), |
| 2226 | SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, |
| 2227 | RT5677_DMIC_4_EN_SFT, 0, NULL, 0), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2228 | |
| 2229 | SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, |
| 2230 | set_dmic_clk, SND_SOC_DAPM_PRE_PMU), |
| 2231 | |
| 2232 | /* Boost */ |
| 2233 | SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, |
| 2234 | RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, |
| 2235 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
| 2236 | SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, |
| 2237 | RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, |
| 2238 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
| 2239 | |
| 2240 | /* ADCs */ |
| 2241 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, |
| 2242 | 0, 0), |
| 2243 | SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, |
| 2244 | 0, 0), |
| 2245 | SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2246 | |
| 2247 | SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, |
| 2248 | RT5677_PWR_ADC_L_BIT, 0, NULL, 0), |
| 2249 | SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, |
| 2250 | RT5677_PWR_ADC_R_BIT, 0, NULL, 0), |
| 2251 | SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, |
| 2252 | RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), |
| 2253 | SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, |
| 2254 | RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), |
| 2255 | |
| 2256 | /* ADC Mux */ |
| 2257 | SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2258 | &rt5677_sto1_dmic_mux), |
| 2259 | SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2260 | &rt5677_sto1_adc1_mux), |
| 2261 | SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2262 | &rt5677_sto1_adc2_mux), |
| 2263 | SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2264 | &rt5677_sto2_dmic_mux), |
| 2265 | SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2266 | &rt5677_sto2_adc1_mux), |
| 2267 | SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2268 | &rt5677_sto2_adc2_mux), |
| 2269 | SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, |
| 2270 | &rt5677_sto2_adc_lr_mux), |
| 2271 | SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2272 | &rt5677_sto3_dmic_mux), |
| 2273 | SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2274 | &rt5677_sto3_adc1_mux), |
| 2275 | SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2276 | &rt5677_sto3_adc2_mux), |
| 2277 | SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2278 | &rt5677_sto4_dmic_mux), |
| 2279 | SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2280 | &rt5677_sto4_adc1_mux), |
| 2281 | SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2282 | &rt5677_sto4_adc2_mux), |
| 2283 | SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, |
| 2284 | &rt5677_mono_dmic_l_mux), |
| 2285 | SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, |
| 2286 | &rt5677_mono_dmic_r_mux), |
| 2287 | SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, |
| 2288 | &rt5677_mono_adc2_l_mux), |
| 2289 | SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, |
| 2290 | &rt5677_mono_adc1_l_mux), |
| 2291 | SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, |
| 2292 | &rt5677_mono_adc1_r_mux), |
| 2293 | SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, |
| 2294 | &rt5677_mono_adc2_r_mux), |
| 2295 | |
| 2296 | /* ADC Mixer */ |
| 2297 | SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, |
| 2298 | RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), |
| 2299 | SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, |
| 2300 | RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), |
| 2301 | SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, |
| 2302 | RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), |
| 2303 | SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, |
| 2304 | RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), |
| 2305 | SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2306 | rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), |
| 2307 | SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2308 | rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), |
| 2309 | SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2310 | rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), |
| 2311 | SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2312 | rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), |
| 2313 | SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2314 | rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), |
| 2315 | SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2316 | rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), |
| 2317 | SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2318 | rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), |
| 2319 | SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2320 | rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), |
| 2321 | SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, |
| 2322 | RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), |
| 2323 | SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2324 | rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), |
| 2325 | SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, |
| 2326 | RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), |
| 2327 | SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2328 | rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), |
| 2329 | |
| 2330 | /* ADC PGA */ |
| 2331 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2332 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2333 | SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2334 | SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2335 | SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2336 | SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2337 | SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2338 | SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2339 | SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2340 | SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2341 | SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2342 | SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2343 | SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2344 | SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2345 | SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2346 | SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2347 | |
| 2348 | /* DSP */ |
| 2349 | SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, |
| 2350 | &rt5677_ib9_src_mux), |
| 2351 | SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, |
| 2352 | &rt5677_ib8_src_mux), |
| 2353 | SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, |
| 2354 | &rt5677_ib7_src_mux), |
| 2355 | SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, |
| 2356 | &rt5677_ib6_src_mux), |
| 2357 | SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, |
| 2358 | &rt5677_ib45_src_mux), |
| 2359 | SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, |
| 2360 | &rt5677_ib23_src_mux), |
| 2361 | SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, |
| 2362 | &rt5677_ib01_src_mux), |
| 2363 | SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2364 | &rt5677_ib45_bypass_src_mux), |
| 2365 | SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2366 | &rt5677_ib23_bypass_src_mux), |
| 2367 | SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2368 | &rt5677_ib01_bypass_src_mux), |
| 2369 | SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2370 | &rt5677_ob23_bypass_src_mux), |
| 2371 | SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2372 | &rt5677_ob01_bypass_src_mux), |
| 2373 | |
| 2374 | SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2375 | SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2376 | |
| 2377 | SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2378 | SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2379 | SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2380 | SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2381 | SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2382 | SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2383 | |
| 2384 | /* Digital Interface */ |
| 2385 | SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, |
| 2386 | RT5677_PWR_I2S1_BIT, 0, NULL, 0), |
| 2387 | SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2388 | SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2389 | SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2390 | SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2391 | SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2392 | SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2393 | SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2394 | SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2395 | SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2396 | SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2397 | SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2398 | SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2399 | SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2400 | SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2401 | SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2402 | SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2403 | |
| 2404 | SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, |
| 2405 | RT5677_PWR_I2S2_BIT, 0, NULL, 0), |
| 2406 | SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2407 | SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2408 | SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2409 | SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2410 | SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2411 | SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2412 | SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2413 | SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2414 | SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2415 | SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2416 | SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2417 | SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2418 | SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2419 | SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2420 | SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2421 | SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2422 | |
| 2423 | SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, |
| 2424 | RT5677_PWR_I2S3_BIT, 0, NULL, 0), |
| 2425 | SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2426 | SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2427 | SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2428 | SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2429 | SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2430 | SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2431 | |
| 2432 | SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, |
| 2433 | RT5677_PWR_I2S4_BIT, 0, NULL, 0), |
| 2434 | SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2435 | SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2436 | SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2437 | SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2438 | SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2439 | SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2440 | |
| 2441 | SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, |
| 2442 | RT5677_PWR_SLB_BIT, 0, NULL, 0), |
| 2443 | SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2444 | SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2445 | SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2446 | SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2447 | SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2448 | SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2449 | SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2450 | SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2451 | SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2452 | SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2453 | SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2454 | SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2455 | SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2456 | SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2457 | SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2458 | SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2459 | |
| 2460 | /* Digital Interface Select */ |
| 2461 | SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2462 | &rt5677_if1_adc1_mux), |
| 2463 | SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2464 | &rt5677_if1_adc2_mux), |
| 2465 | SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2466 | &rt5677_if1_adc3_mux), |
| 2467 | SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2468 | &rt5677_if1_adc4_mux), |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2469 | SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2470 | &rt5677_if1_adc1_swap_mux), |
| 2471 | SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2472 | &rt5677_if1_adc2_swap_mux), |
| 2473 | SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2474 | &rt5677_if1_adc3_swap_mux), |
| 2475 | SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2476 | &rt5677_if1_adc4_swap_mux), |
| 2477 | SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2478 | &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, |
| 2479 | SND_SOC_DAPM_PRE_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2480 | SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2481 | &rt5677_if2_adc1_mux), |
| 2482 | SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2483 | &rt5677_if2_adc2_mux), |
| 2484 | SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2485 | &rt5677_if2_adc3_mux), |
| 2486 | SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2487 | &rt5677_if2_adc4_mux), |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2488 | SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2489 | &rt5677_if2_adc1_swap_mux), |
| 2490 | SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2491 | &rt5677_if2_adc2_swap_mux), |
| 2492 | SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2493 | &rt5677_if2_adc3_swap_mux), |
| 2494 | SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2495 | &rt5677_if2_adc4_swap_mux), |
| 2496 | SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2497 | &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, |
| 2498 | SND_SOC_DAPM_PRE_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2499 | SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, |
| 2500 | &rt5677_if3_adc_mux), |
| 2501 | SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, |
| 2502 | &rt5677_if4_adc_mux), |
| 2503 | SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2504 | &rt5677_slb_adc1_mux), |
| 2505 | SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2506 | &rt5677_slb_adc2_mux), |
| 2507 | SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2508 | &rt5677_slb_adc3_mux), |
| 2509 | SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2510 | &rt5677_slb_adc4_mux), |
| 2511 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame^] | 2512 | SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, |
| 2513 | &rt5677_if1_dac0_tdm_sel_mux), |
| 2514 | SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2515 | &rt5677_if1_dac1_tdm_sel_mux), |
| 2516 | SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2517 | &rt5677_if1_dac2_tdm_sel_mux), |
| 2518 | SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2519 | &rt5677_if1_dac3_tdm_sel_mux), |
| 2520 | SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2521 | &rt5677_if1_dac4_tdm_sel_mux), |
| 2522 | SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, |
| 2523 | &rt5677_if1_dac5_tdm_sel_mux), |
| 2524 | SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, |
| 2525 | &rt5677_if1_dac6_tdm_sel_mux), |
| 2526 | SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, |
| 2527 | &rt5677_if1_dac7_tdm_sel_mux), |
| 2528 | |
| 2529 | SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, |
| 2530 | &rt5677_if2_dac0_tdm_sel_mux), |
| 2531 | SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2532 | &rt5677_if2_dac1_tdm_sel_mux), |
| 2533 | SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2534 | &rt5677_if2_dac2_tdm_sel_mux), |
| 2535 | SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2536 | &rt5677_if2_dac3_tdm_sel_mux), |
| 2537 | SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2538 | &rt5677_if2_dac4_tdm_sel_mux), |
| 2539 | SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, |
| 2540 | &rt5677_if2_dac5_tdm_sel_mux), |
| 2541 | SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, |
| 2542 | &rt5677_if2_dac6_tdm_sel_mux), |
| 2543 | SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, |
| 2544 | &rt5677_if2_dac7_tdm_sel_mux), |
| 2545 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2546 | /* Audio Interface */ |
| 2547 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 2548 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 2549 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 2550 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 2551 | SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 2552 | SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 2553 | SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 2554 | SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 2555 | SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), |
| 2556 | SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), |
| 2557 | |
| 2558 | /* Sidetone Mux */ |
| 2559 | SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, |
| 2560 | &rt5677_sidetone_mux), |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 2561 | SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, |
| 2562 | RT5677_ST_EN_SFT, 0, NULL, 0), |
| 2563 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2564 | /* VAD Mux*/ |
| 2565 | SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, |
| 2566 | &rt5677_vad_src_mux), |
| 2567 | |
| 2568 | /* Tensilica DSP */ |
| 2569 | SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2570 | SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, |
| 2571 | rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), |
| 2572 | SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, |
| 2573 | rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), |
| 2574 | SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, |
| 2575 | rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), |
| 2576 | SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, |
| 2577 | rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), |
| 2578 | SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, |
| 2579 | rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), |
| 2580 | SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, |
| 2581 | rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), |
| 2582 | |
| 2583 | /* Output Side */ |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 2584 | /* DAC mixer before sound effect */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2585 | SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, |
| 2586 | rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), |
| 2587 | SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, |
| 2588 | rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), |
| 2589 | SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2590 | |
| 2591 | /* DAC Mux */ |
| 2592 | SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2593 | &rt5677_dac1_mux), |
| 2594 | SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, |
| 2595 | &rt5677_adda1_mux), |
| 2596 | SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, |
| 2597 | &rt5677_dac12_mux), |
| 2598 | SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, |
| 2599 | &rt5677_dac3_mux), |
| 2600 | |
| 2601 | /* DAC2 channel Mux */ |
| 2602 | SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, |
| 2603 | &rt5677_dac2_l_mux), |
| 2604 | SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, |
| 2605 | &rt5677_dac2_r_mux), |
| 2606 | |
| 2607 | /* DAC3 channel Mux */ |
| 2608 | SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, |
| 2609 | &rt5677_dac3_l_mux), |
| 2610 | SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, |
| 2611 | &rt5677_dac3_r_mux), |
| 2612 | |
| 2613 | /* DAC4 channel Mux */ |
| 2614 | SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, |
| 2615 | &rt5677_dac4_l_mux), |
| 2616 | SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, |
| 2617 | &rt5677_dac4_r_mux), |
| 2618 | |
| 2619 | /* DAC Mixer */ |
| 2620 | SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, |
| 2621 | RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0), |
| 2622 | SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2, |
| 2623 | RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0), |
| 2624 | SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2, |
| 2625 | RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0), |
| 2626 | |
| 2627 | SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, |
| 2628 | rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), |
| 2629 | SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, |
| 2630 | rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), |
| 2631 | SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, |
| 2632 | rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), |
| 2633 | SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, |
| 2634 | rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), |
| 2635 | SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, |
| 2636 | rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), |
| 2637 | SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, |
| 2638 | rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), |
| 2639 | SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, |
| 2640 | rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), |
| 2641 | SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, |
| 2642 | rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), |
| 2643 | SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2644 | SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2645 | SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2646 | SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2647 | |
| 2648 | /* DACs */ |
| 2649 | SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, |
| 2650 | RT5677_PWR_DAC1_BIT, 0), |
| 2651 | SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, |
| 2652 | RT5677_PWR_DAC2_BIT, 0), |
| 2653 | SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, |
| 2654 | RT5677_PWR_DAC3_BIT, 0), |
| 2655 | |
| 2656 | /* PDM */ |
| 2657 | SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, |
| 2658 | RT5677_PWR_PDM1_BIT, 0, NULL, 0), |
| 2659 | SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, |
| 2660 | RT5677_PWR_PDM2_BIT, 0, NULL, 0), |
| 2661 | |
| 2662 | SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, |
| 2663 | 1, &rt5677_pdm1_l_mux), |
| 2664 | SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, |
| 2665 | 1, &rt5677_pdm1_r_mux), |
| 2666 | SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, |
| 2667 | 1, &rt5677_pdm2_l_mux), |
| 2668 | SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, |
| 2669 | 1, &rt5677_pdm2_r_mux), |
| 2670 | |
| 2671 | SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, |
| 2672 | 0, NULL, 0), |
| 2673 | SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, |
| 2674 | 0, NULL, 0), |
| 2675 | SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, |
| 2676 | 0, NULL, 0), |
| 2677 | |
| 2678 | /* Output Lines */ |
| 2679 | SND_SOC_DAPM_OUTPUT("LOUT1"), |
| 2680 | SND_SOC_DAPM_OUTPUT("LOUT2"), |
| 2681 | SND_SOC_DAPM_OUTPUT("LOUT3"), |
| 2682 | SND_SOC_DAPM_OUTPUT("PDM1L"), |
| 2683 | SND_SOC_DAPM_OUTPUT("PDM1R"), |
| 2684 | SND_SOC_DAPM_OUTPUT("PDM2L"), |
| 2685 | SND_SOC_DAPM_OUTPUT("PDM2R"), |
| 2686 | }; |
| 2687 | |
| 2688 | static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { |
| 2689 | { "DMIC1", NULL, "DMIC L1" }, |
| 2690 | { "DMIC1", NULL, "DMIC R1" }, |
| 2691 | { "DMIC2", NULL, "DMIC L2" }, |
| 2692 | { "DMIC2", NULL, "DMIC R2" }, |
| 2693 | { "DMIC3", NULL, "DMIC L3" }, |
| 2694 | { "DMIC3", NULL, "DMIC R3" }, |
| 2695 | { "DMIC4", NULL, "DMIC L4" }, |
| 2696 | { "DMIC4", NULL, "DMIC R4" }, |
| 2697 | |
| 2698 | { "DMIC L1", NULL, "DMIC CLK" }, |
| 2699 | { "DMIC R1", NULL, "DMIC CLK" }, |
| 2700 | { "DMIC L2", NULL, "DMIC CLK" }, |
| 2701 | { "DMIC R2", NULL, "DMIC CLK" }, |
| 2702 | { "DMIC L3", NULL, "DMIC CLK" }, |
| 2703 | { "DMIC R3", NULL, "DMIC CLK" }, |
| 2704 | { "DMIC L4", NULL, "DMIC CLK" }, |
| 2705 | { "DMIC R4", NULL, "DMIC CLK" }, |
| 2706 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 2707 | { "DMIC L1", NULL, "DMIC1 power" }, |
| 2708 | { "DMIC R1", NULL, "DMIC1 power" }, |
| 2709 | { "DMIC L3", NULL, "DMIC3 power" }, |
| 2710 | { "DMIC R3", NULL, "DMIC3 power" }, |
| 2711 | { "DMIC L4", NULL, "DMIC4 power" }, |
| 2712 | { "DMIC R4", NULL, "DMIC4 power" }, |
| 2713 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2714 | { "BST1", NULL, "IN1P" }, |
| 2715 | { "BST1", NULL, "IN1N" }, |
| 2716 | { "BST2", NULL, "IN2P" }, |
| 2717 | { "BST2", NULL, "IN2N" }, |
| 2718 | |
Bard Liao | 22e5134 | 2014-08-27 19:50:33 +0800 | [diff] [blame] | 2719 | { "IN1P", NULL, "MICBIAS1" }, |
| 2720 | { "IN1N", NULL, "MICBIAS1" }, |
| 2721 | { "IN2P", NULL, "MICBIAS1" }, |
| 2722 | { "IN2N", NULL, "MICBIAS1" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2723 | |
| 2724 | { "ADC 1", NULL, "BST1" }, |
| 2725 | { "ADC 1", NULL, "ADC 1 power" }, |
| 2726 | { "ADC 1", NULL, "ADC1 clock" }, |
| 2727 | { "ADC 2", NULL, "BST2" }, |
| 2728 | { "ADC 2", NULL, "ADC 2 power" }, |
| 2729 | { "ADC 2", NULL, "ADC2 clock" }, |
| 2730 | |
| 2731 | { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, |
| 2732 | { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, |
| 2733 | { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, |
| 2734 | { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, |
| 2735 | |
| 2736 | { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, |
| 2737 | { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, |
| 2738 | { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, |
| 2739 | { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, |
| 2740 | |
| 2741 | { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, |
| 2742 | { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, |
| 2743 | { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, |
| 2744 | { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, |
| 2745 | |
| 2746 | { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, |
| 2747 | { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, |
| 2748 | { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, |
| 2749 | { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, |
| 2750 | |
| 2751 | { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, |
| 2752 | { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, |
| 2753 | { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, |
| 2754 | { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, |
| 2755 | |
| 2756 | { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, |
| 2757 | { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, |
| 2758 | { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, |
| 2759 | { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, |
| 2760 | |
| 2761 | { "ADC 1_2", NULL, "ADC 1" }, |
| 2762 | { "ADC 1_2", NULL, "ADC 2" }, |
| 2763 | |
| 2764 | { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 2765 | { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 2766 | { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 2767 | |
| 2768 | { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 2769 | { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, |
| 2770 | { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 2771 | |
| 2772 | { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 2773 | { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 2774 | { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 2775 | |
| 2776 | { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 2777 | { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, |
| 2778 | { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 2779 | |
| 2780 | { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 2781 | { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 2782 | { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 2783 | |
| 2784 | { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 2785 | { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, |
| 2786 | { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 2787 | |
| 2788 | { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 2789 | { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 2790 | { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, |
| 2791 | |
| 2792 | { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 2793 | { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, |
| 2794 | { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, |
| 2795 | |
| 2796 | { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, |
| 2797 | { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, |
| 2798 | { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, |
| 2799 | |
| 2800 | { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, |
| 2801 | { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, |
| 2802 | { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, |
| 2803 | |
| 2804 | { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, |
| 2805 | { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, |
| 2806 | { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, |
| 2807 | |
| 2808 | { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, |
| 2809 | { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, |
| 2810 | { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, |
| 2811 | |
| 2812 | { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, |
| 2813 | { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, |
| 2814 | { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, |
| 2815 | { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, |
| 2816 | |
| 2817 | { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, |
| 2818 | { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, |
| 2819 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2820 | |
| 2821 | { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, |
| 2822 | { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, |
| 2823 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2824 | |
| 2825 | { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, |
| 2826 | { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, |
| 2827 | |
| 2828 | { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, |
| 2829 | { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, |
| 2830 | { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, |
| 2831 | { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, |
| 2832 | |
| 2833 | { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, |
| 2834 | { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, |
| 2835 | |
| 2836 | { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, |
| 2837 | { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, |
| 2838 | |
| 2839 | { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, |
| 2840 | { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, |
| 2841 | { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2842 | |
| 2843 | { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, |
| 2844 | { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, |
| 2845 | { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2846 | |
| 2847 | { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, |
| 2848 | { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, |
| 2849 | |
| 2850 | { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, |
| 2851 | { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, |
| 2852 | { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, |
| 2853 | { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, |
| 2854 | |
| 2855 | { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, |
| 2856 | { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, |
| 2857 | { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2858 | |
| 2859 | { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, |
| 2860 | { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, |
| 2861 | { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2862 | |
| 2863 | { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, |
| 2864 | { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, |
| 2865 | |
| 2866 | { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, |
| 2867 | { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, |
| 2868 | { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, |
| 2869 | { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, |
| 2870 | |
| 2871 | { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, |
| 2872 | { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, |
| 2873 | { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2874 | |
| 2875 | { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, |
| 2876 | { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, |
| 2877 | { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2878 | |
| 2879 | { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, |
| 2880 | { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, |
| 2881 | |
| 2882 | { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, |
| 2883 | { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, |
| 2884 | { "Mono ADC MIXL", NULL, "adc mono left filter" }, |
| 2885 | { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2886 | |
| 2887 | { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, |
| 2888 | { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, |
| 2889 | { "Mono ADC MIXR", NULL, "adc mono right filter" }, |
| 2890 | { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 2891 | |
| 2892 | { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, |
| 2893 | { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, |
| 2894 | |
| 2895 | { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, |
| 2896 | { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, |
| 2897 | { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, |
| 2898 | { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, |
| 2899 | { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, |
| 2900 | |
| 2901 | { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 2902 | { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, |
| 2903 | { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, |
| 2904 | |
| 2905 | { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 2906 | { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, |
| 2907 | |
| 2908 | { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 2909 | { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 2910 | { "IF1 ADC3 Mux", "OB45", "OB45" }, |
| 2911 | |
| 2912 | { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 2913 | { "IF1 ADC4 Mux", "OB67", "OB67" }, |
| 2914 | { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, |
| 2915 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2916 | { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, |
| 2917 | { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, |
| 2918 | { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, |
| 2919 | { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, |
| 2920 | |
| 2921 | { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, |
| 2922 | { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, |
| 2923 | { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, |
| 2924 | { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, |
| 2925 | |
| 2926 | { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, |
| 2927 | { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, |
| 2928 | { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, |
| 2929 | { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, |
| 2930 | |
| 2931 | { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, |
| 2932 | { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, |
| 2933 | { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, |
| 2934 | { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, |
| 2935 | |
| 2936 | { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, |
| 2937 | { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, |
| 2938 | { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, |
| 2939 | { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, |
| 2940 | |
| 2941 | { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, |
| 2942 | { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, |
| 2943 | { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, |
| 2944 | { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, |
| 2945 | { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, |
| 2946 | { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, |
| 2947 | { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, |
| 2948 | { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, |
| 2949 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2950 | { "AIF1TX", NULL, "I2S1" }, |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2951 | { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2952 | |
| 2953 | { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 2954 | { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, |
| 2955 | { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, |
| 2956 | |
| 2957 | { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 2958 | { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, |
| 2959 | |
| 2960 | { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 2961 | { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 2962 | { "IF2 ADC3 Mux", "OB45", "OB45" }, |
| 2963 | |
| 2964 | { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 2965 | { "IF2 ADC4 Mux", "OB67", "OB67" }, |
| 2966 | { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, |
| 2967 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2968 | { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, |
| 2969 | { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, |
| 2970 | { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, |
| 2971 | { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, |
| 2972 | |
| 2973 | { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, |
| 2974 | { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, |
| 2975 | { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, |
| 2976 | { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, |
| 2977 | |
| 2978 | { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, |
| 2979 | { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, |
| 2980 | { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, |
| 2981 | { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, |
| 2982 | |
| 2983 | { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, |
| 2984 | { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, |
| 2985 | { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, |
| 2986 | { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, |
| 2987 | |
| 2988 | { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, |
| 2989 | { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, |
| 2990 | { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, |
| 2991 | { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, |
| 2992 | |
| 2993 | { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, |
| 2994 | { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, |
| 2995 | { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, |
| 2996 | { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, |
| 2997 | { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, |
| 2998 | { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, |
| 2999 | { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, |
| 3000 | { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, |
| 3001 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3002 | { "AIF2TX", NULL, "I2S2" }, |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 3003 | { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3004 | |
| 3005 | { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3006 | { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3007 | { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3008 | { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3009 | { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3010 | { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, |
| 3011 | { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, |
| 3012 | { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3013 | |
| 3014 | { "AIF3TX", NULL, "I2S3" }, |
| 3015 | { "AIF3TX", NULL, "IF3 ADC Mux" }, |
| 3016 | |
| 3017 | { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3018 | { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3019 | { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3020 | { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3021 | { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3022 | { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, |
| 3023 | { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, |
| 3024 | { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3025 | |
| 3026 | { "AIF4TX", NULL, "I2S4" }, |
| 3027 | { "AIF4TX", NULL, "IF4 ADC Mux" }, |
| 3028 | |
| 3029 | { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3030 | { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3031 | { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3032 | |
| 3033 | { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3034 | { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, |
| 3035 | |
| 3036 | { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3037 | { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3038 | { "SLB ADC3 Mux", "OB45", "OB45" }, |
| 3039 | |
| 3040 | { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3041 | { "SLB ADC4 Mux", "OB67", "OB67" }, |
| 3042 | { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3043 | |
| 3044 | { "SLBTX", NULL, "SLB" }, |
| 3045 | { "SLBTX", NULL, "SLB ADC1 Mux" }, |
| 3046 | { "SLBTX", NULL, "SLB ADC2 Mux" }, |
| 3047 | { "SLBTX", NULL, "SLB ADC3 Mux" }, |
| 3048 | { "SLBTX", NULL, "SLB ADC4 Mux" }, |
| 3049 | |
| 3050 | { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, |
| 3051 | { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, |
| 3052 | { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, |
| 3053 | { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3054 | { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, |
| 3055 | |
| 3056 | { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, |
| 3057 | { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, |
| 3058 | |
| 3059 | { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, |
| 3060 | { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, |
| 3061 | { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, |
| 3062 | { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3063 | { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, |
| 3064 | { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, |
| 3065 | |
| 3066 | { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, |
| 3067 | { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, |
| 3068 | |
| 3069 | { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, |
| 3070 | { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, |
| 3071 | { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, |
| 3072 | { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3073 | { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, |
| 3074 | |
| 3075 | { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, |
| 3076 | { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, |
| 3077 | |
| 3078 | { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" }, |
| 3079 | { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" }, |
| 3080 | { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, |
| 3081 | { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, |
| 3082 | { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3083 | { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, |
| 3084 | { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, |
| 3085 | { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, |
| 3086 | |
| 3087 | { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" }, |
| 3088 | { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" }, |
| 3089 | { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, |
| 3090 | { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, |
| 3091 | { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3092 | { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, |
| 3093 | { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, |
| 3094 | { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, |
| 3095 | |
| 3096 | { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, |
| 3097 | { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, |
| 3098 | { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, |
| 3099 | { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, |
| 3100 | { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, |
| 3101 | { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, |
| 3102 | |
| 3103 | { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, |
| 3104 | { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, |
| 3105 | { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, |
| 3106 | { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, |
| 3107 | { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, |
| 3108 | { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, |
| 3109 | { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, |
| 3110 | |
| 3111 | { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3112 | { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3113 | { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3114 | { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3115 | { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3116 | { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3117 | { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3118 | |
| 3119 | { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3120 | { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3121 | { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3122 | { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3123 | { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3124 | { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3125 | { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3126 | |
| 3127 | { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3128 | { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3129 | { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3130 | { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3131 | { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3132 | { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3133 | { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3134 | |
| 3135 | { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3136 | { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3137 | { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3138 | { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3139 | { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3140 | { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3141 | { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3142 | |
| 3143 | { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3144 | { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3145 | { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3146 | { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3147 | { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3148 | { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3149 | { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3150 | |
| 3151 | { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3152 | { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3153 | { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3154 | { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3155 | { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3156 | { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3157 | { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3158 | |
| 3159 | { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, |
| 3160 | { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, |
| 3161 | { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, |
| 3162 | { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, |
| 3163 | |
| 3164 | { "OutBound2", NULL, "OB23 Bypass Mux" }, |
| 3165 | { "OutBound3", NULL, "OB23 Bypass Mux" }, |
| 3166 | { "OutBound4", NULL, "OB4 MIX" }, |
| 3167 | { "OutBound5", NULL, "OB5 MIX" }, |
| 3168 | { "OutBound6", NULL, "OB6 MIX" }, |
| 3169 | { "OutBound7", NULL, "OB7 MIX" }, |
| 3170 | |
| 3171 | { "OB45", NULL, "OutBound4" }, |
| 3172 | { "OB45", NULL, "OutBound5" }, |
| 3173 | { "OB67", NULL, "OutBound6" }, |
| 3174 | { "OB67", NULL, "OutBound7" }, |
| 3175 | |
| 3176 | { "IF1 DAC0", NULL, "AIF1RX" }, |
| 3177 | { "IF1 DAC1", NULL, "AIF1RX" }, |
| 3178 | { "IF1 DAC2", NULL, "AIF1RX" }, |
| 3179 | { "IF1 DAC3", NULL, "AIF1RX" }, |
| 3180 | { "IF1 DAC4", NULL, "AIF1RX" }, |
| 3181 | { "IF1 DAC5", NULL, "AIF1RX" }, |
| 3182 | { "IF1 DAC6", NULL, "AIF1RX" }, |
| 3183 | { "IF1 DAC7", NULL, "AIF1RX" }, |
| 3184 | { "IF1 DAC0", NULL, "I2S1" }, |
| 3185 | { "IF1 DAC1", NULL, "I2S1" }, |
| 3186 | { "IF1 DAC2", NULL, "I2S1" }, |
| 3187 | { "IF1 DAC3", NULL, "I2S1" }, |
| 3188 | { "IF1 DAC4", NULL, "I2S1" }, |
| 3189 | { "IF1 DAC5", NULL, "I2S1" }, |
| 3190 | { "IF1 DAC6", NULL, "I2S1" }, |
| 3191 | { "IF1 DAC7", NULL, "I2S1" }, |
| 3192 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame^] | 3193 | { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, |
| 3194 | { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, |
| 3195 | { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, |
| 3196 | { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, |
| 3197 | { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, |
| 3198 | { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, |
| 3199 | { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, |
| 3200 | { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, |
| 3201 | |
| 3202 | { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, |
| 3203 | { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, |
| 3204 | { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, |
| 3205 | { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, |
| 3206 | { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, |
| 3207 | { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, |
| 3208 | { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, |
| 3209 | { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, |
| 3210 | |
| 3211 | { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, |
| 3212 | { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, |
| 3213 | { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, |
| 3214 | { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, |
| 3215 | { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, |
| 3216 | { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, |
| 3217 | { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, |
| 3218 | { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, |
| 3219 | |
| 3220 | { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, |
| 3221 | { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, |
| 3222 | { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, |
| 3223 | { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, |
| 3224 | { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, |
| 3225 | { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, |
| 3226 | { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, |
| 3227 | { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, |
| 3228 | |
| 3229 | { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, |
| 3230 | { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, |
| 3231 | { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, |
| 3232 | { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, |
| 3233 | { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, |
| 3234 | { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, |
| 3235 | { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, |
| 3236 | { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, |
| 3237 | |
| 3238 | { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, |
| 3239 | { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, |
| 3240 | { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, |
| 3241 | { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, |
| 3242 | { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, |
| 3243 | { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, |
| 3244 | { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, |
| 3245 | { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, |
| 3246 | |
| 3247 | { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, |
| 3248 | { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, |
| 3249 | { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, |
| 3250 | { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, |
| 3251 | { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, |
| 3252 | { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, |
| 3253 | { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, |
| 3254 | { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, |
| 3255 | |
| 3256 | { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, |
| 3257 | { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, |
| 3258 | { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, |
| 3259 | { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, |
| 3260 | { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, |
| 3261 | { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, |
| 3262 | { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, |
| 3263 | { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, |
| 3264 | |
| 3265 | { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, |
| 3266 | { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, |
| 3267 | { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, |
| 3268 | { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, |
| 3269 | { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, |
| 3270 | { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, |
| 3271 | { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, |
| 3272 | { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3273 | |
| 3274 | { "IF2 DAC0", NULL, "AIF2RX" }, |
| 3275 | { "IF2 DAC1", NULL, "AIF2RX" }, |
| 3276 | { "IF2 DAC2", NULL, "AIF2RX" }, |
| 3277 | { "IF2 DAC3", NULL, "AIF2RX" }, |
| 3278 | { "IF2 DAC4", NULL, "AIF2RX" }, |
| 3279 | { "IF2 DAC5", NULL, "AIF2RX" }, |
| 3280 | { "IF2 DAC6", NULL, "AIF2RX" }, |
| 3281 | { "IF2 DAC7", NULL, "AIF2RX" }, |
| 3282 | { "IF2 DAC0", NULL, "I2S2" }, |
| 3283 | { "IF2 DAC1", NULL, "I2S2" }, |
| 3284 | { "IF2 DAC2", NULL, "I2S2" }, |
| 3285 | { "IF2 DAC3", NULL, "I2S2" }, |
| 3286 | { "IF2 DAC4", NULL, "I2S2" }, |
| 3287 | { "IF2 DAC5", NULL, "I2S2" }, |
| 3288 | { "IF2 DAC6", NULL, "I2S2" }, |
| 3289 | { "IF2 DAC7", NULL, "I2S2" }, |
| 3290 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame^] | 3291 | { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, |
| 3292 | { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, |
| 3293 | { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, |
| 3294 | { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, |
| 3295 | { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, |
| 3296 | { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, |
| 3297 | { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, |
| 3298 | { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, |
| 3299 | |
| 3300 | { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, |
| 3301 | { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, |
| 3302 | { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, |
| 3303 | { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, |
| 3304 | { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, |
| 3305 | { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, |
| 3306 | { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, |
| 3307 | { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, |
| 3308 | |
| 3309 | { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, |
| 3310 | { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, |
| 3311 | { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, |
| 3312 | { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, |
| 3313 | { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, |
| 3314 | { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, |
| 3315 | { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, |
| 3316 | { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, |
| 3317 | |
| 3318 | { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, |
| 3319 | { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, |
| 3320 | { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, |
| 3321 | { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, |
| 3322 | { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, |
| 3323 | { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, |
| 3324 | { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, |
| 3325 | { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, |
| 3326 | |
| 3327 | { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, |
| 3328 | { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, |
| 3329 | { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, |
| 3330 | { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, |
| 3331 | { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, |
| 3332 | { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, |
| 3333 | { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, |
| 3334 | { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, |
| 3335 | |
| 3336 | { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, |
| 3337 | { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, |
| 3338 | { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, |
| 3339 | { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, |
| 3340 | { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, |
| 3341 | { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, |
| 3342 | { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, |
| 3343 | { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, |
| 3344 | |
| 3345 | { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, |
| 3346 | { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, |
| 3347 | { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, |
| 3348 | { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, |
| 3349 | { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, |
| 3350 | { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, |
| 3351 | { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, |
| 3352 | { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, |
| 3353 | |
| 3354 | { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, |
| 3355 | { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, |
| 3356 | { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, |
| 3357 | { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, |
| 3358 | { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, |
| 3359 | { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, |
| 3360 | { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, |
| 3361 | { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, |
| 3362 | |
| 3363 | { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, |
| 3364 | { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, |
| 3365 | { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, |
| 3366 | { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, |
| 3367 | { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, |
| 3368 | { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, |
| 3369 | { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, |
| 3370 | { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3371 | |
| 3372 | { "IF3 DAC", NULL, "AIF3RX" }, |
| 3373 | { "IF3 DAC", NULL, "I2S3" }, |
| 3374 | |
| 3375 | { "IF4 DAC", NULL, "AIF4RX" }, |
| 3376 | { "IF4 DAC", NULL, "I2S4" }, |
| 3377 | |
| 3378 | { "IF3 DAC L", NULL, "IF3 DAC" }, |
| 3379 | { "IF3 DAC R", NULL, "IF3 DAC" }, |
| 3380 | |
| 3381 | { "IF4 DAC L", NULL, "IF4 DAC" }, |
| 3382 | { "IF4 DAC R", NULL, "IF4 DAC" }, |
| 3383 | |
| 3384 | { "SLB DAC0", NULL, "SLBRX" }, |
| 3385 | { "SLB DAC1", NULL, "SLBRX" }, |
| 3386 | { "SLB DAC2", NULL, "SLBRX" }, |
| 3387 | { "SLB DAC3", NULL, "SLBRX" }, |
| 3388 | { "SLB DAC4", NULL, "SLBRX" }, |
| 3389 | { "SLB DAC5", NULL, "SLBRX" }, |
| 3390 | { "SLB DAC6", NULL, "SLBRX" }, |
| 3391 | { "SLB DAC7", NULL, "SLBRX" }, |
| 3392 | { "SLB DAC0", NULL, "SLB" }, |
| 3393 | { "SLB DAC1", NULL, "SLB" }, |
| 3394 | { "SLB DAC2", NULL, "SLB" }, |
| 3395 | { "SLB DAC3", NULL, "SLB" }, |
| 3396 | { "SLB DAC4", NULL, "SLB" }, |
| 3397 | { "SLB DAC5", NULL, "SLB" }, |
| 3398 | { "SLB DAC6", NULL, "SLB" }, |
| 3399 | { "SLB DAC7", NULL, "SLB" }, |
| 3400 | |
| 3401 | { "SLB DAC01", NULL, "SLB DAC0" }, |
| 3402 | { "SLB DAC01", NULL, "SLB DAC1" }, |
| 3403 | { "SLB DAC23", NULL, "SLB DAC2" }, |
| 3404 | { "SLB DAC23", NULL, "SLB DAC3" }, |
| 3405 | { "SLB DAC45", NULL, "SLB DAC4" }, |
| 3406 | { "SLB DAC45", NULL, "SLB DAC5" }, |
| 3407 | { "SLB DAC67", NULL, "SLB DAC6" }, |
| 3408 | { "SLB DAC67", NULL, "SLB DAC7" }, |
| 3409 | |
| 3410 | { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3411 | { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3412 | { "ADDA1 Mux", "OB 67", "OB67" }, |
| 3413 | |
| 3414 | { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, |
| 3415 | { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, |
| 3416 | { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, |
| 3417 | { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, |
| 3418 | { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, |
| 3419 | { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, |
| 3420 | |
| 3421 | { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, |
| 3422 | { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, |
| 3423 | { "DAC1 MIXL", NULL, "dac stereo1 filter" }, |
| 3424 | { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, |
| 3425 | { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, |
| 3426 | { "DAC1 MIXR", NULL, "dac stereo1 filter" }, |
| 3427 | |
| 3428 | { "DAC1 FS", NULL, "DAC1 MIXL" }, |
| 3429 | { "DAC1 FS", NULL, "DAC1 MIXR" }, |
| 3430 | |
| 3431 | { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" }, |
| 3432 | { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" }, |
| 3433 | { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, |
| 3434 | { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3435 | { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, |
| 3436 | { "DAC2 L Mux", "OB 2", "OutBound2" }, |
| 3437 | |
| 3438 | { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" }, |
| 3439 | { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" }, |
| 3440 | { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, |
| 3441 | { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3442 | { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, |
| 3443 | { "DAC2 R Mux", "OB 3", "OutBound3" }, |
| 3444 | { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, |
| 3445 | { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3446 | |
| 3447 | { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" }, |
| 3448 | { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" }, |
| 3449 | { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, |
| 3450 | { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3451 | { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, |
| 3452 | { "DAC3 L Mux", "OB 4", "OutBound4" }, |
| 3453 | |
| 3454 | { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" }, |
| 3455 | { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" }, |
| 3456 | { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, |
| 3457 | { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3458 | { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, |
| 3459 | { "DAC3 R Mux", "OB 5", "OutBound5" }, |
| 3460 | |
| 3461 | { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" }, |
| 3462 | { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" }, |
| 3463 | { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, |
| 3464 | { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3465 | { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, |
| 3466 | { "DAC4 L Mux", "OB 6", "OutBound6" }, |
| 3467 | |
| 3468 | { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" }, |
| 3469 | { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" }, |
| 3470 | { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, |
| 3471 | { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3472 | { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, |
| 3473 | { "DAC4 R Mux", "OB 7", "OutBound7" }, |
| 3474 | |
| 3475 | { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, |
| 3476 | { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, |
| 3477 | { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, |
| 3478 | { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, |
| 3479 | { "Sidetone Mux", "ADC1", "ADC 1" }, |
| 3480 | { "Sidetone Mux", "ADC2", "ADC 2" }, |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 3481 | { "Sidetone Mux", NULL, "Sidetone Power" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3482 | |
| 3483 | { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, |
| 3484 | { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, |
| 3485 | { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, |
| 3486 | { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, |
| 3487 | { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, |
| 3488 | { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, |
| 3489 | { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, |
| 3490 | { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, |
| 3491 | { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, |
| 3492 | { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, |
| 3493 | |
| 3494 | { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, |
| 3495 | { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, |
| 3496 | { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, |
| 3497 | { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, |
| 3498 | { "Mono DAC MIXL", NULL, "dac mono left filter" }, |
| 3499 | { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, |
| 3500 | { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, |
| 3501 | { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, |
| 3502 | { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, |
| 3503 | { "Mono DAC MIXR", NULL, "dac mono right filter" }, |
| 3504 | |
| 3505 | { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, |
| 3506 | { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, |
| 3507 | { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, |
| 3508 | { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, |
| 3509 | { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, |
| 3510 | { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, |
| 3511 | { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, |
| 3512 | { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, |
| 3513 | |
| 3514 | { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, |
| 3515 | { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, |
| 3516 | { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, |
| 3517 | { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, |
| 3518 | { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, |
| 3519 | { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, |
| 3520 | { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, |
| 3521 | { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, |
| 3522 | |
| 3523 | { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, |
| 3524 | { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, |
| 3525 | { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, |
| 3526 | { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, |
| 3527 | { "DD1 MIX", NULL, "DD1 MIXL" }, |
| 3528 | { "DD1 MIX", NULL, "DD1 MIXR" }, |
| 3529 | { "DD2 MIX", NULL, "DD2 MIXL" }, |
| 3530 | { "DD2 MIX", NULL, "DD2 MIXR" }, |
| 3531 | |
| 3532 | { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, |
| 3533 | { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, |
| 3534 | { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, |
| 3535 | { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, |
| 3536 | |
| 3537 | { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, |
| 3538 | { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, |
| 3539 | { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, |
| 3540 | { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, |
| 3541 | |
| 3542 | { "DAC 1", NULL, "DAC12 SRC Mux" }, |
| 3543 | { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3544 | { "DAC 2", NULL, "DAC12 SRC Mux" }, |
| 3545 | { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3546 | { "DAC 3", NULL, "DAC3 SRC Mux" }, |
| 3547 | { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3548 | |
| 3549 | { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, |
| 3550 | { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, |
| 3551 | { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, |
| 3552 | { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, |
| 3553 | { "PDM1 L Mux", NULL, "PDM1 Power" }, |
| 3554 | { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, |
| 3555 | { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, |
| 3556 | { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, |
| 3557 | { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, |
| 3558 | { "PDM1 R Mux", NULL, "PDM1 Power" }, |
| 3559 | { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, |
| 3560 | { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, |
| 3561 | { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, |
| 3562 | { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, |
| 3563 | { "PDM2 L Mux", NULL, "PDM2 Power" }, |
| 3564 | { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, |
| 3565 | { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, |
| 3566 | { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, |
| 3567 | { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, |
| 3568 | { "PDM2 R Mux", NULL, "PDM2 Power" }, |
| 3569 | |
| 3570 | { "LOUT1 amp", NULL, "DAC 1" }, |
| 3571 | { "LOUT2 amp", NULL, "DAC 2" }, |
| 3572 | { "LOUT3 amp", NULL, "DAC 3" }, |
| 3573 | |
| 3574 | { "LOUT1", NULL, "LOUT1 amp" }, |
| 3575 | { "LOUT2", NULL, "LOUT2 amp" }, |
| 3576 | { "LOUT3", NULL, "LOUT3 amp" }, |
| 3577 | |
| 3578 | { "PDM1L", NULL, "PDM1 L Mux" }, |
| 3579 | { "PDM1R", NULL, "PDM1 R Mux" }, |
| 3580 | { "PDM2L", NULL, "PDM2 L Mux" }, |
| 3581 | { "PDM2R", NULL, "PDM2 R Mux" }, |
| 3582 | }; |
| 3583 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 3584 | static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { |
| 3585 | { "DMIC L2", NULL, "DMIC1 power" }, |
| 3586 | { "DMIC R2", NULL, "DMIC1 power" }, |
| 3587 | }; |
| 3588 | |
| 3589 | static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { |
| 3590 | { "DMIC L2", NULL, "DMIC2 power" }, |
| 3591 | { "DMIC R2", NULL, "DMIC2 power" }, |
| 3592 | }; |
| 3593 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3594 | static int rt5677_hw_params(struct snd_pcm_substream *substream, |
| 3595 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
| 3596 | { |
| 3597 | struct snd_soc_codec *codec = dai->codec; |
| 3598 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 3599 | unsigned int val_len = 0, val_clk, mask_clk; |
| 3600 | int pre_div, bclk_ms, frame_size; |
| 3601 | |
| 3602 | rt5677->lrck[dai->id] = params_rate(params); |
Axel Lin | 30f14b4 | 2014-06-10 08:57:36 +0800 | [diff] [blame] | 3603 | pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3604 | if (pre_div < 0) { |
Anatol Pomozov | 8a4bd60 | 2014-10-15 13:55:32 -0700 | [diff] [blame] | 3605 | dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", |
| 3606 | rt5677->sysclk, rt5677->lrck[dai->id]); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3607 | return -EINVAL; |
| 3608 | } |
| 3609 | frame_size = snd_soc_params_to_frame_size(params); |
| 3610 | if (frame_size < 0) { |
| 3611 | dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); |
| 3612 | return -EINVAL; |
| 3613 | } |
| 3614 | bclk_ms = frame_size > 32; |
| 3615 | rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); |
| 3616 | |
| 3617 | dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", |
| 3618 | rt5677->bclk[dai->id], rt5677->lrck[dai->id]); |
| 3619 | dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", |
| 3620 | bclk_ms, pre_div, dai->id); |
| 3621 | |
| 3622 | switch (params_width(params)) { |
| 3623 | case 16: |
| 3624 | break; |
| 3625 | case 20: |
| 3626 | val_len |= RT5677_I2S_DL_20; |
| 3627 | break; |
| 3628 | case 24: |
| 3629 | val_len |= RT5677_I2S_DL_24; |
| 3630 | break; |
| 3631 | case 8: |
| 3632 | val_len |= RT5677_I2S_DL_8; |
| 3633 | break; |
| 3634 | default: |
| 3635 | return -EINVAL; |
| 3636 | } |
| 3637 | |
| 3638 | switch (dai->id) { |
| 3639 | case RT5677_AIF1: |
| 3640 | mask_clk = RT5677_I2S_PD1_MASK; |
| 3641 | val_clk = pre_div << RT5677_I2S_PD1_SFT; |
| 3642 | regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, |
| 3643 | RT5677_I2S_DL_MASK, val_len); |
| 3644 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 3645 | mask_clk, val_clk); |
| 3646 | break; |
| 3647 | case RT5677_AIF2: |
| 3648 | mask_clk = RT5677_I2S_PD2_MASK; |
| 3649 | val_clk = pre_div << RT5677_I2S_PD2_SFT; |
| 3650 | regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, |
| 3651 | RT5677_I2S_DL_MASK, val_len); |
| 3652 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 3653 | mask_clk, val_clk); |
| 3654 | break; |
| 3655 | case RT5677_AIF3: |
| 3656 | mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; |
| 3657 | val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | |
| 3658 | pre_div << RT5677_I2S_PD3_SFT; |
| 3659 | regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, |
| 3660 | RT5677_I2S_DL_MASK, val_len); |
| 3661 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 3662 | mask_clk, val_clk); |
| 3663 | break; |
| 3664 | case RT5677_AIF4: |
| 3665 | mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; |
| 3666 | val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | |
| 3667 | pre_div << RT5677_I2S_PD4_SFT; |
| 3668 | regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, |
| 3669 | RT5677_I2S_DL_MASK, val_len); |
| 3670 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 3671 | mask_clk, val_clk); |
| 3672 | break; |
| 3673 | default: |
| 3674 | break; |
| 3675 | } |
| 3676 | |
| 3677 | return 0; |
| 3678 | } |
| 3679 | |
| 3680 | static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 3681 | { |
| 3682 | struct snd_soc_codec *codec = dai->codec; |
| 3683 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 3684 | unsigned int reg_val = 0; |
| 3685 | |
| 3686 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 3687 | case SND_SOC_DAIFMT_CBM_CFM: |
| 3688 | rt5677->master[dai->id] = 1; |
| 3689 | break; |
| 3690 | case SND_SOC_DAIFMT_CBS_CFS: |
| 3691 | reg_val |= RT5677_I2S_MS_S; |
| 3692 | rt5677->master[dai->id] = 0; |
| 3693 | break; |
| 3694 | default: |
| 3695 | return -EINVAL; |
| 3696 | } |
| 3697 | |
| 3698 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 3699 | case SND_SOC_DAIFMT_NB_NF: |
| 3700 | break; |
| 3701 | case SND_SOC_DAIFMT_IB_NF: |
| 3702 | reg_val |= RT5677_I2S_BP_INV; |
| 3703 | break; |
| 3704 | default: |
| 3705 | return -EINVAL; |
| 3706 | } |
| 3707 | |
| 3708 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 3709 | case SND_SOC_DAIFMT_I2S: |
| 3710 | break; |
| 3711 | case SND_SOC_DAIFMT_LEFT_J: |
| 3712 | reg_val |= RT5677_I2S_DF_LEFT; |
| 3713 | break; |
| 3714 | case SND_SOC_DAIFMT_DSP_A: |
| 3715 | reg_val |= RT5677_I2S_DF_PCM_A; |
| 3716 | break; |
| 3717 | case SND_SOC_DAIFMT_DSP_B: |
| 3718 | reg_val |= RT5677_I2S_DF_PCM_B; |
| 3719 | break; |
| 3720 | default: |
| 3721 | return -EINVAL; |
| 3722 | } |
| 3723 | |
| 3724 | switch (dai->id) { |
| 3725 | case RT5677_AIF1: |
| 3726 | regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, |
| 3727 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 3728 | RT5677_I2S_DF_MASK, reg_val); |
| 3729 | break; |
| 3730 | case RT5677_AIF2: |
| 3731 | regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, |
| 3732 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 3733 | RT5677_I2S_DF_MASK, reg_val); |
| 3734 | break; |
| 3735 | case RT5677_AIF3: |
| 3736 | regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, |
| 3737 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 3738 | RT5677_I2S_DF_MASK, reg_val); |
| 3739 | break; |
| 3740 | case RT5677_AIF4: |
| 3741 | regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, |
| 3742 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 3743 | RT5677_I2S_DF_MASK, reg_val); |
| 3744 | break; |
| 3745 | default: |
| 3746 | break; |
| 3747 | } |
| 3748 | |
| 3749 | |
| 3750 | return 0; |
| 3751 | } |
| 3752 | |
| 3753 | static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, |
| 3754 | int clk_id, unsigned int freq, int dir) |
| 3755 | { |
| 3756 | struct snd_soc_codec *codec = dai->codec; |
| 3757 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 3758 | unsigned int reg_val = 0; |
| 3759 | |
| 3760 | if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) |
| 3761 | return 0; |
| 3762 | |
| 3763 | switch (clk_id) { |
| 3764 | case RT5677_SCLK_S_MCLK: |
| 3765 | reg_val |= RT5677_SCLK_SRC_MCLK; |
| 3766 | break; |
| 3767 | case RT5677_SCLK_S_PLL1: |
| 3768 | reg_val |= RT5677_SCLK_SRC_PLL1; |
| 3769 | break; |
| 3770 | case RT5677_SCLK_S_RCCLK: |
| 3771 | reg_val |= RT5677_SCLK_SRC_RCCLK; |
| 3772 | break; |
| 3773 | default: |
| 3774 | dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); |
| 3775 | return -EINVAL; |
| 3776 | } |
| 3777 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 3778 | RT5677_SCLK_SRC_MASK, reg_val); |
| 3779 | rt5677->sysclk = freq; |
| 3780 | rt5677->sysclk_src = clk_id; |
| 3781 | |
| 3782 | dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); |
| 3783 | |
| 3784 | return 0; |
| 3785 | } |
| 3786 | |
| 3787 | /** |
| 3788 | * rt5677_pll_calc - Calcualte PLL M/N/K code. |
| 3789 | * @freq_in: external clock provided to codec. |
| 3790 | * @freq_out: target clock which codec works on. |
| 3791 | * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. |
| 3792 | * |
| 3793 | * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. |
| 3794 | * |
| 3795 | * Returns 0 for success or negative error code. |
| 3796 | */ |
| 3797 | static int rt5677_pll_calc(const unsigned int freq_in, |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 3798 | const unsigned int freq_out, struct rl6231_pll_code *pll_code) |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3799 | { |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 3800 | if (RT5677_PLL_INP_MIN > freq_in) |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3801 | return -EINVAL; |
| 3802 | |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 3803 | return rl6231_pll_calc(freq_in, freq_out, pll_code); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3804 | } |
| 3805 | |
| 3806 | static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, |
| 3807 | unsigned int freq_in, unsigned int freq_out) |
| 3808 | { |
| 3809 | struct snd_soc_codec *codec = dai->codec; |
| 3810 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 3811 | struct rl6231_pll_code pll_code; |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3812 | int ret; |
| 3813 | |
| 3814 | if (source == rt5677->pll_src && freq_in == rt5677->pll_in && |
| 3815 | freq_out == rt5677->pll_out) |
| 3816 | return 0; |
| 3817 | |
| 3818 | if (!freq_in || !freq_out) { |
| 3819 | dev_dbg(codec->dev, "PLL disabled\n"); |
| 3820 | |
| 3821 | rt5677->pll_in = 0; |
| 3822 | rt5677->pll_out = 0; |
| 3823 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 3824 | RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); |
| 3825 | return 0; |
| 3826 | } |
| 3827 | |
| 3828 | switch (source) { |
| 3829 | case RT5677_PLL1_S_MCLK: |
| 3830 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 3831 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); |
| 3832 | break; |
| 3833 | case RT5677_PLL1_S_BCLK1: |
| 3834 | case RT5677_PLL1_S_BCLK2: |
| 3835 | case RT5677_PLL1_S_BCLK3: |
| 3836 | case RT5677_PLL1_S_BCLK4: |
| 3837 | switch (dai->id) { |
| 3838 | case RT5677_AIF1: |
| 3839 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 3840 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); |
| 3841 | break; |
| 3842 | case RT5677_AIF2: |
| 3843 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 3844 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); |
| 3845 | break; |
| 3846 | case RT5677_AIF3: |
| 3847 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 3848 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); |
| 3849 | break; |
| 3850 | case RT5677_AIF4: |
| 3851 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 3852 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); |
| 3853 | break; |
| 3854 | default: |
| 3855 | break; |
| 3856 | } |
| 3857 | break; |
| 3858 | default: |
| 3859 | dev_err(codec->dev, "Unknown PLL source %d\n", source); |
| 3860 | return -EINVAL; |
| 3861 | } |
| 3862 | |
| 3863 | ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); |
| 3864 | if (ret < 0) { |
| 3865 | dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); |
| 3866 | return ret; |
| 3867 | } |
| 3868 | |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 3869 | dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n", |
| 3870 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), |
| 3871 | pll_code.n_code, pll_code.k_code); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3872 | |
| 3873 | regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 3874 | pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3875 | regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, |
| 3876 | (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | |
| 3877 | pll_code.m_bp << RT5677_PLL_M_BP_SFT); |
| 3878 | |
| 3879 | rt5677->pll_in = freq_in; |
| 3880 | rt5677->pll_out = freq_out; |
| 3881 | rt5677->pll_src = source; |
| 3882 | |
| 3883 | return 0; |
| 3884 | } |
| 3885 | |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 3886 | static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, |
| 3887 | unsigned int rx_mask, int slots, int slot_width) |
| 3888 | { |
| 3889 | struct snd_soc_codec *codec = dai->codec; |
| 3890 | unsigned int val = 0; |
| 3891 | |
| 3892 | if (rx_mask || tx_mask) |
| 3893 | val |= (1 << 12); |
| 3894 | |
| 3895 | switch (slots) { |
| 3896 | case 4: |
| 3897 | val |= (1 << 10); |
| 3898 | break; |
| 3899 | case 6: |
| 3900 | val |= (2 << 10); |
| 3901 | break; |
| 3902 | case 8: |
| 3903 | val |= (3 << 10); |
| 3904 | break; |
| 3905 | case 2: |
| 3906 | default: |
| 3907 | break; |
| 3908 | } |
| 3909 | |
| 3910 | switch (slot_width) { |
| 3911 | case 20: |
| 3912 | val |= (1 << 8); |
| 3913 | break; |
| 3914 | case 24: |
| 3915 | val |= (2 << 8); |
| 3916 | break; |
| 3917 | case 32: |
| 3918 | val |= (3 << 8); |
| 3919 | break; |
| 3920 | case 16: |
| 3921 | default: |
| 3922 | break; |
| 3923 | } |
| 3924 | |
| 3925 | switch (dai->id) { |
| 3926 | case RT5677_AIF1: |
| 3927 | snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val); |
| 3928 | break; |
| 3929 | case RT5677_AIF2: |
| 3930 | snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val); |
| 3931 | break; |
| 3932 | default: |
| 3933 | break; |
| 3934 | } |
| 3935 | |
| 3936 | return 0; |
| 3937 | } |
| 3938 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3939 | static int rt5677_set_bias_level(struct snd_soc_codec *codec, |
| 3940 | enum snd_soc_bias_level level) |
| 3941 | { |
| 3942 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 3943 | |
| 3944 | switch (level) { |
| 3945 | case SND_SOC_BIAS_ON: |
| 3946 | break; |
| 3947 | |
| 3948 | case SND_SOC_BIAS_PREPARE: |
| 3949 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 3950 | rt5677_set_dsp_vad(codec, false); |
| 3951 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3952 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
| 3953 | RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, |
| 3954 | 0x0055); |
| 3955 | regmap_update_bits(rt5677->regmap, |
| 3956 | RT5677_PR_BASE + RT5677_BIAS_CUR4, |
| 3957 | 0x0f00, 0x0f00); |
| 3958 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
| 3959 | RT5677_PWR_VREF1 | RT5677_PWR_MB | |
| 3960 | RT5677_PWR_BG | RT5677_PWR_VREF2, |
| 3961 | RT5677_PWR_VREF1 | RT5677_PWR_MB | |
| 3962 | RT5677_PWR_BG | RT5677_PWR_VREF2); |
| 3963 | mdelay(20); |
| 3964 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
| 3965 | RT5677_PWR_FV1 | RT5677_PWR_FV2, |
| 3966 | RT5677_PWR_FV1 | RT5677_PWR_FV2); |
| 3967 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 3968 | RT5677_PWR_CORE, RT5677_PWR_CORE); |
| 3969 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, |
| 3970 | 0x1, 0x1); |
| 3971 | } |
| 3972 | break; |
| 3973 | |
| 3974 | case SND_SOC_BIAS_STANDBY: |
| 3975 | break; |
| 3976 | |
| 3977 | case SND_SOC_BIAS_OFF: |
| 3978 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); |
| 3979 | regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); |
| 3980 | regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); |
Oder Chiou | f18803a | 2014-07-07 15:37:00 +0800 | [diff] [blame] | 3981 | regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3982 | regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); |
| 3983 | regmap_update_bits(rt5677->regmap, |
| 3984 | RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 3985 | |
| 3986 | if (rt5677->dsp_vad_en) |
| 3987 | rt5677_set_dsp_vad(codec, true); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3988 | break; |
| 3989 | |
| 3990 | default: |
| 3991 | break; |
| 3992 | } |
| 3993 | codec->dapm.bias_level = level; |
| 3994 | |
| 3995 | return 0; |
| 3996 | } |
| 3997 | |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 3998 | #ifdef CONFIG_GPIOLIB |
| 3999 | static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip) |
| 4000 | { |
| 4001 | return container_of(chip, struct rt5677_priv, gpio_chip); |
| 4002 | } |
| 4003 | |
| 4004 | static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 4005 | { |
| 4006 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); |
| 4007 | |
| 4008 | switch (offset) { |
| 4009 | case RT5677_GPIO1 ... RT5677_GPIO5: |
| 4010 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 4011 | 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1)); |
| 4012 | break; |
| 4013 | |
| 4014 | case RT5677_GPIO6: |
| 4015 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, |
| 4016 | RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT); |
| 4017 | break; |
| 4018 | |
| 4019 | default: |
| 4020 | break; |
| 4021 | } |
| 4022 | } |
| 4023 | |
| 4024 | static int rt5677_gpio_direction_out(struct gpio_chip *chip, |
| 4025 | unsigned offset, int value) |
| 4026 | { |
| 4027 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); |
| 4028 | |
| 4029 | switch (offset) { |
| 4030 | case RT5677_GPIO1 ... RT5677_GPIO5: |
| 4031 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 4032 | 0x3 << (offset * 3 + 1), |
| 4033 | (0x2 | !!value) << (offset * 3 + 1)); |
| 4034 | break; |
| 4035 | |
| 4036 | case RT5677_GPIO6: |
| 4037 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, |
| 4038 | RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK, |
| 4039 | RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT); |
| 4040 | break; |
| 4041 | |
| 4042 | default: |
| 4043 | break; |
| 4044 | } |
| 4045 | |
| 4046 | return 0; |
| 4047 | } |
| 4048 | |
| 4049 | static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 4050 | { |
| 4051 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); |
| 4052 | int value, ret; |
| 4053 | |
| 4054 | ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); |
| 4055 | if (ret < 0) |
| 4056 | return ret; |
| 4057 | |
| 4058 | return (value & (0x1 << offset)) >> offset; |
| 4059 | } |
| 4060 | |
| 4061 | static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) |
| 4062 | { |
| 4063 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); |
| 4064 | |
| 4065 | switch (offset) { |
| 4066 | case RT5677_GPIO1 ... RT5677_GPIO5: |
| 4067 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 4068 | 0x1 << (offset * 3 + 2), 0x0); |
| 4069 | break; |
| 4070 | |
| 4071 | case RT5677_GPIO6: |
| 4072 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, |
| 4073 | RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); |
| 4074 | break; |
| 4075 | |
| 4076 | default: |
| 4077 | break; |
| 4078 | } |
| 4079 | |
| 4080 | return 0; |
| 4081 | } |
| 4082 | |
Anatol Pomozov | 40eb90a | 2014-10-10 20:46:36 -0700 | [diff] [blame] | 4083 | /** Configures the gpio as |
| 4084 | * 0 - floating |
| 4085 | * 1 - pull down |
| 4086 | * 2 - pull up |
| 4087 | */ |
| 4088 | static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, |
| 4089 | int value) |
| 4090 | { |
| 4091 | int shift; |
| 4092 | |
| 4093 | switch (offset) { |
| 4094 | case RT5677_GPIO1 ... RT5677_GPIO2: |
| 4095 | shift = 2 * (1 - offset); |
| 4096 | regmap_update_bits(rt5677->regmap, |
| 4097 | RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, |
| 4098 | 0x3 << shift, |
| 4099 | (value & 0x3) << shift); |
| 4100 | break; |
| 4101 | |
| 4102 | case RT5677_GPIO3 ... RT5677_GPIO6: |
| 4103 | shift = 2 * (9 - offset); |
| 4104 | regmap_update_bits(rt5677->regmap, |
| 4105 | RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, |
| 4106 | 0x3 << shift, |
| 4107 | (value & 0x3) << shift); |
| 4108 | break; |
| 4109 | |
| 4110 | default: |
| 4111 | break; |
| 4112 | } |
| 4113 | } |
| 4114 | |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4115 | static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) |
| 4116 | { |
| 4117 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); |
| 4118 | struct regmap_irq_chip_data *data = rt5677->irq_data; |
| 4119 | int irq; |
| 4120 | |
| 4121 | if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) { |
| 4122 | if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || |
| 4123 | (rt5677->pdata.jd1_gpio == 2 && |
| 4124 | offset == RT5677_GPIO2) || |
| 4125 | (rt5677->pdata.jd1_gpio == 3 && |
| 4126 | offset == RT5677_GPIO3)) { |
| 4127 | irq = RT5677_IRQ_JD1; |
| 4128 | } else { |
| 4129 | return -ENXIO; |
| 4130 | } |
| 4131 | } |
| 4132 | |
| 4133 | if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) { |
| 4134 | if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || |
| 4135 | (rt5677->pdata.jd2_gpio == 2 && |
| 4136 | offset == RT5677_GPIO5) || |
| 4137 | (rt5677->pdata.jd2_gpio == 3 && |
| 4138 | offset == RT5677_GPIO6)) { |
| 4139 | irq = RT5677_IRQ_JD2; |
| 4140 | } else if ((rt5677->pdata.jd3_gpio == 1 && |
| 4141 | offset == RT5677_GPIO4) || |
| 4142 | (rt5677->pdata.jd3_gpio == 2 && |
| 4143 | offset == RT5677_GPIO5) || |
| 4144 | (rt5677->pdata.jd3_gpio == 3 && |
| 4145 | offset == RT5677_GPIO6)) { |
| 4146 | irq = RT5677_IRQ_JD3; |
| 4147 | } else { |
| 4148 | return -ENXIO; |
| 4149 | } |
| 4150 | } |
| 4151 | |
| 4152 | return regmap_irq_get_virq(data, irq); |
| 4153 | } |
| 4154 | |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4155 | static struct gpio_chip rt5677_template_chip = { |
| 4156 | .label = "rt5677", |
| 4157 | .owner = THIS_MODULE, |
| 4158 | .direction_output = rt5677_gpio_direction_out, |
| 4159 | .set = rt5677_gpio_set, |
| 4160 | .direction_input = rt5677_gpio_direction_in, |
| 4161 | .get = rt5677_gpio_get, |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4162 | .to_irq = rt5677_to_irq, |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4163 | .can_sleep = 1, |
| 4164 | }; |
| 4165 | |
| 4166 | static void rt5677_init_gpio(struct i2c_client *i2c) |
| 4167 | { |
| 4168 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
| 4169 | int ret; |
| 4170 | |
| 4171 | rt5677->gpio_chip = rt5677_template_chip; |
| 4172 | rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; |
| 4173 | rt5677->gpio_chip.dev = &i2c->dev; |
| 4174 | rt5677->gpio_chip.base = -1; |
| 4175 | |
| 4176 | ret = gpiochip_add(&rt5677->gpio_chip); |
| 4177 | if (ret != 0) |
| 4178 | dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); |
| 4179 | } |
| 4180 | |
| 4181 | static void rt5677_free_gpio(struct i2c_client *i2c) |
| 4182 | { |
| 4183 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4184 | |
Axel Lin | 5d5e63a | 2014-09-17 20:58:02 +0800 | [diff] [blame] | 4185 | gpiochip_remove(&rt5677->gpio_chip); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4186 | } |
| 4187 | #else |
Anatol Pomozov | 45b6e1d | 2014-10-16 09:40:58 -0700 | [diff] [blame] | 4188 | static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, |
| 4189 | int value) |
| 4190 | { |
| 4191 | } |
| 4192 | |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4193 | static void rt5677_init_gpio(struct i2c_client *i2c) |
| 4194 | { |
| 4195 | } |
| 4196 | |
| 4197 | static void rt5677_free_gpio(struct i2c_client *i2c) |
| 4198 | { |
| 4199 | } |
| 4200 | #endif |
| 4201 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4202 | static int rt5677_probe(struct snd_soc_codec *codec) |
| 4203 | { |
| 4204 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Anatol Pomozov | 40eb90a | 2014-10-10 20:46:36 -0700 | [diff] [blame] | 4205 | int i; |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4206 | |
| 4207 | rt5677->codec = codec; |
| 4208 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 4209 | if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { |
| 4210 | snd_soc_dapm_add_routes(&codec->dapm, |
| 4211 | rt5677_dmic2_clk_2, |
| 4212 | ARRAY_SIZE(rt5677_dmic2_clk_2)); |
| 4213 | } else { /*use dmic1 clock by default*/ |
| 4214 | snd_soc_dapm_add_routes(&codec->dapm, |
| 4215 | rt5677_dmic2_clk_1, |
| 4216 | ARRAY_SIZE(rt5677_dmic2_clk_1)); |
| 4217 | } |
| 4218 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4219 | rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 4220 | |
| 4221 | regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); |
| 4222 | regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); |
| 4223 | |
Anatol Pomozov | 40eb90a | 2014-10-10 20:46:36 -0700 | [diff] [blame] | 4224 | for (i = 0; i < RT5677_GPIO_NUM; i++) |
| 4225 | rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); |
| 4226 | |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4227 | if (rt5677->irq_data) { |
| 4228 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000, |
| 4229 | 0x8000); |
| 4230 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018, |
| 4231 | 0x0008); |
| 4232 | |
| 4233 | if (rt5677->pdata.jd1_gpio) |
| 4234 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, |
| 4235 | RT5677_SEL_GPIO_JD1_MASK, |
| 4236 | rt5677->pdata.jd1_gpio << |
| 4237 | RT5677_SEL_GPIO_JD1_SFT); |
| 4238 | |
| 4239 | if (rt5677->pdata.jd2_gpio) |
| 4240 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, |
| 4241 | RT5677_SEL_GPIO_JD2_MASK, |
| 4242 | rt5677->pdata.jd2_gpio << |
| 4243 | RT5677_SEL_GPIO_JD2_SFT); |
| 4244 | |
| 4245 | if (rt5677->pdata.jd3_gpio) |
| 4246 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, |
| 4247 | RT5677_SEL_GPIO_JD3_MASK, |
| 4248 | rt5677->pdata.jd3_gpio << |
| 4249 | RT5677_SEL_GPIO_JD3_SFT); |
| 4250 | } |
| 4251 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4252 | mutex_init(&rt5677->dsp_cmd_lock); |
| 4253 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4254 | return 0; |
| 4255 | } |
| 4256 | |
| 4257 | static int rt5677_remove(struct snd_soc_codec *codec) |
| 4258 | { |
| 4259 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4260 | |
| 4261 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 4262 | if (gpio_is_valid(rt5677->pow_ldo2)) |
| 4263 | gpio_set_value_cansleep(rt5677->pow_ldo2, 0); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4264 | |
| 4265 | return 0; |
| 4266 | } |
| 4267 | |
| 4268 | #ifdef CONFIG_PM |
| 4269 | static int rt5677_suspend(struct snd_soc_codec *codec) |
| 4270 | { |
| 4271 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4272 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4273 | if (!rt5677->dsp_vad_en) { |
| 4274 | regcache_cache_only(rt5677->regmap, true); |
| 4275 | regcache_mark_dirty(rt5677->regmap); |
| 4276 | } |
| 4277 | |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 4278 | if (gpio_is_valid(rt5677->pow_ldo2)) |
| 4279 | gpio_set_value_cansleep(rt5677->pow_ldo2, 0); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4280 | |
| 4281 | return 0; |
| 4282 | } |
| 4283 | |
| 4284 | static int rt5677_resume(struct snd_soc_codec *codec) |
| 4285 | { |
| 4286 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4287 | |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 4288 | if (gpio_is_valid(rt5677->pow_ldo2)) { |
| 4289 | gpio_set_value_cansleep(rt5677->pow_ldo2, 1); |
| 4290 | msleep(10); |
| 4291 | } |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4292 | |
| 4293 | if (!rt5677->dsp_vad_en) { |
| 4294 | regcache_cache_only(rt5677->regmap, false); |
| 4295 | regcache_sync(rt5677->regmap); |
| 4296 | } |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4297 | |
| 4298 | return 0; |
| 4299 | } |
| 4300 | #else |
| 4301 | #define rt5677_suspend NULL |
| 4302 | #define rt5677_resume NULL |
| 4303 | #endif |
| 4304 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4305 | static int rt5677_read(void *context, unsigned int reg, unsigned int *val) |
| 4306 | { |
| 4307 | struct i2c_client *client = context; |
| 4308 | struct rt5677_priv *rt5677 = i2c_get_clientdata(client); |
| 4309 | |
| 4310 | if (rt5677->is_dsp_mode) |
| 4311 | rt5677_dsp_mode_i2c_read(rt5677, reg, val); |
| 4312 | else |
| 4313 | regmap_read(rt5677->regmap_physical, reg, val); |
| 4314 | |
| 4315 | return 0; |
| 4316 | } |
| 4317 | |
| 4318 | static int rt5677_write(void *context, unsigned int reg, unsigned int val) |
| 4319 | { |
| 4320 | struct i2c_client *client = context; |
| 4321 | struct rt5677_priv *rt5677 = i2c_get_clientdata(client); |
| 4322 | |
| 4323 | if (rt5677->is_dsp_mode) |
| 4324 | rt5677_dsp_mode_i2c_write(rt5677, reg, val); |
| 4325 | else |
| 4326 | regmap_write(rt5677->regmap_physical, reg, val); |
| 4327 | |
| 4328 | return 0; |
| 4329 | } |
| 4330 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4331 | #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 |
| 4332 | #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 4333 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) |
| 4334 | |
| 4335 | static struct snd_soc_dai_ops rt5677_aif_dai_ops = { |
| 4336 | .hw_params = rt5677_hw_params, |
| 4337 | .set_fmt = rt5677_set_dai_fmt, |
| 4338 | .set_sysclk = rt5677_set_dai_sysclk, |
| 4339 | .set_pll = rt5677_set_dai_pll, |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 4340 | .set_tdm_slot = rt5677_set_tdm_slot, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4341 | }; |
| 4342 | |
| 4343 | static struct snd_soc_dai_driver rt5677_dai[] = { |
| 4344 | { |
| 4345 | .name = "rt5677-aif1", |
| 4346 | .id = RT5677_AIF1, |
| 4347 | .playback = { |
| 4348 | .stream_name = "AIF1 Playback", |
| 4349 | .channels_min = 1, |
| 4350 | .channels_max = 2, |
| 4351 | .rates = RT5677_STEREO_RATES, |
| 4352 | .formats = RT5677_FORMATS, |
| 4353 | }, |
| 4354 | .capture = { |
| 4355 | .stream_name = "AIF1 Capture", |
| 4356 | .channels_min = 1, |
| 4357 | .channels_max = 2, |
| 4358 | .rates = RT5677_STEREO_RATES, |
| 4359 | .formats = RT5677_FORMATS, |
| 4360 | }, |
| 4361 | .ops = &rt5677_aif_dai_ops, |
| 4362 | }, |
| 4363 | { |
| 4364 | .name = "rt5677-aif2", |
| 4365 | .id = RT5677_AIF2, |
| 4366 | .playback = { |
| 4367 | .stream_name = "AIF2 Playback", |
| 4368 | .channels_min = 1, |
| 4369 | .channels_max = 2, |
| 4370 | .rates = RT5677_STEREO_RATES, |
| 4371 | .formats = RT5677_FORMATS, |
| 4372 | }, |
| 4373 | .capture = { |
| 4374 | .stream_name = "AIF2 Capture", |
| 4375 | .channels_min = 1, |
| 4376 | .channels_max = 2, |
| 4377 | .rates = RT5677_STEREO_RATES, |
| 4378 | .formats = RT5677_FORMATS, |
| 4379 | }, |
| 4380 | .ops = &rt5677_aif_dai_ops, |
| 4381 | }, |
| 4382 | { |
| 4383 | .name = "rt5677-aif3", |
| 4384 | .id = RT5677_AIF3, |
| 4385 | .playback = { |
| 4386 | .stream_name = "AIF3 Playback", |
| 4387 | .channels_min = 1, |
| 4388 | .channels_max = 2, |
| 4389 | .rates = RT5677_STEREO_RATES, |
| 4390 | .formats = RT5677_FORMATS, |
| 4391 | }, |
| 4392 | .capture = { |
| 4393 | .stream_name = "AIF3 Capture", |
| 4394 | .channels_min = 1, |
| 4395 | .channels_max = 2, |
| 4396 | .rates = RT5677_STEREO_RATES, |
| 4397 | .formats = RT5677_FORMATS, |
| 4398 | }, |
| 4399 | .ops = &rt5677_aif_dai_ops, |
| 4400 | }, |
| 4401 | { |
| 4402 | .name = "rt5677-aif4", |
| 4403 | .id = RT5677_AIF4, |
| 4404 | .playback = { |
| 4405 | .stream_name = "AIF4 Playback", |
| 4406 | .channels_min = 1, |
| 4407 | .channels_max = 2, |
| 4408 | .rates = RT5677_STEREO_RATES, |
| 4409 | .formats = RT5677_FORMATS, |
| 4410 | }, |
| 4411 | .capture = { |
| 4412 | .stream_name = "AIF4 Capture", |
| 4413 | .channels_min = 1, |
| 4414 | .channels_max = 2, |
| 4415 | .rates = RT5677_STEREO_RATES, |
| 4416 | .formats = RT5677_FORMATS, |
| 4417 | }, |
| 4418 | .ops = &rt5677_aif_dai_ops, |
| 4419 | }, |
| 4420 | { |
| 4421 | .name = "rt5677-slimbus", |
| 4422 | .id = RT5677_AIF5, |
| 4423 | .playback = { |
| 4424 | .stream_name = "SLIMBus Playback", |
| 4425 | .channels_min = 1, |
| 4426 | .channels_max = 2, |
| 4427 | .rates = RT5677_STEREO_RATES, |
| 4428 | .formats = RT5677_FORMATS, |
| 4429 | }, |
| 4430 | .capture = { |
| 4431 | .stream_name = "SLIMBus Capture", |
| 4432 | .channels_min = 1, |
| 4433 | .channels_max = 2, |
| 4434 | .rates = RT5677_STEREO_RATES, |
| 4435 | .formats = RT5677_FORMATS, |
| 4436 | }, |
| 4437 | .ops = &rt5677_aif_dai_ops, |
| 4438 | }, |
| 4439 | }; |
| 4440 | |
| 4441 | static struct snd_soc_codec_driver soc_codec_dev_rt5677 = { |
| 4442 | .probe = rt5677_probe, |
| 4443 | .remove = rt5677_remove, |
| 4444 | .suspend = rt5677_suspend, |
| 4445 | .resume = rt5677_resume, |
| 4446 | .set_bias_level = rt5677_set_bias_level, |
| 4447 | .idle_bias_off = true, |
| 4448 | .controls = rt5677_snd_controls, |
| 4449 | .num_controls = ARRAY_SIZE(rt5677_snd_controls), |
| 4450 | .dapm_widgets = rt5677_dapm_widgets, |
| 4451 | .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), |
| 4452 | .dapm_routes = rt5677_dapm_routes, |
| 4453 | .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), |
| 4454 | }; |
| 4455 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4456 | static const struct regmap_config rt5677_regmap_physical = { |
| 4457 | .name = "physical", |
| 4458 | .reg_bits = 8, |
| 4459 | .val_bits = 16, |
| 4460 | |
| 4461 | .max_register = RT5677_VENDOR_ID2 + 1, |
| 4462 | .readable_reg = rt5677_readable_register, |
| 4463 | |
| 4464 | .cache_type = REGCACHE_NONE, |
| 4465 | }; |
| 4466 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4467 | static const struct regmap_config rt5677_regmap = { |
| 4468 | .reg_bits = 8, |
| 4469 | .val_bits = 16, |
| 4470 | |
| 4471 | .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * |
| 4472 | RT5677_PR_SPACING), |
| 4473 | |
| 4474 | .volatile_reg = rt5677_volatile_register, |
| 4475 | .readable_reg = rt5677_readable_register, |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4476 | .reg_read = rt5677_read, |
| 4477 | .reg_write = rt5677_write, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4478 | |
| 4479 | .cache_type = REGCACHE_RBTREE, |
| 4480 | .reg_defaults = rt5677_reg, |
| 4481 | .num_reg_defaults = ARRAY_SIZE(rt5677_reg), |
| 4482 | .ranges = rt5677_ranges, |
| 4483 | .num_ranges = ARRAY_SIZE(rt5677_ranges), |
| 4484 | }; |
| 4485 | |
| 4486 | static const struct i2c_device_id rt5677_i2c_id[] = { |
| 4487 | { "rt5677", 0 }, |
| 4488 | { } |
| 4489 | }; |
| 4490 | MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); |
| 4491 | |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 4492 | static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np) |
| 4493 | { |
Anatol Pomozov | 6f67c38 | 2014-09-26 09:57:27 -0700 | [diff] [blame] | 4494 | rt5677->pdata.in1_diff = of_property_read_bool(np, |
| 4495 | "realtek,in1-differential"); |
| 4496 | rt5677->pdata.in2_diff = of_property_read_bool(np, |
| 4497 | "realtek,in2-differential"); |
| 4498 | rt5677->pdata.lout1_diff = of_property_read_bool(np, |
| 4499 | "realtek,lout1-differential"); |
| 4500 | rt5677->pdata.lout2_diff = of_property_read_bool(np, |
| 4501 | "realtek,lout2-differential"); |
| 4502 | rt5677->pdata.lout3_diff = of_property_read_bool(np, |
| 4503 | "realtek,lout3-differential"); |
| 4504 | |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 4505 | rt5677->pow_ldo2 = of_get_named_gpio(np, |
| 4506 | "realtek,pow-ldo2-gpio", 0); |
| 4507 | |
| 4508 | /* |
| 4509 | * POW_LDO2 is optional (it may be statically tied on the board). |
| 4510 | * -ENOENT means that the property doesn't exist, i.e. there is no |
| 4511 | * GPIO, so is not an error. Any other error code means the property |
| 4512 | * exists, but could not be parsed. |
| 4513 | */ |
| 4514 | if (!gpio_is_valid(rt5677->pow_ldo2) && |
| 4515 | (rt5677->pow_ldo2 != -ENOENT)) |
| 4516 | return rt5677->pow_ldo2; |
| 4517 | |
Anatol Pomozov | 40eb90a | 2014-10-10 20:46:36 -0700 | [diff] [blame] | 4518 | of_property_read_u8_array(np, "realtek,gpio-config", |
| 4519 | rt5677->pdata.gpio_config, RT5677_GPIO_NUM); |
| 4520 | |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4521 | of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio); |
| 4522 | of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio); |
| 4523 | of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio); |
| 4524 | |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 4525 | return 0; |
| 4526 | } |
| 4527 | |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4528 | static struct regmap_irq rt5677_irqs[] = { |
| 4529 | [RT5677_IRQ_JD1] = { |
| 4530 | .reg_offset = 0, |
| 4531 | .mask = RT5677_EN_IRQ_GPIO_JD1, |
| 4532 | }, |
| 4533 | [RT5677_IRQ_JD2] = { |
| 4534 | .reg_offset = 0, |
| 4535 | .mask = RT5677_EN_IRQ_GPIO_JD2, |
| 4536 | }, |
| 4537 | [RT5677_IRQ_JD3] = { |
| 4538 | .reg_offset = 0, |
| 4539 | .mask = RT5677_EN_IRQ_GPIO_JD3, |
| 4540 | }, |
| 4541 | }; |
| 4542 | |
| 4543 | static struct regmap_irq_chip rt5677_irq_chip = { |
| 4544 | .name = "rt5677", |
| 4545 | .irqs = rt5677_irqs, |
| 4546 | .num_irqs = ARRAY_SIZE(rt5677_irqs), |
| 4547 | |
| 4548 | .num_regs = 1, |
| 4549 | .status_base = RT5677_IRQ_CTRL1, |
| 4550 | .mask_base = RT5677_IRQ_CTRL1, |
| 4551 | .mask_invert = 1, |
| 4552 | }; |
| 4553 | |
kbuild test robot | 2d27deb | 2014-10-22 20:04:08 +0800 | [diff] [blame] | 4554 | static int rt5677_irq_init(struct i2c_client *i2c) |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4555 | { |
| 4556 | int ret; |
| 4557 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
| 4558 | |
| 4559 | if (!rt5677->pdata.jd1_gpio && |
| 4560 | !rt5677->pdata.jd2_gpio && |
| 4561 | !rt5677->pdata.jd3_gpio) |
| 4562 | return 0; |
| 4563 | |
| 4564 | if (!i2c->irq) { |
| 4565 | dev_err(&i2c->dev, "No interrupt specified\n"); |
| 4566 | return -EINVAL; |
| 4567 | } |
| 4568 | |
| 4569 | ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq, |
| 4570 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0, |
| 4571 | &rt5677_irq_chip, &rt5677->irq_data); |
| 4572 | |
| 4573 | if (ret != 0) { |
| 4574 | dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret); |
| 4575 | return ret; |
| 4576 | } |
| 4577 | |
| 4578 | return 0; |
| 4579 | } |
| 4580 | |
kbuild test robot | 2d27deb | 2014-10-22 20:04:08 +0800 | [diff] [blame] | 4581 | static void rt5677_irq_exit(struct i2c_client *i2c) |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4582 | { |
| 4583 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
| 4584 | |
| 4585 | if (rt5677->irq_data) |
| 4586 | regmap_del_irq_chip(i2c->irq, rt5677->irq_data); |
| 4587 | } |
| 4588 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4589 | static int rt5677_i2c_probe(struct i2c_client *i2c, |
| 4590 | const struct i2c_device_id *id) |
| 4591 | { |
| 4592 | struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev); |
| 4593 | struct rt5677_priv *rt5677; |
| 4594 | int ret; |
| 4595 | unsigned int val; |
| 4596 | |
| 4597 | rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), |
| 4598 | GFP_KERNEL); |
| 4599 | if (rt5677 == NULL) |
| 4600 | return -ENOMEM; |
| 4601 | |
| 4602 | i2c_set_clientdata(i2c, rt5677); |
| 4603 | |
| 4604 | if (pdata) |
| 4605 | rt5677->pdata = *pdata; |
| 4606 | |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 4607 | if (i2c->dev.of_node) { |
| 4608 | ret = rt5677_parse_dt(rt5677, i2c->dev.of_node); |
| 4609 | if (ret) { |
| 4610 | dev_err(&i2c->dev, "Failed to parse device tree: %d\n", |
| 4611 | ret); |
| 4612 | return ret; |
| 4613 | } |
| 4614 | } else { |
| 4615 | rt5677->pow_ldo2 = -EINVAL; |
| 4616 | } |
| 4617 | |
| 4618 | if (gpio_is_valid(rt5677->pow_ldo2)) { |
| 4619 | ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2, |
| 4620 | GPIOF_OUT_INIT_HIGH, |
| 4621 | "RT5677 POW_LDO2"); |
| 4622 | if (ret < 0) { |
| 4623 | dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n", |
| 4624 | rt5677->pow_ldo2, ret); |
| 4625 | return ret; |
| 4626 | } |
| 4627 | /* Wait a while until I2C bus becomes available. The datasheet |
| 4628 | * does not specify the exact we should wait but startup |
| 4629 | * sequence mentiones at least a few milliseconds. |
| 4630 | */ |
| 4631 | msleep(10); |
| 4632 | } |
| 4633 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4634 | rt5677->regmap_physical = devm_regmap_init_i2c(i2c, |
| 4635 | &rt5677_regmap_physical); |
| 4636 | if (IS_ERR(rt5677->regmap_physical)) { |
| 4637 | ret = PTR_ERR(rt5677->regmap_physical); |
| 4638 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", |
| 4639 | ret); |
| 4640 | return ret; |
| 4641 | } |
| 4642 | |
| 4643 | rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4644 | if (IS_ERR(rt5677->regmap)) { |
| 4645 | ret = PTR_ERR(rt5677->regmap); |
| 4646 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", |
| 4647 | ret); |
| 4648 | return ret; |
| 4649 | } |
| 4650 | |
| 4651 | regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); |
| 4652 | if (val != RT5677_DEVICE_ID) { |
| 4653 | dev_err(&i2c->dev, |
| 4654 | "Device with ID register %x is not rt5677\n", val); |
| 4655 | return -ENODEV; |
| 4656 | } |
| 4657 | |
| 4658 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); |
| 4659 | |
| 4660 | ret = regmap_register_patch(rt5677->regmap, init_list, |
| 4661 | ARRAY_SIZE(init_list)); |
| 4662 | if (ret != 0) |
| 4663 | dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); |
| 4664 | |
| 4665 | if (rt5677->pdata.in1_diff) |
| 4666 | regmap_update_bits(rt5677->regmap, RT5677_IN1, |
| 4667 | RT5677_IN_DF1, RT5677_IN_DF1); |
| 4668 | |
| 4669 | if (rt5677->pdata.in2_diff) |
| 4670 | regmap_update_bits(rt5677->regmap, RT5677_IN1, |
| 4671 | RT5677_IN_DF2, RT5677_IN_DF2); |
| 4672 | |
Anatol Pomozov | 6f67c38 | 2014-09-26 09:57:27 -0700 | [diff] [blame] | 4673 | if (rt5677->pdata.lout1_diff) |
| 4674 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, |
| 4675 | RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); |
| 4676 | |
| 4677 | if (rt5677->pdata.lout2_diff) |
| 4678 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, |
| 4679 | RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); |
| 4680 | |
| 4681 | if (rt5677->pdata.lout3_diff) |
| 4682 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, |
| 4683 | RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); |
| 4684 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 4685 | if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { |
| 4686 | regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, |
| 4687 | RT5677_GPIO5_FUNC_MASK, |
| 4688 | RT5677_GPIO5_FUNC_DMIC); |
| 4689 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 4690 | RT5677_GPIO5_DIR_MASK, |
| 4691 | RT5677_GPIO5_DIR_OUT); |
| 4692 | } |
| 4693 | |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4694 | rt5677_init_gpio(i2c); |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4695 | rt5677_irq_init(i2c); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4696 | |
Axel Lin | d0bdcb9 | 2014-06-10 11:37:24 +0800 | [diff] [blame] | 4697 | return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, |
| 4698 | rt5677_dai, ARRAY_SIZE(rt5677_dai)); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4699 | } |
| 4700 | |
| 4701 | static int rt5677_i2c_remove(struct i2c_client *i2c) |
| 4702 | { |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4703 | rt5677_irq_exit(i2c); |
| 4704 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4705 | snd_soc_unregister_codec(&i2c->dev); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4706 | rt5677_free_gpio(i2c); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4707 | |
| 4708 | return 0; |
| 4709 | } |
| 4710 | |
| 4711 | static struct i2c_driver rt5677_i2c_driver = { |
| 4712 | .driver = { |
| 4713 | .name = "rt5677", |
| 4714 | .owner = THIS_MODULE, |
| 4715 | }, |
| 4716 | .probe = rt5677_i2c_probe, |
| 4717 | .remove = rt5677_i2c_remove, |
| 4718 | .id_table = rt5677_i2c_id, |
| 4719 | }; |
Axel Lin | c8cfbec | 2014-06-03 10:56:41 +0800 | [diff] [blame] | 4720 | module_i2c_driver(rt5677_i2c_driver); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4721 | |
| 4722 | MODULE_DESCRIPTION("ASoC RT5677 driver"); |
| 4723 | MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); |
| 4724 | MODULE_LICENSE("GPL v2"); |