| Mika Westerberg | 5fae8b8 | 2014-10-24 15:16:52 +0300 | [diff] [blame] | 1 | # |
| 2 | # Intel pin control drivers |
| 3 | # |
| 4 | |
| 5 | config PINCTRL_BAYTRAIL |
| 6 | bool "Intel Baytrail GPIO pin control" |
| 7 | depends on GPIOLIB && ACPI |
| 8 | select GPIOLIB_IRQCHIP |
| 9 | help |
| 10 | driver for memory mapped GPIO functionality on Intel Baytrail |
| 11 | platforms. Supports 3 banks with 102, 28 and 44 gpios. |
| 12 | Most pins are usually muxed to some other functionality by firmware, |
| 13 | so only a small amount is available for gpio use. |
| 14 | |
| 15 | Requires ACPI device enumeration code to set up a platform device. |
| Mika Westerberg | 6e08d6b | 2014-11-03 13:01:33 +0200 | [diff] [blame] | 16 | |
| 17 | config PINCTRL_CHERRYVIEW |
| 18 | tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" |
| 19 | depends on ACPI |
| 20 | select PINMUX |
| 21 | select PINCONF |
| 22 | select GENERIC_PINCONF |
| 23 | select GPIOLIB |
| 24 | select GPIOLIB_IRQCHIP |
| 25 | help |
| 26 | Cherryview/Braswell pinctrl driver provides an interface that |
| 27 | allows configuring of SoC pins and using them as GPIOs. |
| Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 28 | |
| 29 | config PINCTRL_INTEL |
| 30 | tristate |
| 31 | select PINMUX |
| 32 | select PINCONF |
| 33 | select GENERIC_PINCONF |
| 34 | select GPIOLIB |
| 35 | select GPIOLIB_IRQCHIP |
| 36 | |
| 37 | config PINCTRL_SUNRISEPOINT |
| 38 | tristate "Intel Sunrisepoint pinctrl and GPIO driver" |
| 39 | depends on ACPI |
| 40 | select PINCTRL_INTEL |
| 41 | help |
| 42 | Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver |
| 43 | provides an interface that allows configuring of PCH pins and |
| 44 | using them as GPIOs. |