Kamil Debski | 9188473 | 2011-10-06 11:32:12 -0300 | [diff] [blame^] | 1 | /* |
| 2 | * Samsung S5P G2D - 2D Graphics Accelerator Driver |
| 3 | * |
| 4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 5 | * Kamil Debski, <k.debski@samsung.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the |
| 10 | * License, or (at your option) any later version |
| 11 | */ |
| 12 | |
| 13 | #include <linux/io.h> |
| 14 | |
| 15 | #include "g2d.h" |
| 16 | #include "g2d-regs.h" |
| 17 | |
| 18 | #define w(x, a) writel((x), d->regs + (a)) |
| 19 | #define r(a) readl(d->regs + (a)) |
| 20 | |
| 21 | /* g2d_reset clears all g2d registers */ |
| 22 | void g2d_reset(struct g2d_dev *d) |
| 23 | { |
| 24 | w(1, SOFT_RESET_REG); |
| 25 | } |
| 26 | |
| 27 | void g2d_set_src_size(struct g2d_dev *d, struct g2d_frame *f) |
| 28 | { |
| 29 | u32 n; |
| 30 | u32 stride; |
| 31 | |
| 32 | w(f->stride & 0xFFFF, SRC_STRIDE_REG); |
| 33 | |
| 34 | n = f->o_height & 0xFFF; |
| 35 | n <<= 16; |
| 36 | n |= f->o_width & 0xFFF; |
| 37 | w(n, SRC_LEFT_TOP_REG); |
| 38 | |
| 39 | n = f->bottom & 0xFFF; |
| 40 | n <<= 16; |
| 41 | n |= f->right & 0xFFF; |
| 42 | w(n, SRC_RIGHT_BOTTOM_REG); |
| 43 | |
| 44 | w(f->fmt->hw, SRC_COLOR_MODE_REG); |
| 45 | } |
| 46 | |
| 47 | void g2d_set_src_addr(struct g2d_dev *d, dma_addr_t a) |
| 48 | { |
| 49 | w(a, SRC_BASE_ADDR_REG); |
| 50 | } |
| 51 | |
| 52 | void g2d_set_dst_size(struct g2d_dev *d, struct g2d_frame *f) |
| 53 | { |
| 54 | u32 n; |
| 55 | u32 stride; |
| 56 | |
| 57 | w(f->stride & 0xFFFF, DST_STRIDE_REG); |
| 58 | |
| 59 | n = f->o_height & 0xFFF; |
| 60 | n <<= 16; |
| 61 | n |= f->o_width & 0xFFF; |
| 62 | w(n, DST_LEFT_TOP_REG); |
| 63 | |
| 64 | n = f->bottom & 0xFFF; |
| 65 | n <<= 16; |
| 66 | n |= f->right & 0xFFF; |
| 67 | w(n, DST_RIGHT_BOTTOM_REG); |
| 68 | |
| 69 | w(f->fmt->hw, DST_COLOR_MODE_REG); |
| 70 | } |
| 71 | |
| 72 | void g2d_set_dst_addr(struct g2d_dev *d, dma_addr_t a) |
| 73 | { |
| 74 | w(a, DST_BASE_ADDR_REG); |
| 75 | } |
| 76 | |
| 77 | void g2d_set_rop4(struct g2d_dev *d, u32 r) |
| 78 | { |
| 79 | w(r, ROP4_REG); |
| 80 | } |
| 81 | |
| 82 | u32 g2d_cmd_stretch(u32 e) |
| 83 | { |
| 84 | e &= 1; |
| 85 | return e << 4; |
| 86 | } |
| 87 | |
| 88 | void g2d_set_cmd(struct g2d_dev *d, u32 c) |
| 89 | { |
| 90 | w(c, BITBLT_COMMAND_REG); |
| 91 | } |
| 92 | |
| 93 | void g2d_start(struct g2d_dev *d) |
| 94 | { |
| 95 | /* Clear cache */ |
| 96 | w(0x7, CACHECTL_REG); |
| 97 | /* Enable interrupt */ |
| 98 | w(1, INTEN_REG); |
| 99 | /* Start G2D engine */ |
| 100 | w(1, BITBLT_START_REG); |
| 101 | } |
| 102 | |
| 103 | void g2d_clear_int(struct g2d_dev *d) |
| 104 | { |
| 105 | w(1, INTC_PEND_REG); |
| 106 | } |