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Sergey Matyukevich918d7b72009-06-19 08:27:40 +04001/*
2 * PATA driver for AT91SAM9260 Static Memory Controller
3 * with CompactFlash interface in True IDE mode
4 *
5 * Copyright (C) 2009 Matyukevich Sergey
6 *
7 * Based on:
8 * * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
9 * * pata_at32 driver by Kristoffer Nyborg Gregertsen
10 * * at91_ide driver by Stanislaw Gruszka
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2
14 * as published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/blkdev.h>
22#include <scsi/scsi_host.h>
23#include <linux/ata.h>
24#include <linux/clk.h>
25#include <linux/libata.h>
26#include <linux/platform_device.h>
27#include <linux/ata_platform.h>
28
29#include <mach/at91sam9260_matrix.h>
30#include <mach/at91sam9_smc.h>
31#include <mach/at91sam9260.h>
32#include <mach/board.h>
33#include <mach/gpio.h>
34
35
36#define DRV_NAME "pata_at91"
37#define DRV_VERSION "0.1"
38
39#define CF_IDE_OFFSET 0x00c00000
40#define CF_ALT_IDE_OFFSET 0x00e00000
41#define CF_IDE_RES_SIZE 0x08
42
43struct at91_ide_info {
44 unsigned long mode;
45 unsigned int cs;
46
47 void __iomem *ide_addr;
48 void __iomem *alt_addr;
49};
50
51const struct ata_timing initial_timing =
52 {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
53
54static unsigned int calc_mck_cycles(unsigned int ns, unsigned int mck_hz)
55{
56 unsigned long mul;
57
58 /*
59 * cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] =
60 * x * (f / 1_000_000_000) =
61 * x * ((f * 65536) / 1_000_000_000) / 65536 =
62 * x * (((f / 10_000) * 65536) / 100_000) / 65536 =
63 */
64
65 mul = (mck_hz / 10000) << 16;
66 mul /= 100000;
67
68 return (ns * mul + 65536) >> 16; /* rounding */
69}
70
71static void set_smc_mode(struct at91_ide_info *info)
72{
73 at91_sys_write(AT91_SMC_MODE(info->cs), info->mode);
74 return;
75}
76
77static void set_smc_timing(struct device *dev,
78 struct at91_ide_info *info, const struct ata_timing *ata)
79{
80 int read_cycle, write_cycle, active, recover;
81 int nrd_setup, nrd_pulse, nrd_recover;
82 int nwe_setup, nwe_pulse;
83
84 int ncs_write_setup, ncs_write_pulse;
85 int ncs_read_setup, ncs_read_pulse;
86
87 unsigned int mck_hz;
88 struct clk *mck;
89
90 read_cycle = ata->cyc8b;
91 nrd_setup = ata->setup;
92 nrd_pulse = ata->act8b;
93 nrd_recover = ata->rec8b;
94
95 mck = clk_get(NULL, "mck");
96 BUG_ON(IS_ERR(mck));
97 mck_hz = clk_get_rate(mck);
98
99 read_cycle = calc_mck_cycles(read_cycle, mck_hz);
100 nrd_setup = calc_mck_cycles(nrd_setup, mck_hz);
101 nrd_pulse = calc_mck_cycles(nrd_pulse, mck_hz);
102 nrd_recover = calc_mck_cycles(nrd_recover, mck_hz);
103
104 clk_put(mck);
105
106 active = nrd_setup + nrd_pulse;
107 recover = read_cycle - active;
108
109 /* Need at least two cycles recovery */
110 if (recover < 2)
111 read_cycle = active + 2;
112
113 /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
114 ncs_read_setup = 1;
115 ncs_read_pulse = read_cycle - 2;
116
117 /* Write timings same as read timings */
118 write_cycle = read_cycle;
119 nwe_setup = nrd_setup;
120 nwe_pulse = nrd_pulse;
121 ncs_write_setup = ncs_read_setup;
122 ncs_write_pulse = ncs_read_pulse;
123
124 dev_dbg(dev, "ATA timings: nrd_setup = %d nrd_pulse = %d nrd_cycle = %d\n",
125 nrd_setup, nrd_pulse, read_cycle);
126 dev_dbg(dev, "ATA timings: nwe_setup = %d nwe_pulse = %d nwe_cycle = %d\n",
127 nwe_setup, nwe_pulse, write_cycle);
128 dev_dbg(dev, "ATA timings: ncs_read_setup = %d ncs_read_pulse = %d\n",
129 ncs_read_setup, ncs_read_pulse);
130 dev_dbg(dev, "ATA timings: ncs_write_setup = %d ncs_write_pulse = %d\n",
131 ncs_write_setup, ncs_write_pulse);
132
133 at91_sys_write(AT91_SMC_SETUP(info->cs),
134 AT91_SMC_NWESETUP_(nwe_setup) |
135 AT91_SMC_NRDSETUP_(nrd_setup) |
136 AT91_SMC_NCS_WRSETUP_(ncs_write_setup) |
137 AT91_SMC_NCS_RDSETUP_(ncs_read_setup));
138
139 at91_sys_write(AT91_SMC_PULSE(info->cs),
140 AT91_SMC_NWEPULSE_(nwe_pulse) |
141 AT91_SMC_NRDPULSE_(nrd_pulse) |
142 AT91_SMC_NCS_WRPULSE_(ncs_write_pulse) |
143 AT91_SMC_NCS_RDPULSE_(ncs_read_pulse));
144
145 at91_sys_write(AT91_SMC_CYCLE(info->cs),
146 AT91_SMC_NWECYCLE_(write_cycle) |
147 AT91_SMC_NRDCYCLE_(read_cycle));
148
149 return;
150}
151
152static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
153{
154 struct at91_ide_info *info = ap->host->private_data;
155 struct ata_timing timing;
156 int ret;
157
158 /* Compute ATA timing and set it to SMC */
159 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
160 if (ret) {
161 dev_warn(ap->dev, "Failed to compute ATA timing %d, \
162 set PIO_0 timing\n", ret);
163 set_smc_timing(ap->dev, info, &initial_timing);
164 } else {
165 set_smc_timing(ap->dev, info, &timing);
166 }
167
168 /* Setup SMC mode */
169 set_smc_mode(info);
170
171 return;
172}
173
174static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
175 unsigned char *buf, unsigned int buflen, int rw)
176{
177 struct at91_ide_info *info = dev->link->ap->host->private_data;
178 unsigned int consumed;
179 unsigned long flags;
180 unsigned int mode;
181
182 local_irq_save(flags);
183 mode = at91_sys_read(AT91_SMC_MODE(info->cs));
184
185 /* set 16bit mode before writing data */
186 at91_sys_write(AT91_SMC_MODE(info->cs),
187 (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16);
188
189 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
190
191 /* restore 8bit mode after data is written */
192 at91_sys_write(AT91_SMC_MODE(info->cs),
193 (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8);
194
195 local_irq_restore(flags);
196 return consumed;
197}
198
199static struct scsi_host_template pata_at91_sht = {
200 ATA_PIO_SHT(DRV_NAME),
201};
202
203static struct ata_port_operations pata_at91_port_ops = {
204 .inherits = &ata_sff_port_ops,
205
206 .sff_data_xfer = pata_at91_data_xfer_noirq,
207 .set_piomode = pata_at91_set_piomode,
208 .cable_detect = ata_cable_40wire,
209 .port_start = ATA_OP_NULL,
210};
211
212static int __devinit pata_at91_probe(struct platform_device *pdev)
213{
214 struct at91_cf_data *board = pdev->dev.platform_data;
215 struct device *dev = &pdev->dev;
216 struct at91_ide_info *info;
217 struct resource *mem_res;
218 struct ata_host *host;
219 struct ata_port *ap;
220 int irq_flags = 0;
221 int irq = 0;
222 int ret;
223
224 /* get platform resources: IO/CTL memories and irq/rst pins */
225
226 if (pdev->num_resources != 1) {
227 dev_err(&pdev->dev, "invalid number of resources\n");
228 return -EINVAL;
229 }
230
231 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
232
233 if (!mem_res) {
234 dev_err(dev, "failed to get mem resource\n");
235 return -EINVAL;
236 }
237
238 irq = board->irq_pin;
239
240 /* init ata host */
241
242 host = ata_host_alloc(dev, 1);
243
244 if (!host)
245 return -ENOMEM;
246
247 ap = host->ports[0];
248 ap->ops = &pata_at91_port_ops;
249 ap->flags |= ATA_FLAG_SLAVE_POSS;
250 ap->pio_mask = ATA_PIO4;
251
252 if (!irq) {
253 ap->flags |= ATA_FLAG_PIO_POLLING;
254 ata_port_desc(ap, "no IRQ, using PIO polling");
255 }
256
257 info = kzalloc(sizeof(*info), GFP_KERNEL);
258
259 if (!info) {
260 dev_err(dev, "failed to allocate memory for private data\n");
261 return -ENOMEM;
262 }
263
264 info->cs = board->chipselect;
265 info->mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
266 AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT |
267 AT91_SMC_DBW_8 | AT91_SMC_TDF_(0);
268
269 info->ide_addr = devm_ioremap(dev,
270 mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE);
271
272 if (!info->ide_addr) {
273 dev_err(dev, "failed to map IO base\n");
274 ret = -ENOMEM;
275 goto err_ide_ioremap;
276 }
277
278 info->alt_addr = devm_ioremap(dev,
279 mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE);
280
281 if (!info->alt_addr) {
282 dev_err(dev, "failed to map CTL base\n");
283 ret = -ENOMEM;
284 goto err_alt_ioremap;
285 }
286
287 ap->ioaddr.cmd_addr = info->ide_addr;
288 ap->ioaddr.ctl_addr = info->alt_addr + 0x06;
289 ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
290
291 ata_sff_std_ports(&ap->ioaddr);
292
293 ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx",
294 (unsigned long long)mem_res->start + CF_IDE_OFFSET,
295 (unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET);
296
297 host->private_data = info;
298
299 return ata_host_activate(host, irq ? gpio_to_irq(irq) : 0,
300 irq ? ata_sff_interrupt : NULL,
301 irq_flags, &pata_at91_sht);
302
303err_alt_ioremap:
304 devm_iounmap(dev, info->ide_addr);
305
306err_ide_ioremap:
307 kfree(info);
308
309 return ret;
310}
311
312static int __devexit pata_at91_remove(struct platform_device *pdev)
313{
314 struct ata_host *host = dev_get_drvdata(&pdev->dev);
315 struct at91_ide_info *info = host->private_data;
316 struct device *dev = &pdev->dev;
317
318 if (!host)
319 return 0;
320
321 ata_host_detach(host);
322
323 if (!info)
324 return 0;
325
326 devm_iounmap(dev, info->ide_addr);
327 devm_iounmap(dev, info->alt_addr);
328
329 kfree(info);
330 return 0;
331}
332
333static struct platform_driver pata_at91_driver = {
334 .probe = pata_at91_probe,
335 .remove = __devexit_p(pata_at91_remove),
336 .driver = {
337 .name = DRV_NAME,
338 .owner = THIS_MODULE,
339 },
340};
341
342static int __init pata_at91_init(void)
343{
344 return platform_driver_register(&pata_at91_driver);
345}
346
347static void __exit pata_at91_exit(void)
348{
349 platform_driver_unregister(&pata_at91_driver);
350}
351
352
353module_init(pata_at91_init);
354module_exit(pata_at91_exit);
355
356
357MODULE_LICENSE("GPL");
358MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC");
359MODULE_AUTHOR("Matyukevich Sergey");
360MODULE_VERSION(DRV_VERSION);
361