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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifdef __KERNEL__
2#ifndef _ASM_IRQ_H
3#define _ASM_IRQ_H
4
5#include <linux/config.h>
6#include <asm/machdep.h> /* ppc_md */
7#include <asm/atomic.h>
8
9/*
10 * These constants are used for passing information about interrupt
11 * signal polarity and level/edge sensing to the low-level PIC chip
12 * drivers.
13 */
14#define IRQ_SENSE_MASK 0x1
15#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
16#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
17
18#define IRQ_POLARITY_MASK 0x2
19#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
20#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
21
22#if defined(CONFIG_40x)
23#include <asm/ibm4xx.h>
24
25#ifndef NR_BOARD_IRQS
26#define NR_BOARD_IRQS 0
27#endif
28
29#ifndef UIC_WIDTH /* Number of interrupts per device */
30#define UIC_WIDTH 32
31#endif
32
33#ifndef NR_UICS /* number of UIC devices */
34#define NR_UICS 1
35#endif
36
37#if defined (CONFIG_403)
38/*
39 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
40 * 32 possible interrupts, a majority of which are not implemented on
41 * all cores. There are six configurable, external interrupt pins and
42 * there are eight internal interrupts for the on-chip serial port
43 * (SPU), DMA controller, and JTAG controller.
44 *
45 */
46
47#define NR_AIC_IRQS 32
48#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
49
50#elif !defined (CONFIG_403)
51
52/*
53 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
54 * possible interrupts as well. There are seven, configurable external
55 * interrupt pins and there are 17 internal interrupts for the on-chip
56 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
57 *
58 */
59
60
61#define NR_UIC_IRQS UIC_WIDTH
62#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
63#endif
64static __inline__ int
65irq_canonicalize(int irq)
66{
67 return (irq);
68}
69
70#elif defined(CONFIG_44x)
71#include <asm/ibm44x.h>
72
73#define NR_UIC_IRQS 32
74#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
75
76static __inline__ int
77irq_canonicalize(int irq)
78{
79 return (irq);
80}
81
82#elif defined(CONFIG_8xx)
83
84/* Now include the board configuration specific associations.
85*/
86#include <asm/mpc8xx.h>
87
88/* The MPC8xx cores have 16 possible interrupts. There are eight
89 * possible level sensitive interrupts assigned and generated internally
90 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
91 * There are eight external interrupts (IRQs) that can be configured
92 * as either level or edge sensitive.
93 *
94 * On some implementations, there is also the possibility of an 8259
95 * through the PCI and PCI-ISA bridges.
96 *
97 * We are "flattening" the interrupt vectors of the cascaded CPM
98 * and 8259 interrupt controllers so that we can uniquely identify
99 * any interrupt source with a single integer.
100 */
101#define NR_SIU_INTS 16
102#define NR_CPM_INTS 32
103#ifndef NR_8259_INTS
104#define NR_8259_INTS 0
105#endif
106
107#define SIU_IRQ_OFFSET 0
108#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
109#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
110
111#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
112
113/* These values must be zero-based and map 1:1 with the SIU configuration.
114 * They are used throughout the 8xx I/O subsystem to generate
115 * interrupt masks, flags, and other control patterns. This is why the
116 * current kernel assumption of the 8259 as the base controller is such
117 * a pain in the butt.
118 */
119#define SIU_IRQ0 (0) /* Highest priority */
120#define SIU_LEVEL0 (1)
121#define SIU_IRQ1 (2)
122#define SIU_LEVEL1 (3)
123#define SIU_IRQ2 (4)
124#define SIU_LEVEL2 (5)
125#define SIU_IRQ3 (6)
126#define SIU_LEVEL3 (7)
127#define SIU_IRQ4 (8)
128#define SIU_LEVEL4 (9)
129#define SIU_IRQ5 (10)
130#define SIU_LEVEL5 (11)
131#define SIU_IRQ6 (12)
132#define SIU_LEVEL6 (13)
133#define SIU_IRQ7 (14)
134#define SIU_LEVEL7 (15)
135
136/* The internal interrupts we can configure as we see fit.
137 * My personal preference is CPM at level 2, which puts it above the
138 * MBX PCI/ISA/IDE interrupts.
139 */
140#ifndef PIT_INTERRUPT
141#define PIT_INTERRUPT SIU_LEVEL0
142#endif
143#ifndef CPM_INTERRUPT
144#define CPM_INTERRUPT SIU_LEVEL2
145#endif
146#ifndef PCMCIA_INTERRUPT
147#define PCMCIA_INTERRUPT SIU_LEVEL6
148#endif
149#ifndef DEC_INTERRUPT
150#define DEC_INTERRUPT SIU_LEVEL7
151#endif
152
153/* Some internal interrupt registers use an 8-bit mask for the interrupt
154 * level instead of a number.
155 */
156#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
157
158/* always the same on 8xx -- Cort */
159static __inline__ int irq_canonicalize(int irq)
160{
161 return irq;
162}
163
164#elif defined(CONFIG_83xx)
165#include <asm/mpc83xx.h>
166
167static __inline__ int irq_canonicalize(int irq)
168{
169 return irq;
170}
171
172#define NR_IRQS (NR_IPIC_INTS)
173
174#elif defined(CONFIG_85xx)
175/* Now include the board configuration specific associations.
176*/
177#include <asm/mpc85xx.h>
178
Kumar Gala65145e02005-06-21 17:15:25 -0700179/* The MPC8548 openpic has 48 internal interrupts and 12 external
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 * interrupts.
181 *
182 * We are "flattening" the interrupt vectors of the cascaded CPM
183 * so that we can uniquely identify any interrupt source with a
184 * single integer.
185 */
186#define NR_CPM_INTS 64
Kumar Gala65145e02005-06-21 17:15:25 -0700187#define NR_EPIC_INTS 60
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188#ifndef NR_8259_INTS
189#define NR_8259_INTS 0
190#endif
191#define NUM_8259_INTERRUPTS NR_8259_INTS
192
193#ifndef CPM_IRQ_OFFSET
194#define CPM_IRQ_OFFSET 0
195#endif
196
197#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
198
199/* Internal IRQs on MPC85xx OpenPIC */
200
201#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
202#ifdef CONFIG_CPM2
203#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
204#else
205#define MPC85xx_OPENPIC_IRQ_OFFSET 0
206#endif
207#endif
208
209/* Not all of these exist on all MPC85xx implementations */
210#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
211#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
212#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
213#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
214#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
215#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
216#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
217#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
218#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
219#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
220#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
221#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
222#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
223#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
224#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
225#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
Kumar Gala5b37b702005-06-21 17:15:18 -0700226#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
227#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
228#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
230#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
231#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
Kumar Gala5b37b702005-06-21 17:15:18 -0700232#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
233#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
234#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
236#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
237#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
238#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
239#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
240#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
241#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
242
243/* The 12 external interrupt lines */
Kumar Gala65145e02005-06-21 17:15:25 -0700244#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
245#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
246#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
247#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
248#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
249#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
250#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
251#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
252#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
253#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
254#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
255#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256
257/* CPM related interrupts */
258#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
259#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
260#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
261#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
262#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
263#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
264#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
265#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
266#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
267#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
268#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
269#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
270#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
271#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
272#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
273#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
274#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
275#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
276#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
277#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
278#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
279#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
280#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
281#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
282#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
283#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
284#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
285#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
286#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
287#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
288#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
289#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
290#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
291#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
292#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
293#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
294
295static __inline__ int irq_canonicalize(int irq)
296{
297 return irq;
298}
299
300#else /* CONFIG_40x + CONFIG_8xx */
301/*
302 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
303 * so it is the max of them all
304 */
305#define NR_IRQS 256
306
307#ifndef CONFIG_8260
308
309#define NUM_8259_INTERRUPTS 16
310
311#else /* CONFIG_8260 */
312
313/* The 8260 has an internal interrupt controller with a maximum of
314 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
315 * Don't be confused by the 8260 documentation where they list an
316 * "interrupt number" and "interrupt vector". We are only interested
317 * in the interrupt vector. There are "reserved" holes where the
318 * vector number increases, but the interrupt number in the table does not.
319 * (Document errata updates have fixed this...make sure you have up to
320 * date processor documentation -- Dan).
321 */
322
323#ifndef CPM_IRQ_OFFSET
324#define CPM_IRQ_OFFSET 0
325#endif
326
327#define NR_CPM_INTS 64
328
329#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
330#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
331#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
332#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
333#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
334#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
335#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
336#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
337#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
338#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
339#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
340#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
341#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
342#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
343#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
344#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
345#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
346#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
347#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
348#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
349#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
350#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
351#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
352#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
353#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
354#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
355#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
356#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
357#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
358#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
359#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
360#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
361#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
362#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
363#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
364#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
365#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
366#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
367#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
368#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
369#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
370#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
371#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
372#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
373#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
374#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
375#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
376#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
377#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
378
379#endif /* CONFIG_8260 */
380
381/*
382 * This gets called from serial.c, which is now used on
383 * powermacs as well as prep/chrp boxes.
384 * Prep and chrp both have cascaded 8259 PICs.
385 */
386static __inline__ int irq_canonicalize(int irq)
387{
388 if (ppc_md.irq_canonicalize)
389 return ppc_md.irq_canonicalize(irq);
390 return irq;
391}
392
393#endif
394
395#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
396/* pedantic: these are long because they are used with set_bit --RR */
397extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
398extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
399extern atomic_t ppc_n_lost_interrupts;
400
401struct irqaction;
402struct pt_regs;
403int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
404
405#endif /* _ASM_IRQ_H */
406#endif /* __KERNEL__ */