Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2008-2009 MontaVista Software Inc. |
| 3 | * Copyright (C) 2008-2009 Texas Instruments Inc |
| 4 | * |
| 5 | * Based on the LCD driver for TI Avalanche processors written by |
| 6 | * Ajay Singh and Shalom Hai. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option)any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/kernel.h> |
| 24 | #include <linux/fb.h> |
| 25 | #include <linux/dma-mapping.h> |
| 26 | #include <linux/device.h> |
| 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/uaccess.h> |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/clk.h> |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 31 | #include <linux/cpufreq.h> |
Chaithrika U S | 1d3c6c7 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 32 | #include <linux/console.h> |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 33 | #include <linux/spinlock.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Aditya Nellutla | 3b9cc4e | 2012-05-23 11:36:31 +0530 | [diff] [blame] | 35 | #include <linux/lcm.h> |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 36 | #include <video/da8xx-fb.h> |
Manjunathappa, Prakash | 12fa835 | 2012-02-09 11:54:06 +0530 | [diff] [blame] | 37 | #include <asm/div64.h> |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 38 | |
| 39 | #define DRIVER_NAME "da8xx_lcdc" |
| 40 | |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 41 | #define LCD_VERSION_1 1 |
| 42 | #define LCD_VERSION_2 2 |
| 43 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 44 | /* LCD Status Register */ |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 45 | #define LCD_END_OF_FRAME1 BIT(9) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 46 | #define LCD_END_OF_FRAME0 BIT(8) |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 47 | #define LCD_PL_LOAD_DONE BIT(6) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 48 | #define LCD_FIFO_UNDERFLOW BIT(5) |
| 49 | #define LCD_SYNC_LOST BIT(2) |
| 50 | |
| 51 | /* LCD DMA Control Register */ |
| 52 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) |
| 53 | #define LCD_DMA_BURST_1 0x0 |
| 54 | #define LCD_DMA_BURST_2 0x1 |
| 55 | #define LCD_DMA_BURST_4 0x2 |
| 56 | #define LCD_DMA_BURST_8 0x3 |
| 57 | #define LCD_DMA_BURST_16 0x4 |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 58 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
| 59 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) |
| 60 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 61 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
| 62 | |
| 63 | /* LCD Control Register */ |
| 64 | #define LCD_CLK_DIVISOR(x) ((x) << 8) |
| 65 | #define LCD_RASTER_MODE 0x01 |
| 66 | |
| 67 | /* LCD Raster Control Register */ |
| 68 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) |
| 69 | #define PALETTE_AND_DATA 0x00 |
| 70 | #define PALETTE_ONLY 0x01 |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 71 | #define DATA_ONLY 0x02 |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 72 | |
| 73 | #define LCD_MONO_8BIT_MODE BIT(9) |
| 74 | #define LCD_RASTER_ORDER BIT(8) |
| 75 | #define LCD_TFT_MODE BIT(7) |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 76 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
| 77 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) |
| 78 | #define LCD_V1_PL_INT_ENA BIT(4) |
| 79 | #define LCD_V2_PL_INT_ENA BIT(6) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 80 | #define LCD_MONOCHROME_MODE BIT(1) |
| 81 | #define LCD_RASTER_ENABLE BIT(0) |
| 82 | #define LCD_TFT_ALT_ENABLE BIT(23) |
| 83 | #define LCD_STN_565_ENABLE BIT(24) |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 84 | #define LCD_V2_DMA_CLK_EN BIT(2) |
| 85 | #define LCD_V2_LIDD_CLK_EN BIT(1) |
| 86 | #define LCD_V2_CORE_CLK_EN BIT(0) |
| 87 | #define LCD_V2_LPP_B10 26 |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 88 | |
| 89 | /* LCD Raster Timing 2 Register */ |
| 90 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) |
| 91 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) |
| 92 | #define LCD_SYNC_CTRL BIT(25) |
| 93 | #define LCD_SYNC_EDGE BIT(24) |
| 94 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) |
| 95 | #define LCD_INVERT_LINE_CLOCK BIT(21) |
| 96 | #define LCD_INVERT_FRAME_CLOCK BIT(20) |
| 97 | |
| 98 | /* LCD Block */ |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 99 | #define LCD_PID_REG 0x0 |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 100 | #define LCD_CTRL_REG 0x4 |
| 101 | #define LCD_STAT_REG 0x8 |
| 102 | #define LCD_RASTER_CTRL_REG 0x28 |
| 103 | #define LCD_RASTER_TIMING_0_REG 0x2C |
| 104 | #define LCD_RASTER_TIMING_1_REG 0x30 |
| 105 | #define LCD_RASTER_TIMING_2_REG 0x34 |
| 106 | #define LCD_DMA_CTRL_REG 0x40 |
| 107 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 |
| 108 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 109 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
| 110 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 |
| 111 | |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 112 | /* Interrupt Registers available only in Version 2 */ |
| 113 | #define LCD_RAW_STAT_REG 0x58 |
| 114 | #define LCD_MASKED_STAT_REG 0x5c |
| 115 | #define LCD_INT_ENABLE_SET_REG 0x60 |
| 116 | #define LCD_INT_ENABLE_CLR_REG 0x64 |
| 117 | #define LCD_END_OF_INT_IND_REG 0x68 |
| 118 | |
| 119 | /* Clock registers available only on Version 2 */ |
| 120 | #define LCD_CLK_ENABLE_REG 0x6c |
| 121 | #define LCD_CLK_RESET_REG 0x70 |
Manjunathappa, Prakash | 74a0efd | 2011-11-15 17:32:23 +0530 | [diff] [blame] | 122 | #define LCD_CLK_MAIN_RESET BIT(3) |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 123 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 124 | #define LCD_NUM_BUFFERS 2 |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 125 | |
| 126 | #define WSI_TIMEOUT 50 |
| 127 | #define PALETTE_SIZE 256 |
| 128 | #define LEFT_MARGIN 64 |
| 129 | #define RIGHT_MARGIN 64 |
| 130 | #define UPPER_MARGIN 32 |
| 131 | #define LOWER_MARGIN 32 |
| 132 | |
| 133 | static resource_size_t da8xx_fb_reg_base; |
| 134 | static struct resource *lcdc_regs; |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 135 | static unsigned int lcd_revision; |
| 136 | static irq_handler_t lcdc_irq_handler; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 137 | |
| 138 | static inline unsigned int lcdc_read(unsigned int addr) |
| 139 | { |
| 140 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); |
| 141 | } |
| 142 | |
| 143 | static inline void lcdc_write(unsigned int val, unsigned int addr) |
| 144 | { |
| 145 | __raw_writel(val, da8xx_fb_reg_base + (addr)); |
| 146 | } |
| 147 | |
| 148 | struct da8xx_fb_par { |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 149 | resource_size_t p_palette_base; |
| 150 | unsigned char *v_palette_base; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 151 | dma_addr_t vram_phys; |
| 152 | unsigned long vram_size; |
| 153 | void *vram_virt; |
| 154 | unsigned int dma_start; |
| 155 | unsigned int dma_end; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 156 | struct clk *lcdc_clk; |
| 157 | int irq; |
| 158 | unsigned short pseudo_palette[16]; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 159 | unsigned int palette_sz; |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 160 | unsigned int pxl_clk; |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 161 | int blank; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 162 | wait_queue_head_t vsync_wait; |
| 163 | int vsync_flag; |
| 164 | int vsync_timeout; |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 165 | spinlock_t lock_for_chan_update; |
| 166 | |
| 167 | /* |
| 168 | * LCDC has 2 ping pong DMA channels, channel 0 |
| 169 | * and channel 1. |
| 170 | */ |
| 171 | unsigned int which_dma_channel_done; |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 172 | #ifdef CONFIG_CPU_FREQ |
| 173 | struct notifier_block freq_transition; |
Manjunathappa, Prakash | f820917 | 2012-01-03 18:10:51 +0530 | [diff] [blame] | 174 | unsigned int lcd_fck_rate; |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 175 | #endif |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 176 | void (*panel_power_ctrl)(int); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 177 | }; |
| 178 | |
| 179 | /* Variable Screen Information */ |
| 180 | static struct fb_var_screeninfo da8xx_fb_var __devinitdata = { |
| 181 | .xoffset = 0, |
| 182 | .yoffset = 0, |
| 183 | .transp = {0, 0, 0}, |
| 184 | .nonstd = 0, |
| 185 | .activate = 0, |
| 186 | .height = -1, |
| 187 | .width = -1, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 188 | .accel_flags = 0, |
| 189 | .left_margin = LEFT_MARGIN, |
| 190 | .right_margin = RIGHT_MARGIN, |
| 191 | .upper_margin = UPPER_MARGIN, |
| 192 | .lower_margin = LOWER_MARGIN, |
| 193 | .sync = 0, |
| 194 | .vmode = FB_VMODE_NONINTERLACED |
| 195 | }; |
| 196 | |
| 197 | static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = { |
| 198 | .id = "DA8xx FB Drv", |
| 199 | .type = FB_TYPE_PACKED_PIXELS, |
| 200 | .type_aux = 0, |
| 201 | .visual = FB_VISUAL_PSEUDOCOLOR, |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 202 | .xpanstep = 0, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 203 | .ypanstep = 1, |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 204 | .ywrapstep = 0, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 205 | .accel = FB_ACCEL_NONE |
| 206 | }; |
| 207 | |
| 208 | struct da8xx_panel { |
| 209 | const char name[25]; /* Full name <vendor>_<model> */ |
| 210 | unsigned short width; |
| 211 | unsigned short height; |
| 212 | int hfp; /* Horizontal front porch */ |
| 213 | int hbp; /* Horizontal back porch */ |
| 214 | int hsw; /* Horizontal Sync Pulse Width */ |
| 215 | int vfp; /* Vertical front porch */ |
| 216 | int vbp; /* Vertical back porch */ |
| 217 | int vsw; /* Vertical Sync Pulse Width */ |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 218 | unsigned int pxl_clk; /* Pixel clock */ |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 219 | unsigned char invert_pxl_clk; /* Invert Pixel clock */ |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 220 | }; |
| 221 | |
| 222 | static struct da8xx_panel known_lcd_panels[] = { |
| 223 | /* Sharp LCD035Q3DG01 */ |
| 224 | [0] = { |
| 225 | .name = "Sharp_LCD035Q3DG01", |
| 226 | .width = 320, |
| 227 | .height = 240, |
| 228 | .hfp = 8, |
| 229 | .hbp = 6, |
| 230 | .hsw = 0, |
| 231 | .vfp = 2, |
| 232 | .vbp = 2, |
| 233 | .vsw = 0, |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 234 | .pxl_clk = 4608000, |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 235 | .invert_pxl_clk = 1, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 236 | }, |
| 237 | /* Sharp LK043T1DG01 */ |
| 238 | [1] = { |
| 239 | .name = "Sharp_LK043T1DG01", |
| 240 | .width = 480, |
| 241 | .height = 272, |
| 242 | .hfp = 2, |
| 243 | .hbp = 2, |
| 244 | .hsw = 41, |
| 245 | .vfp = 2, |
| 246 | .vbp = 2, |
| 247 | .vsw = 10, |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 248 | .pxl_clk = 7833600, |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 249 | .invert_pxl_clk = 0, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 250 | }, |
Anatolij Gustschin | f413070 | 2012-03-13 14:13:57 +0100 | [diff] [blame] | 251 | [2] = { |
| 252 | /* Hitachi SP10Q010 */ |
| 253 | .name = "SP10Q010", |
| 254 | .width = 320, |
| 255 | .height = 240, |
| 256 | .hfp = 10, |
| 257 | .hbp = 10, |
| 258 | .hsw = 10, |
| 259 | .vfp = 10, |
| 260 | .vbp = 10, |
| 261 | .vsw = 10, |
| 262 | .pxl_clk = 7833600, |
| 263 | .invert_pxl_clk = 0, |
| 264 | }, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 265 | }; |
| 266 | |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 267 | /* Enable the Raster Engine of the LCD Controller */ |
| 268 | static inline void lcd_enable_raster(void) |
| 269 | { |
| 270 | u32 reg; |
| 271 | |
Manjunathappa, Prakash | 92b4e45 | 2012-07-20 21:21:11 +0530 | [diff] [blame^] | 272 | /* Put LCDC in reset for several cycles */ |
| 273 | if (lcd_revision == LCD_VERSION_2) |
| 274 | /* Write 1 to reset LCDC */ |
| 275 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); |
| 276 | mdelay(1); |
| 277 | |
Manjunathappa, Prakash | 74a0efd | 2011-11-15 17:32:23 +0530 | [diff] [blame] | 278 | /* Bring LCDC out of reset */ |
| 279 | if (lcd_revision == LCD_VERSION_2) |
| 280 | lcdc_write(0, LCD_CLK_RESET_REG); |
Manjunathappa, Prakash | 92b4e45 | 2012-07-20 21:21:11 +0530 | [diff] [blame^] | 281 | mdelay(1); |
Manjunathappa, Prakash | 74a0efd | 2011-11-15 17:32:23 +0530 | [diff] [blame] | 282 | |
Manjunathappa, Prakash | 92b4e45 | 2012-07-20 21:21:11 +0530 | [diff] [blame^] | 283 | /* Above reset sequence doesnot reset register context */ |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 284 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
| 285 | if (!(reg & LCD_RASTER_ENABLE)) |
| 286 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
| 287 | } |
| 288 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 289 | /* Disable the Raster Engine of the LCD Controller */ |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 290 | static inline void lcd_disable_raster(void) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 291 | { |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 292 | u32 reg; |
| 293 | |
| 294 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 295 | if (reg & LCD_RASTER_ENABLE) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 296 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) |
| 300 | { |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 301 | u32 start; |
| 302 | u32 end; |
| 303 | u32 reg_ras; |
| 304 | u32 reg_dma; |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 305 | u32 reg_int; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 306 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 307 | /* init reg to clear PLM (loading mode) fields */ |
| 308 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); |
| 309 | reg_ras &= ~(3 << 20); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 310 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 311 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 312 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 313 | if (load_mode == LOAD_DATA) { |
| 314 | start = par->dma_start; |
| 315 | end = par->dma_end; |
| 316 | |
| 317 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 318 | if (lcd_revision == LCD_VERSION_1) { |
| 319 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; |
| 320 | } else { |
| 321 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | |
| 322 | LCD_V2_END_OF_FRAME0_INT_ENA | |
| 323 | LCD_V2_END_OF_FRAME1_INT_ENA; |
| 324 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
| 325 | } |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 326 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
| 327 | |
| 328 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); |
| 329 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); |
| 330 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); |
| 331 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); |
| 332 | } else if (load_mode == LOAD_PALETTE) { |
| 333 | start = par->p_palette_base; |
| 334 | end = start + par->palette_sz - 1; |
| 335 | |
| 336 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 337 | |
| 338 | if (lcd_revision == LCD_VERSION_1) { |
| 339 | reg_ras |= LCD_V1_PL_INT_ENA; |
| 340 | } else { |
| 341 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | |
| 342 | LCD_V2_PL_INT_ENA; |
| 343 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
| 344 | } |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 345 | |
| 346 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); |
| 347 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); |
| 348 | } |
| 349 | |
| 350 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
| 351 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
| 352 | |
| 353 | /* |
| 354 | * The Raster enable bit must be set after all other control fields are |
| 355 | * set. |
| 356 | */ |
| 357 | lcd_enable_raster(); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 358 | } |
| 359 | |
Manjunathappa, Prakash | fb8fa94 | 2012-07-18 21:03:36 +0530 | [diff] [blame] | 360 | /* Configure the Burst Size and fifo threhold of DMA */ |
| 361 | static int lcd_cfg_dma(int burst_size, int fifo_th) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 362 | { |
| 363 | u32 reg; |
| 364 | |
| 365 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; |
| 366 | switch (burst_size) { |
| 367 | case 1: |
| 368 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); |
| 369 | break; |
| 370 | case 2: |
| 371 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); |
| 372 | break; |
| 373 | case 4: |
| 374 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); |
| 375 | break; |
| 376 | case 8: |
| 377 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); |
| 378 | break; |
| 379 | case 16: |
| 380 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); |
| 381 | break; |
| 382 | default: |
| 383 | return -EINVAL; |
| 384 | } |
Manjunathappa, Prakash | fb8fa94 | 2012-07-18 21:03:36 +0530 | [diff] [blame] | 385 | |
| 386 | reg |= (fifo_th << 8); |
| 387 | |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 388 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 389 | |
| 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) |
| 394 | { |
| 395 | u32 reg; |
| 396 | |
| 397 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ |
| 398 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; |
| 399 | reg |= LCD_AC_BIAS_FREQUENCY(period) | |
| 400 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); |
| 401 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); |
| 402 | } |
| 403 | |
| 404 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, |
| 405 | int front_porch) |
| 406 | { |
| 407 | u32 reg; |
| 408 | |
| 409 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; |
| 410 | reg |= ((back_porch & 0xff) << 24) |
| 411 | | ((front_porch & 0xff) << 16) |
| 412 | | ((pulse_width & 0x3f) << 10); |
| 413 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
| 414 | } |
| 415 | |
| 416 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, |
| 417 | int front_porch) |
| 418 | { |
| 419 | u32 reg; |
| 420 | |
| 421 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; |
| 422 | reg |= ((back_porch & 0xff) << 24) |
| 423 | | ((front_porch & 0xff) << 16) |
| 424 | | ((pulse_width & 0x3f) << 10); |
| 425 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); |
| 426 | } |
| 427 | |
| 428 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) |
| 429 | { |
| 430 | u32 reg; |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 431 | u32 reg_int; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 432 | |
| 433 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | |
| 434 | LCD_MONO_8BIT_MODE | |
| 435 | LCD_MONOCHROME_MODE); |
| 436 | |
| 437 | switch (cfg->p_disp_panel->panel_shade) { |
| 438 | case MONOCHROME: |
| 439 | reg |= LCD_MONOCHROME_MODE; |
| 440 | if (cfg->mono_8bit_mode) |
| 441 | reg |= LCD_MONO_8BIT_MODE; |
| 442 | break; |
| 443 | case COLOR_ACTIVE: |
| 444 | reg |= LCD_TFT_MODE; |
| 445 | if (cfg->tft_alt_mode) |
| 446 | reg |= LCD_TFT_ALT_ENABLE; |
| 447 | break; |
| 448 | |
| 449 | case COLOR_PASSIVE: |
| 450 | if (cfg->stn_565_mode) |
| 451 | reg |= LCD_STN_565_ENABLE; |
| 452 | break; |
| 453 | |
| 454 | default: |
| 455 | return -EINVAL; |
| 456 | } |
| 457 | |
| 458 | /* enable additional interrupts here */ |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 459 | if (lcd_revision == LCD_VERSION_1) { |
| 460 | reg |= LCD_V1_UNDERFLOW_INT_ENA; |
| 461 | } else { |
| 462 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | |
| 463 | LCD_V2_UNDERFLOW_INT_ENA; |
| 464 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
| 465 | } |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 466 | |
| 467 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
| 468 | |
| 469 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); |
| 470 | |
| 471 | if (cfg->sync_ctrl) |
| 472 | reg |= LCD_SYNC_CTRL; |
| 473 | else |
| 474 | reg &= ~LCD_SYNC_CTRL; |
| 475 | |
| 476 | if (cfg->sync_edge) |
| 477 | reg |= LCD_SYNC_EDGE; |
| 478 | else |
| 479 | reg &= ~LCD_SYNC_EDGE; |
| 480 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 481 | if (cfg->invert_line_clock) |
| 482 | reg |= LCD_INVERT_LINE_CLOCK; |
| 483 | else |
| 484 | reg &= ~LCD_INVERT_LINE_CLOCK; |
| 485 | |
| 486 | if (cfg->invert_frm_clock) |
| 487 | reg |= LCD_INVERT_FRAME_CLOCK; |
| 488 | else |
| 489 | reg &= ~LCD_INVERT_FRAME_CLOCK; |
| 490 | |
| 491 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | |
| 496 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, |
| 497 | u32 bpp, u32 raster_order) |
| 498 | { |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 499 | u32 reg; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 500 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 501 | /* Set the Panel Width */ |
| 502 | /* Pixels per line = (PPL + 1)*16 */ |
Manjunathappa, Prakash | 4d74080 | 2011-07-18 09:58:53 +0530 | [diff] [blame] | 503 | if (lcd_revision == LCD_VERSION_1) { |
| 504 | /* |
| 505 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 |
| 506 | * pixels. |
| 507 | */ |
| 508 | width &= 0x3f0; |
| 509 | } else { |
| 510 | /* |
| 511 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 |
| 512 | * pixels. |
| 513 | */ |
| 514 | width &= 0x7f0; |
| 515 | } |
| 516 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 517 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
| 518 | reg &= 0xfffffc00; |
Manjunathappa, Prakash | 4d74080 | 2011-07-18 09:58:53 +0530 | [diff] [blame] | 519 | if (lcd_revision == LCD_VERSION_1) { |
| 520 | reg |= ((width >> 4) - 1) << 4; |
| 521 | } else { |
| 522 | width = (width >> 4) - 1; |
| 523 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); |
| 524 | } |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 525 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
| 526 | |
| 527 | /* Set the Panel Height */ |
Manjunathappa, Prakash | 4d74080 | 2011-07-18 09:58:53 +0530 | [diff] [blame] | 528 | /* Set bits 9:0 of Lines Per Pixel */ |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 529 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
| 530 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); |
| 531 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); |
| 532 | |
Manjunathappa, Prakash | 4d74080 | 2011-07-18 09:58:53 +0530 | [diff] [blame] | 533 | /* Set bit 10 of Lines Per Pixel */ |
| 534 | if (lcd_revision == LCD_VERSION_2) { |
| 535 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); |
| 536 | reg |= ((height - 1) & 0x400) << 16; |
| 537 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); |
| 538 | } |
| 539 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 540 | /* Set the Raster Order of the Frame Buffer */ |
| 541 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); |
| 542 | if (raster_order) |
| 543 | reg |= LCD_RASTER_ORDER; |
| 544 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
| 545 | |
| 546 | switch (bpp) { |
| 547 | case 1: |
| 548 | case 2: |
| 549 | case 4: |
| 550 | case 16: |
| 551 | par->palette_sz = 16 * 2; |
| 552 | break; |
| 553 | |
| 554 | case 8: |
| 555 | par->palette_sz = 256 * 2; |
| 556 | break; |
| 557 | |
| 558 | default: |
| 559 | return -EINVAL; |
| 560 | } |
| 561 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
| 566 | unsigned blue, unsigned transp, |
| 567 | struct fb_info *info) |
| 568 | { |
| 569 | struct da8xx_fb_par *par = info->par; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 570 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 571 | u_short pal; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 572 | int update_hw = 0; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 573 | |
| 574 | if (regno > 255) |
| 575 | return 1; |
| 576 | |
| 577 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) |
| 578 | return 1; |
| 579 | |
Anatolij Gustschin | f413070 | 2012-03-13 14:13:57 +0100 | [diff] [blame] | 580 | if (info->var.bits_per_pixel == 4) { |
| 581 | if (regno > 15) |
| 582 | return 1; |
| 583 | |
| 584 | if (info->var.grayscale) { |
| 585 | pal = regno; |
| 586 | } else { |
| 587 | red >>= 4; |
| 588 | green >>= 8; |
| 589 | blue >>= 12; |
| 590 | |
| 591 | pal = (red & 0x0f00); |
| 592 | pal |= (green & 0x00f0); |
| 593 | pal |= (blue & 0x000f); |
| 594 | } |
| 595 | if (regno == 0) |
| 596 | pal |= 0x2000; |
| 597 | palette[regno] = pal; |
| 598 | |
| 599 | } else if (info->var.bits_per_pixel == 8) { |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 600 | red >>= 4; |
| 601 | green >>= 8; |
| 602 | blue >>= 12; |
| 603 | |
| 604 | pal = (red & 0x0f00); |
| 605 | pal |= (green & 0x00f0); |
| 606 | pal |= (blue & 0x000f); |
| 607 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 608 | if (palette[regno] != pal) { |
| 609 | update_hw = 1; |
| 610 | palette[regno] = pal; |
| 611 | } |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 612 | } else if ((info->var.bits_per_pixel == 16) && regno < 16) { |
| 613 | red >>= (16 - info->var.red.length); |
| 614 | red <<= info->var.red.offset; |
| 615 | |
| 616 | green >>= (16 - info->var.green.length); |
| 617 | green <<= info->var.green.offset; |
| 618 | |
| 619 | blue >>= (16 - info->var.blue.length); |
| 620 | blue <<= info->var.blue.offset; |
| 621 | |
| 622 | par->pseudo_palette[regno] = red | green | blue; |
| 623 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 624 | if (palette[0] != 0x4000) { |
| 625 | update_hw = 1; |
| 626 | palette[0] = 0x4000; |
| 627 | } |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 628 | } |
| 629 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 630 | /* Update the palette in the h/w as needed. */ |
| 631 | if (update_hw) |
| 632 | lcd_blit(LOAD_PALETTE, par); |
| 633 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 634 | return 0; |
| 635 | } |
| 636 | |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 637 | static void lcd_reset(struct da8xx_fb_par *par) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 638 | { |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 639 | /* Disable the Raster if previously Enabled */ |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 640 | lcd_disable_raster(); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 641 | |
| 642 | /* DMA has to be disabled */ |
| 643 | lcdc_write(0, LCD_DMA_CTRL_REG); |
| 644 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 645 | |
Manjunathappa, Prakash | 74a0efd | 2011-11-15 17:32:23 +0530 | [diff] [blame] | 646 | if (lcd_revision == LCD_VERSION_2) { |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 647 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
Manjunathappa, Prakash | 74a0efd | 2011-11-15 17:32:23 +0530 | [diff] [blame] | 648 | /* Write 1 to reset */ |
| 649 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); |
| 650 | lcdc_write(0, LCD_CLK_RESET_REG); |
| 651 | } |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 652 | } |
| 653 | |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 654 | static void lcd_calc_clk_divider(struct da8xx_fb_par *par) |
| 655 | { |
| 656 | unsigned int lcd_clk, div; |
| 657 | |
| 658 | lcd_clk = clk_get_rate(par->lcdc_clk); |
| 659 | div = lcd_clk / par->pxl_clk; |
| 660 | |
| 661 | /* Configure the LCD clock divisor. */ |
| 662 | lcdc_write(LCD_CLK_DIVISOR(div) | |
| 663 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 664 | |
| 665 | if (lcd_revision == LCD_VERSION_2) |
| 666 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | |
| 667 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); |
| 668 | |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 669 | } |
| 670 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 671 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
| 672 | struct da8xx_panel *panel) |
| 673 | { |
| 674 | u32 bpp; |
| 675 | int ret = 0; |
| 676 | |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 677 | lcd_reset(par); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 678 | |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 679 | /* Calculate the divider */ |
| 680 | lcd_calc_clk_divider(par); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 681 | |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 682 | if (panel->invert_pxl_clk) |
| 683 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | |
| 684 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); |
| 685 | else |
| 686 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & |
| 687 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); |
| 688 | |
Manjunathappa, Prakash | fb8fa94 | 2012-07-18 21:03:36 +0530 | [diff] [blame] | 689 | /* Configure the DMA burst size and fifo threshold. */ |
| 690 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 691 | if (ret < 0) |
| 692 | return ret; |
| 693 | |
| 694 | /* Configure the AC bias properties. */ |
| 695 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); |
| 696 | |
| 697 | /* Configure the vertical and horizontal sync properties. */ |
| 698 | lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); |
| 699 | lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); |
| 700 | |
| 701 | /* Configure for disply */ |
| 702 | ret = lcd_cfg_display(cfg); |
| 703 | if (ret < 0) |
| 704 | return ret; |
| 705 | |
| 706 | if (QVGA != cfg->p_disp_panel->panel_type) |
| 707 | return -EINVAL; |
| 708 | |
| 709 | if (cfg->bpp <= cfg->p_disp_panel->max_bpp && |
| 710 | cfg->bpp >= cfg->p_disp_panel->min_bpp) |
| 711 | bpp = cfg->bpp; |
| 712 | else |
| 713 | bpp = cfg->p_disp_panel->max_bpp; |
| 714 | if (bpp == 12) |
| 715 | bpp = 16; |
| 716 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, |
| 717 | (unsigned int)panel->height, bpp, |
| 718 | cfg->raster_order); |
| 719 | if (ret < 0) |
| 720 | return ret; |
| 721 | |
| 722 | /* Configure FDD */ |
| 723 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | |
| 724 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); |
| 725 | |
| 726 | return 0; |
| 727 | } |
| 728 | |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 729 | /* IRQ handler for version 2 of LCDC */ |
| 730 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) |
| 731 | { |
| 732 | struct da8xx_fb_par *par = arg; |
| 733 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 734 | |
| 735 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { |
| 736 | lcd_disable_raster(); |
| 737 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
| 738 | lcd_enable_raster(); |
| 739 | } else if (stat & LCD_PL_LOAD_DONE) { |
| 740 | /* |
| 741 | * Must disable raster before changing state of any control bit. |
| 742 | * And also must be disabled before clearing the PL loading |
| 743 | * interrupt via the following write to the status register. If |
| 744 | * this is done after then one gets multiple PL done interrupts. |
| 745 | */ |
| 746 | lcd_disable_raster(); |
| 747 | |
| 748 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
| 749 | |
Manjunathappa, Prakash | 8a81dcc | 2012-07-18 20:51:11 +0530 | [diff] [blame] | 750 | /* Disable PL completion interrupt */ |
| 751 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 752 | |
| 753 | /* Setup and start data loading mode */ |
| 754 | lcd_blit(LOAD_DATA, par); |
| 755 | } else { |
| 756 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
| 757 | |
| 758 | if (stat & LCD_END_OF_FRAME0) { |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 759 | par->which_dma_channel_done = 0; |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 760 | lcdc_write(par->dma_start, |
| 761 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); |
| 762 | lcdc_write(par->dma_end, |
| 763 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); |
| 764 | par->vsync_flag = 1; |
| 765 | wake_up_interruptible(&par->vsync_wait); |
| 766 | } |
| 767 | |
| 768 | if (stat & LCD_END_OF_FRAME1) { |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 769 | par->which_dma_channel_done = 1; |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 770 | lcdc_write(par->dma_start, |
| 771 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); |
| 772 | lcdc_write(par->dma_end, |
| 773 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); |
| 774 | par->vsync_flag = 1; |
| 775 | wake_up_interruptible(&par->vsync_wait); |
| 776 | } |
| 777 | } |
| 778 | |
| 779 | lcdc_write(0, LCD_END_OF_INT_IND_REG); |
| 780 | return IRQ_HANDLED; |
| 781 | } |
| 782 | |
| 783 | /* IRQ handler for version 1 LCDC */ |
| 784 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 785 | { |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 786 | struct da8xx_fb_par *par = arg; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 787 | u32 stat = lcdc_read(LCD_STAT_REG); |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 788 | u32 reg_ras; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 789 | |
| 790 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 791 | lcd_disable_raster(); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 792 | lcdc_write(stat, LCD_STAT_REG); |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 793 | lcd_enable_raster(); |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 794 | } else if (stat & LCD_PL_LOAD_DONE) { |
| 795 | /* |
| 796 | * Must disable raster before changing state of any control bit. |
| 797 | * And also must be disabled before clearing the PL loading |
| 798 | * interrupt via the following write to the status register. If |
| 799 | * this is done after then one gets multiple PL done interrupts. |
| 800 | */ |
| 801 | lcd_disable_raster(); |
| 802 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 803 | lcdc_write(stat, LCD_STAT_REG); |
| 804 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 805 | /* Disable PL completion inerrupt */ |
| 806 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 807 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 808 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
| 809 | |
| 810 | /* Setup and start data loading mode */ |
| 811 | lcd_blit(LOAD_DATA, par); |
| 812 | } else { |
| 813 | lcdc_write(stat, LCD_STAT_REG); |
| 814 | |
| 815 | if (stat & LCD_END_OF_FRAME0) { |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 816 | par->which_dma_channel_done = 0; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 817 | lcdc_write(par->dma_start, |
| 818 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); |
| 819 | lcdc_write(par->dma_end, |
| 820 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); |
| 821 | par->vsync_flag = 1; |
| 822 | wake_up_interruptible(&par->vsync_wait); |
| 823 | } |
| 824 | |
| 825 | if (stat & LCD_END_OF_FRAME1) { |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 826 | par->which_dma_channel_done = 1; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 827 | lcdc_write(par->dma_start, |
| 828 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); |
| 829 | lcdc_write(par->dma_end, |
| 830 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); |
| 831 | par->vsync_flag = 1; |
| 832 | wake_up_interruptible(&par->vsync_wait); |
| 833 | } |
| 834 | } |
| 835 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 836 | return IRQ_HANDLED; |
| 837 | } |
| 838 | |
| 839 | static int fb_check_var(struct fb_var_screeninfo *var, |
| 840 | struct fb_info *info) |
| 841 | { |
| 842 | int err = 0; |
| 843 | |
| 844 | switch (var->bits_per_pixel) { |
| 845 | case 1: |
| 846 | case 8: |
| 847 | var->red.offset = 0; |
| 848 | var->red.length = 8; |
| 849 | var->green.offset = 0; |
| 850 | var->green.length = 8; |
| 851 | var->blue.offset = 0; |
| 852 | var->blue.length = 8; |
| 853 | var->transp.offset = 0; |
| 854 | var->transp.length = 0; |
Anatolij Gustschin | f413070 | 2012-03-13 14:13:57 +0100 | [diff] [blame] | 855 | var->nonstd = 0; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 856 | break; |
| 857 | case 4: |
| 858 | var->red.offset = 0; |
| 859 | var->red.length = 4; |
| 860 | var->green.offset = 0; |
| 861 | var->green.length = 4; |
| 862 | var->blue.offset = 0; |
| 863 | var->blue.length = 4; |
| 864 | var->transp.offset = 0; |
| 865 | var->transp.length = 0; |
Anatolij Gustschin | f413070 | 2012-03-13 14:13:57 +0100 | [diff] [blame] | 866 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 867 | break; |
| 868 | case 16: /* RGB 565 */ |
Sudhakar Rajashekhara | 3510b8f | 2009-12-01 13:17:43 -0800 | [diff] [blame] | 869 | var->red.offset = 11; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 870 | var->red.length = 5; |
| 871 | var->green.offset = 5; |
| 872 | var->green.length = 6; |
Sudhakar Rajashekhara | 3510b8f | 2009-12-01 13:17:43 -0800 | [diff] [blame] | 873 | var->blue.offset = 0; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 874 | var->blue.length = 5; |
| 875 | var->transp.offset = 0; |
| 876 | var->transp.length = 0; |
Anatolij Gustschin | f413070 | 2012-03-13 14:13:57 +0100 | [diff] [blame] | 877 | var->nonstd = 0; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 878 | break; |
| 879 | default: |
| 880 | err = -EINVAL; |
| 881 | } |
| 882 | |
| 883 | var->red.msb_right = 0; |
| 884 | var->green.msb_right = 0; |
| 885 | var->blue.msb_right = 0; |
| 886 | var->transp.msb_right = 0; |
| 887 | return err; |
| 888 | } |
| 889 | |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 890 | #ifdef CONFIG_CPU_FREQ |
| 891 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, |
| 892 | unsigned long val, void *data) |
| 893 | { |
| 894 | struct da8xx_fb_par *par; |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 895 | |
| 896 | par = container_of(nb, struct da8xx_fb_par, freq_transition); |
Manjunathappa, Prakash | f820917 | 2012-01-03 18:10:51 +0530 | [diff] [blame] | 897 | if (val == CPUFREQ_POSTCHANGE) { |
| 898 | if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { |
| 899 | par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); |
| 900 | lcd_disable_raster(); |
| 901 | lcd_calc_clk_divider(par); |
| 902 | lcd_enable_raster(); |
| 903 | } |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | return 0; |
| 907 | } |
| 908 | |
| 909 | static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) |
| 910 | { |
| 911 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; |
| 912 | |
| 913 | return cpufreq_register_notifier(&par->freq_transition, |
| 914 | CPUFREQ_TRANSITION_NOTIFIER); |
| 915 | } |
| 916 | |
| 917 | static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) |
| 918 | { |
| 919 | cpufreq_unregister_notifier(&par->freq_transition, |
| 920 | CPUFREQ_TRANSITION_NOTIFIER); |
| 921 | } |
| 922 | #endif |
| 923 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 924 | static int __devexit fb_remove(struct platform_device *dev) |
| 925 | { |
| 926 | struct fb_info *info = dev_get_drvdata(&dev->dev); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 927 | |
| 928 | if (info) { |
| 929 | struct da8xx_fb_par *par = info->par; |
| 930 | |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 931 | #ifdef CONFIG_CPU_FREQ |
| 932 | lcd_da8xx_cpufreq_deregister(par); |
| 933 | #endif |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 934 | if (par->panel_power_ctrl) |
| 935 | par->panel_power_ctrl(0); |
| 936 | |
| 937 | lcd_disable_raster(); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 938 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
| 939 | |
| 940 | /* disable DMA */ |
| 941 | lcdc_write(0, LCD_DMA_CTRL_REG); |
| 942 | |
| 943 | unregister_framebuffer(info); |
| 944 | fb_dealloc_cmap(&info->cmap); |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 945 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
| 946 | par->p_palette_base); |
| 947 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, |
| 948 | par->vram_phys); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 949 | free_irq(par->irq, par); |
| 950 | clk_disable(par->lcdc_clk); |
| 951 | clk_put(par->lcdc_clk); |
| 952 | framebuffer_release(info); |
| 953 | iounmap((void __iomem *)da8xx_fb_reg_base); |
| 954 | release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); |
| 955 | |
| 956 | } |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 957 | return 0; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 958 | } |
| 959 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 960 | /* |
| 961 | * Function to wait for vertical sync which for this LCD peripheral |
| 962 | * translates into waiting for the current raster frame to complete. |
| 963 | */ |
| 964 | static int fb_wait_for_vsync(struct fb_info *info) |
| 965 | { |
| 966 | struct da8xx_fb_par *par = info->par; |
| 967 | int ret; |
| 968 | |
| 969 | /* |
| 970 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 971 | * race condition here where the ISR could have occurred just before or |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 972 | * just after this set. But since we are just coarsely waiting for |
| 973 | * a frame to complete then that's OK. i.e. if the frame completed |
| 974 | * just before this code executed then we have to wait another full |
| 975 | * frame time but there is no way to avoid such a situation. On the |
| 976 | * other hand if the frame completed just after then we don't need |
| 977 | * to wait long at all. Either way we are guaranteed to return to the |
| 978 | * user immediately after a frame completion which is all that is |
| 979 | * required. |
| 980 | */ |
| 981 | par->vsync_flag = 0; |
| 982 | ret = wait_event_interruptible_timeout(par->vsync_wait, |
| 983 | par->vsync_flag != 0, |
| 984 | par->vsync_timeout); |
| 985 | if (ret < 0) |
| 986 | return ret; |
| 987 | if (ret == 0) |
| 988 | return -ETIMEDOUT; |
| 989 | |
| 990 | return 0; |
| 991 | } |
| 992 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 993 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
| 994 | unsigned long arg) |
| 995 | { |
| 996 | struct lcd_sync_arg sync_arg; |
| 997 | |
| 998 | switch (cmd) { |
| 999 | case FBIOGET_CONTRAST: |
| 1000 | case FBIOPUT_CONTRAST: |
| 1001 | case FBIGET_BRIGHTNESS: |
| 1002 | case FBIPUT_BRIGHTNESS: |
| 1003 | case FBIGET_COLOR: |
| 1004 | case FBIPUT_COLOR: |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1005 | return -ENOTTY; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1006 | case FBIPUT_HSYNC: |
| 1007 | if (copy_from_user(&sync_arg, (char *)arg, |
| 1008 | sizeof(struct lcd_sync_arg))) |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1009 | return -EFAULT; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1010 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
| 1011 | sync_arg.pulse_width, |
| 1012 | sync_arg.front_porch); |
| 1013 | break; |
| 1014 | case FBIPUT_VSYNC: |
| 1015 | if (copy_from_user(&sync_arg, (char *)arg, |
| 1016 | sizeof(struct lcd_sync_arg))) |
Sudhakar Rajashekhara | 2f93e8f | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1017 | return -EFAULT; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1018 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
| 1019 | sync_arg.pulse_width, |
| 1020 | sync_arg.front_porch); |
| 1021 | break; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1022 | case FBIO_WAITFORVSYNC: |
| 1023 | return fb_wait_for_vsync(info); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1024 | default: |
| 1025 | return -EINVAL; |
| 1026 | } |
| 1027 | return 0; |
| 1028 | } |
| 1029 | |
Chaithrika U S | 312d971 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1030 | static int cfb_blank(int blank, struct fb_info *info) |
| 1031 | { |
| 1032 | struct da8xx_fb_par *par = info->par; |
| 1033 | int ret = 0; |
| 1034 | |
| 1035 | if (par->blank == blank) |
| 1036 | return 0; |
| 1037 | |
| 1038 | par->blank = blank; |
| 1039 | switch (blank) { |
| 1040 | case FB_BLANK_UNBLANK: |
| 1041 | if (par->panel_power_ctrl) |
| 1042 | par->panel_power_ctrl(1); |
| 1043 | |
| 1044 | lcd_enable_raster(); |
| 1045 | break; |
Yegor Yefremov | 99a647d | 2012-07-06 16:01:28 +0200 | [diff] [blame] | 1046 | case FB_BLANK_NORMAL: |
| 1047 | case FB_BLANK_VSYNC_SUSPEND: |
| 1048 | case FB_BLANK_HSYNC_SUSPEND: |
Chaithrika U S | 312d971 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1049 | case FB_BLANK_POWERDOWN: |
| 1050 | if (par->panel_power_ctrl) |
| 1051 | par->panel_power_ctrl(0); |
| 1052 | |
| 1053 | lcd_disable_raster(); |
| 1054 | break; |
| 1055 | default: |
| 1056 | ret = -EINVAL; |
| 1057 | } |
| 1058 | |
| 1059 | return ret; |
| 1060 | } |
| 1061 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1062 | /* |
| 1063 | * Set new x,y offsets in the virtual display for the visible area and switch |
| 1064 | * to the new mode. |
| 1065 | */ |
| 1066 | static int da8xx_pan_display(struct fb_var_screeninfo *var, |
| 1067 | struct fb_info *fbi) |
| 1068 | { |
| 1069 | int ret = 0; |
| 1070 | struct fb_var_screeninfo new_var; |
| 1071 | struct da8xx_fb_par *par = fbi->par; |
| 1072 | struct fb_fix_screeninfo *fix = &fbi->fix; |
| 1073 | unsigned int end; |
| 1074 | unsigned int start; |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 1075 | unsigned long irq_flags; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1076 | |
| 1077 | if (var->xoffset != fbi->var.xoffset || |
| 1078 | var->yoffset != fbi->var.yoffset) { |
| 1079 | memcpy(&new_var, &fbi->var, sizeof(new_var)); |
| 1080 | new_var.xoffset = var->xoffset; |
| 1081 | new_var.yoffset = var->yoffset; |
| 1082 | if (fb_check_var(&new_var, fbi)) |
| 1083 | ret = -EINVAL; |
| 1084 | else { |
| 1085 | memcpy(&fbi->var, &new_var, sizeof(new_var)); |
| 1086 | |
| 1087 | start = fix->smem_start + |
| 1088 | new_var.yoffset * fix->line_length + |
Laurent Pinchart | e6c4d3d | 2011-06-14 09:24:45 +0000 | [diff] [blame] | 1089 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
| 1090 | end = start + fbi->var.yres * fix->line_length - 1; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1091 | par->dma_start = start; |
| 1092 | par->dma_end = end; |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 1093 | spin_lock_irqsave(&par->lock_for_chan_update, |
| 1094 | irq_flags); |
| 1095 | if (par->which_dma_channel_done == 0) { |
| 1096 | lcdc_write(par->dma_start, |
| 1097 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); |
| 1098 | lcdc_write(par->dma_end, |
| 1099 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); |
| 1100 | } else if (par->which_dma_channel_done == 1) { |
| 1101 | lcdc_write(par->dma_start, |
| 1102 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); |
| 1103 | lcdc_write(par->dma_end, |
| 1104 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); |
| 1105 | } |
| 1106 | spin_unlock_irqrestore(&par->lock_for_chan_update, |
| 1107 | irq_flags); |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1108 | } |
| 1109 | } |
| 1110 | |
| 1111 | return ret; |
| 1112 | } |
| 1113 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1114 | static struct fb_ops da8xx_fb_ops = { |
| 1115 | .owner = THIS_MODULE, |
| 1116 | .fb_check_var = fb_check_var, |
| 1117 | .fb_setcolreg = fb_setcolreg, |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1118 | .fb_pan_display = da8xx_pan_display, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1119 | .fb_ioctl = fb_ioctl, |
| 1120 | .fb_fillrect = cfb_fillrect, |
| 1121 | .fb_copyarea = cfb_copyarea, |
| 1122 | .fb_imageblit = cfb_imageblit, |
Chaithrika U S | 312d971 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1123 | .fb_blank = cfb_blank, |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1124 | }; |
| 1125 | |
Manjunathappa, Prakash | 12fa835 | 2012-02-09 11:54:06 +0530 | [diff] [blame] | 1126 | /* Calculate and return pixel clock period in pico seconds */ |
| 1127 | static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par) |
| 1128 | { |
| 1129 | unsigned int lcd_clk, div; |
| 1130 | unsigned int configured_pix_clk; |
| 1131 | unsigned long long pix_clk_period_picosec = 1000000000000ULL; |
| 1132 | |
| 1133 | lcd_clk = clk_get_rate(par->lcdc_clk); |
| 1134 | div = lcd_clk / par->pxl_clk; |
| 1135 | configured_pix_clk = (lcd_clk / div); |
| 1136 | |
| 1137 | do_div(pix_clk_period_picosec, configured_pix_clk); |
| 1138 | |
| 1139 | return pix_clk_period_picosec; |
| 1140 | } |
| 1141 | |
axel lin | 1db41e0 | 2011-02-22 01:52:42 +0000 | [diff] [blame] | 1142 | static int __devinit fb_probe(struct platform_device *device) |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1143 | { |
| 1144 | struct da8xx_lcdc_platform_data *fb_pdata = |
| 1145 | device->dev.platform_data; |
| 1146 | struct lcd_ctrl_config *lcd_cfg; |
| 1147 | struct da8xx_panel *lcdc_info; |
| 1148 | struct fb_info *da8xx_fb_info; |
| 1149 | struct clk *fb_clk = NULL; |
| 1150 | struct da8xx_fb_par *par; |
| 1151 | resource_size_t len; |
| 1152 | int ret, i; |
Aditya Nellutla | 3b9cc4e | 2012-05-23 11:36:31 +0530 | [diff] [blame] | 1153 | unsigned long ulcm; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1154 | |
| 1155 | if (fb_pdata == NULL) { |
| 1156 | dev_err(&device->dev, "Can not get platform data\n"); |
| 1157 | return -ENOENT; |
| 1158 | } |
| 1159 | |
| 1160 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); |
| 1161 | if (!lcdc_regs) { |
| 1162 | dev_err(&device->dev, |
| 1163 | "Can not get memory resource for LCD controller\n"); |
| 1164 | return -ENOENT; |
| 1165 | } |
| 1166 | |
| 1167 | len = resource_size(lcdc_regs); |
| 1168 | |
| 1169 | lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name); |
| 1170 | if (!lcdc_regs) |
| 1171 | return -EBUSY; |
| 1172 | |
| 1173 | da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len); |
| 1174 | if (!da8xx_fb_reg_base) { |
| 1175 | ret = -EBUSY; |
| 1176 | goto err_request_mem; |
| 1177 | } |
| 1178 | |
| 1179 | fb_clk = clk_get(&device->dev, NULL); |
| 1180 | if (IS_ERR(fb_clk)) { |
| 1181 | dev_err(&device->dev, "Can not get device clock\n"); |
| 1182 | ret = -ENODEV; |
| 1183 | goto err_ioremap; |
| 1184 | } |
| 1185 | ret = clk_enable(fb_clk); |
| 1186 | if (ret) |
| 1187 | goto err_clk_put; |
| 1188 | |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 1189 | /* Determine LCD IP Version */ |
| 1190 | switch (lcdc_read(LCD_PID_REG)) { |
| 1191 | case 0x4C100102: |
| 1192 | lcd_revision = LCD_VERSION_1; |
| 1193 | break; |
| 1194 | case 0x4F200800: |
| 1195 | lcd_revision = LCD_VERSION_2; |
| 1196 | break; |
| 1197 | default: |
| 1198 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " |
| 1199 | "defaulting to LCD revision 1\n", |
| 1200 | lcdc_read(LCD_PID_REG)); |
| 1201 | lcd_revision = LCD_VERSION_1; |
| 1202 | break; |
| 1203 | } |
| 1204 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1205 | for (i = 0, lcdc_info = known_lcd_panels; |
| 1206 | i < ARRAY_SIZE(known_lcd_panels); |
| 1207 | i++, lcdc_info++) { |
| 1208 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) |
| 1209 | break; |
| 1210 | } |
| 1211 | |
| 1212 | if (i == ARRAY_SIZE(known_lcd_panels)) { |
| 1213 | dev_err(&device->dev, "GLCD: No valid panel found\n"); |
Roel Kluin | dd04a6b | 2009-11-17 14:06:15 -0800 | [diff] [blame] | 1214 | ret = -ENODEV; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1215 | goto err_clk_disable; |
| 1216 | } else |
| 1217 | dev_info(&device->dev, "GLCD: Found %s panel\n", |
| 1218 | fb_pdata->type); |
| 1219 | |
| 1220 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; |
| 1221 | |
| 1222 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), |
| 1223 | &device->dev); |
| 1224 | if (!da8xx_fb_info) { |
| 1225 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); |
| 1226 | ret = -ENOMEM; |
| 1227 | goto err_clk_disable; |
| 1228 | } |
| 1229 | |
| 1230 | par = da8xx_fb_info->par; |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 1231 | par->lcdc_clk = fb_clk; |
Manjunathappa, Prakash | f820917 | 2012-01-03 18:10:51 +0530 | [diff] [blame] | 1232 | #ifdef CONFIG_CPU_FREQ |
| 1233 | par->lcd_fck_rate = clk_get_rate(fb_clk); |
| 1234 | #endif |
Chaithrika U S | 8097b17 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 1235 | par->pxl_clk = lcdc_info->pxl_clk; |
Chaithrika U S | 3611380 | 2009-12-15 16:46:38 -0800 | [diff] [blame] | 1236 | if (fb_pdata->panel_power_ctrl) { |
| 1237 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; |
| 1238 | par->panel_power_ctrl(1); |
| 1239 | } |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1240 | |
| 1241 | if (lcd_init(par, lcd_cfg, lcdc_info) < 0) { |
| 1242 | dev_err(&device->dev, "lcd_init failed\n"); |
| 1243 | ret = -EFAULT; |
| 1244 | goto err_release_fb; |
| 1245 | } |
| 1246 | |
| 1247 | /* allocate frame buffer */ |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1248 | par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp; |
Aditya Nellutla | 3b9cc4e | 2012-05-23 11:36:31 +0530 | [diff] [blame] | 1249 | ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE); |
| 1250 | par->vram_size = roundup(par->vram_size/8, ulcm); |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1251 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1252 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1253 | par->vram_virt = dma_alloc_coherent(NULL, |
| 1254 | par->vram_size, |
| 1255 | (resource_size_t *) &par->vram_phys, |
| 1256 | GFP_KERNEL | GFP_DMA); |
| 1257 | if (!par->vram_virt) { |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1258 | dev_err(&device->dev, |
| 1259 | "GLCD: kmalloc for frame buffer failed\n"); |
| 1260 | ret = -EINVAL; |
| 1261 | goto err_release_fb; |
| 1262 | } |
| 1263 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1264 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
| 1265 | da8xx_fb_fix.smem_start = par->vram_phys; |
| 1266 | da8xx_fb_fix.smem_len = par->vram_size; |
| 1267 | da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1268 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1269 | par->dma_start = par->vram_phys; |
| 1270 | par->dma_end = par->dma_start + lcdc_info->height * |
| 1271 | da8xx_fb_fix.line_length - 1; |
| 1272 | |
| 1273 | /* allocate palette buffer */ |
| 1274 | par->v_palette_base = dma_alloc_coherent(NULL, |
| 1275 | PALETTE_SIZE, |
| 1276 | (resource_size_t *) |
| 1277 | &par->p_palette_base, |
| 1278 | GFP_KERNEL | GFP_DMA); |
| 1279 | if (!par->v_palette_base) { |
| 1280 | dev_err(&device->dev, |
| 1281 | "GLCD: kmalloc for palette buffer failed\n"); |
| 1282 | ret = -EINVAL; |
| 1283 | goto err_release_fb_mem; |
| 1284 | } |
| 1285 | memset(par->v_palette_base, 0, PALETTE_SIZE); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1286 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1287 | par->irq = platform_get_irq(device, 0); |
| 1288 | if (par->irq < 0) { |
| 1289 | ret = -ENOENT; |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1290 | goto err_release_pl_mem; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1291 | } |
| 1292 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1293 | /* Initialize par */ |
| 1294 | da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp; |
| 1295 | |
| 1296 | da8xx_fb_var.xres = lcdc_info->width; |
| 1297 | da8xx_fb_var.xres_virtual = lcdc_info->width; |
| 1298 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1299 | da8xx_fb_var.yres = lcdc_info->height; |
| 1300 | da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1301 | |
| 1302 | da8xx_fb_var.grayscale = |
| 1303 | lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; |
| 1304 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; |
| 1305 | |
| 1306 | da8xx_fb_var.hsync_len = lcdc_info->hsw; |
| 1307 | da8xx_fb_var.vsync_len = lcdc_info->vsw; |
Anatolij Gustschin | 084e104 | 2012-03-13 14:13:04 +0100 | [diff] [blame] | 1308 | da8xx_fb_var.right_margin = lcdc_info->hfp; |
| 1309 | da8xx_fb_var.left_margin = lcdc_info->hbp; |
| 1310 | da8xx_fb_var.lower_margin = lcdc_info->vfp; |
| 1311 | da8xx_fb_var.upper_margin = lcdc_info->vbp; |
Manjunathappa, Prakash | 12fa835 | 2012-02-09 11:54:06 +0530 | [diff] [blame] | 1312 | da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1313 | |
| 1314 | /* Initialize fbinfo */ |
| 1315 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; |
| 1316 | da8xx_fb_info->fix = da8xx_fb_fix; |
| 1317 | da8xx_fb_info->var = da8xx_fb_var; |
| 1318 | da8xx_fb_info->fbops = &da8xx_fb_ops; |
| 1319 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; |
Sudhakar Rajashekhara | 3510b8f | 2009-12-01 13:17:43 -0800 | [diff] [blame] | 1320 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
| 1321 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1322 | |
| 1323 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); |
| 1324 | if (ret) |
Caglar Akyuz | 93c176f | 2010-11-30 20:04:14 +0000 | [diff] [blame] | 1325 | goto err_release_pl_mem; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1326 | da8xx_fb_info->cmap.len = par->palette_sz; |
| 1327 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1328 | /* initialize var_screeninfo */ |
| 1329 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; |
| 1330 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); |
| 1331 | |
| 1332 | dev_set_drvdata(&device->dev, da8xx_fb_info); |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1333 | |
| 1334 | /* initialize the vsync wait queue */ |
| 1335 | init_waitqueue_head(&par->vsync_wait); |
| 1336 | par->vsync_timeout = HZ / 5; |
Manjunathappa, Prakash | deb95c6 | 2012-07-18 21:01:56 +0530 | [diff] [blame] | 1337 | par->which_dma_channel_done = -1; |
| 1338 | spin_lock_init(&par->lock_for_chan_update); |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1339 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1340 | /* Register the Frame Buffer */ |
| 1341 | if (register_framebuffer(da8xx_fb_info) < 0) { |
| 1342 | dev_err(&device->dev, |
| 1343 | "GLCD: Frame Buffer Registration Failed!\n"); |
| 1344 | ret = -EINVAL; |
| 1345 | goto err_dealloc_cmap; |
| 1346 | } |
| 1347 | |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 1348 | #ifdef CONFIG_CPU_FREQ |
| 1349 | ret = lcd_da8xx_cpufreq_register(par); |
| 1350 | if (ret) { |
| 1351 | dev_err(&device->dev, "failed to register cpufreq\n"); |
| 1352 | goto err_cpu_freq; |
| 1353 | } |
| 1354 | #endif |
Caglar Akyuz | 93c176f | 2010-11-30 20:04:14 +0000 | [diff] [blame] | 1355 | |
Manjunathappa, Prakash | c6daf05 | 2011-07-05 15:51:20 +0530 | [diff] [blame] | 1356 | if (lcd_revision == LCD_VERSION_1) |
| 1357 | lcdc_irq_handler = lcdc_irq_handler_rev01; |
| 1358 | else |
| 1359 | lcdc_irq_handler = lcdc_irq_handler_rev02; |
| 1360 | |
| 1361 | ret = request_irq(par->irq, lcdc_irq_handler, 0, |
| 1362 | DRIVER_NAME, par); |
Caglar Akyuz | 93c176f | 2010-11-30 20:04:14 +0000 | [diff] [blame] | 1363 | if (ret) |
| 1364 | goto irq_freq; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1365 | return 0; |
| 1366 | |
Caglar Akyuz | 93c176f | 2010-11-30 20:04:14 +0000 | [diff] [blame] | 1367 | irq_freq: |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 1368 | #ifdef CONFIG_CPU_FREQ |
axel lin | 360c202 | 2011-01-20 03:50:51 +0000 | [diff] [blame] | 1369 | lcd_da8xx_cpufreq_deregister(par); |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 1370 | err_cpu_freq: |
Manjunathappa, Prakash | 3a84409 | 2012-02-09 10:34:38 +0530 | [diff] [blame] | 1371 | #endif |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 1372 | unregister_framebuffer(da8xx_fb_info); |
Chaithrika U S | e04e548 | 2009-12-15 16:46:29 -0800 | [diff] [blame] | 1373 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1374 | err_dealloc_cmap: |
| 1375 | fb_dealloc_cmap(&da8xx_fb_info->cmap); |
| 1376 | |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1377 | err_release_pl_mem: |
| 1378 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
| 1379 | par->p_palette_base); |
| 1380 | |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1381 | err_release_fb_mem: |
Martin Ambrose | 1f9c3e1 | 2010-05-24 14:34:01 -0700 | [diff] [blame] | 1382 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1383 | |
| 1384 | err_release_fb: |
| 1385 | framebuffer_release(da8xx_fb_info); |
| 1386 | |
| 1387 | err_clk_disable: |
| 1388 | clk_disable(fb_clk); |
| 1389 | |
| 1390 | err_clk_put: |
| 1391 | clk_put(fb_clk); |
| 1392 | |
| 1393 | err_ioremap: |
| 1394 | iounmap((void __iomem *)da8xx_fb_reg_base); |
| 1395 | |
| 1396 | err_request_mem: |
| 1397 | release_mem_region(lcdc_regs->start, len); |
| 1398 | |
| 1399 | return ret; |
| 1400 | } |
| 1401 | |
| 1402 | #ifdef CONFIG_PM |
| 1403 | static int fb_suspend(struct platform_device *dev, pm_message_t state) |
| 1404 | { |
Chaithrika U S | 1d3c6c7 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1405 | struct fb_info *info = platform_get_drvdata(dev); |
| 1406 | struct da8xx_fb_par *par = info->par; |
| 1407 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1408 | console_lock(); |
Chaithrika U S | 1d3c6c7 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1409 | if (par->panel_power_ctrl) |
| 1410 | par->panel_power_ctrl(0); |
| 1411 | |
| 1412 | fb_set_suspend(info, 1); |
| 1413 | lcd_disable_raster(); |
| 1414 | clk_disable(par->lcdc_clk); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1415 | console_unlock(); |
Chaithrika U S | 1d3c6c7 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1416 | |
| 1417 | return 0; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1418 | } |
| 1419 | static int fb_resume(struct platform_device *dev) |
| 1420 | { |
Chaithrika U S | 1d3c6c7 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1421 | struct fb_info *info = platform_get_drvdata(dev); |
| 1422 | struct da8xx_fb_par *par = info->par; |
| 1423 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1424 | console_lock(); |
Chaithrika U S | 1d3c6c7 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1425 | if (par->panel_power_ctrl) |
| 1426 | par->panel_power_ctrl(1); |
| 1427 | |
| 1428 | clk_enable(par->lcdc_clk); |
| 1429 | lcd_enable_raster(); |
| 1430 | fb_set_suspend(info, 0); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1431 | console_unlock(); |
Chaithrika U S | 1d3c6c7 | 2009-12-15 16:46:39 -0800 | [diff] [blame] | 1432 | |
| 1433 | return 0; |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1434 | } |
| 1435 | #else |
| 1436 | #define fb_suspend NULL |
| 1437 | #define fb_resume NULL |
| 1438 | #endif |
| 1439 | |
| 1440 | static struct platform_driver da8xx_fb_driver = { |
| 1441 | .probe = fb_probe, |
axel lin | 1db41e0 | 2011-02-22 01:52:42 +0000 | [diff] [blame] | 1442 | .remove = __devexit_p(fb_remove), |
Sudhakar Rajashekhara | 4ed824d | 2009-09-22 16:47:06 -0700 | [diff] [blame] | 1443 | .suspend = fb_suspend, |
| 1444 | .resume = fb_resume, |
| 1445 | .driver = { |
| 1446 | .name = DRIVER_NAME, |
| 1447 | .owner = THIS_MODULE, |
| 1448 | }, |
| 1449 | }; |
| 1450 | |
| 1451 | static int __init da8xx_fb_init(void) |
| 1452 | { |
| 1453 | return platform_driver_register(&da8xx_fb_driver); |
| 1454 | } |
| 1455 | |
| 1456 | static void __exit da8xx_fb_cleanup(void) |
| 1457 | { |
| 1458 | platform_driver_unregister(&da8xx_fb_driver); |
| 1459 | } |
| 1460 | |
| 1461 | module_init(da8xx_fb_init); |
| 1462 | module_exit(da8xx_fb_cleanup); |
| 1463 | |
| 1464 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); |
| 1465 | MODULE_AUTHOR("Texas Instruments"); |
| 1466 | MODULE_LICENSE("GPL"); |