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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/video/virgefb.h -- CyberVision64 definitions for the
3 * text console driver.
4 *
5 * Copyright (c) 1998 Alan Bair
6 *
7 * This file is based on the initial port to Linux of grf_cvreg.h:
8 *
9 * Copyright (c) 1997 Antonio Santos
10 *
11 * The original work is from the NetBSD CyberVision 64 framebuffer driver
12 * and support files (grf_cv.c, grf_cvreg.h, ite_cv.c):
13 * Permission to use the source of this driver was obtained from the
14 * author Michael Teske by Alan Bair.
15 *
16 * Copyright (c) 1995 Michael Teske
17 *
18 * History:
19 *
20 *
21 *
22 * This file is subject to the terms and conditions of the GNU General Public
23 * License. See the file COPYING in the main directory of this archive
24 * for more details.
25 */
26
27/* Enhanced register mapping (MMIO mode) */
28
29#define S3_CRTC_ADR 0x03d4
30#define S3_CRTC_DATA 0x03d5
31
32#define S3_REG_LOCK2 0x39
33#define S3_HGC_MODE 0x45
34
35#define S3_HWGC_ORGX_H 0x46
36#define S3_HWGC_ORGX_L 0x47
37#define S3_HWGC_ORGY_H 0x48
38#define S3_HWGC_ORGY_L 0x49
39#define S3_HWGC_DX 0x4e
40#define S3_HWGC_DY 0x4f
41
42#define S3_LAW_CTL 0x58
43
44/**************************************************/
45
46/*
47 * Defines for the used register addresses (mw)
48 *
49 * NOTE: There are some registers that have different addresses when
50 * in mono or color mode. We only support color mode, and thus
51 * some addresses won't work in mono-mode!
52 *
53 * General and VGA-registers taken from retina driver. Fixed a few
54 * bugs in it. (SR and GR read address is Port + 1, NOT Port)
55 *
56 */
57
58/* General Registers: */
59#define GREG_MISC_OUTPUT_R 0x03CC
60#define GREG_MISC_OUTPUT_W 0x03C2
61#define GREG_FEATURE_CONTROL_R 0x03CA
62#define GREG_FEATURE_CONTROL_W 0x03DA
63#define GREG_INPUT_STATUS0_R 0x03C2
64#define GREG_INPUT_STATUS1_R 0x03DA
65
66/* Setup Registers: */
67#define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* virge */
68
69/* Attribute Controller: */
70#define ACT_ADDRESS 0x03C0
71#define ACT_ADDRESS_R 0x03C1
72#define ACT_ADDRESS_W 0x03C0
73#define ACT_ADDRESS_RESET 0x03DA
74#define ACT_ID_PALETTE0 0x00
75#define ACT_ID_PALETTE1 0x01
76#define ACT_ID_PALETTE2 0x02
77#define ACT_ID_PALETTE3 0x03
78#define ACT_ID_PALETTE4 0x04
79#define ACT_ID_PALETTE5 0x05
80#define ACT_ID_PALETTE6 0x06
81#define ACT_ID_PALETTE7 0x07
82#define ACT_ID_PALETTE8 0x08
83#define ACT_ID_PALETTE9 0x09
84#define ACT_ID_PALETTE10 0x0A
85#define ACT_ID_PALETTE11 0x0B
86#define ACT_ID_PALETTE12 0x0C
87#define ACT_ID_PALETTE13 0x0D
88#define ACT_ID_PALETTE14 0x0E
89#define ACT_ID_PALETTE15 0x0F
90#define ACT_ID_ATTR_MODE_CNTL 0x10
91#define ACT_ID_OVERSCAN_COLOR 0x11
92#define ACT_ID_COLOR_PLANE_ENA 0x12
93#define ACT_ID_HOR_PEL_PANNING 0x13
94#define ACT_ID_COLOR_SELECT 0x14 /* virge PX_PADD pixel padding register */
95
96/* Graphics Controller: */
97#define GCT_ADDRESS 0x03CE
98#define GCT_ADDRESS_R 0x03CF
99#define GCT_ADDRESS_W 0x03CF
100#define GCT_ID_SET_RESET 0x00
101#define GCT_ID_ENABLE_SET_RESET 0x01
102#define GCT_ID_COLOR_COMPARE 0x02
103#define GCT_ID_DATA_ROTATE 0x03
104#define GCT_ID_READ_MAP_SELECT 0x04
105#define GCT_ID_GRAPHICS_MODE 0x05
106#define GCT_ID_MISC 0x06
107#define GCT_ID_COLOR_XCARE 0x07
108#define GCT_ID_BITMASK 0x08
109
110/* Sequencer: */
111#define SEQ_ADDRESS 0x03C4
112#define SEQ_ADDRESS_R 0x03C5
113#define SEQ_ADDRESS_W 0x03C5
114#define SEQ_ID_RESET 0x00
115#define SEQ_ID_CLOCKING_MODE 0x01
116#define SEQ_ID_MAP_MASK 0x02
117#define SEQ_ID_CHAR_MAP_SELECT 0x03
118#define SEQ_ID_MEMORY_MODE 0x04
119#define SEQ_ID_UNKNOWN1 0x05
120#define SEQ_ID_UNKNOWN2 0x06
121#define SEQ_ID_UNKNOWN3 0x07
122/* S3 extensions */
123#define SEQ_ID_UNLOCK_EXT 0x08
124#define SEQ_ID_EXT_SEQ_REG9 0x09 /* b7 = 1 extended reg access by MMIO only */
125#define SEQ_ID_BUS_REQ_CNTL 0x0A
126#define SEQ_ID_EXT_MISC_SEQ 0x0B
127#define SEQ_ID_UNKNOWN4 0x0C
128#define SEQ_ID_EXT_SEQ 0x0D
129#define SEQ_ID_UNKNOWN5 0x0E
130#define SEQ_ID_UNKNOWN6 0x0F
131#define SEQ_ID_MCLK_LO 0x10
132#define SEQ_ID_MCLK_HI 0x11
133#define SEQ_ID_DCLK_LO 0x12
134#define SEQ_ID_DCLK_HI 0x13
135#define SEQ_ID_CLKSYN_CNTL_1 0x14
136#define SEQ_ID_CLKSYN_CNTL_2 0x15
137#define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */
138#define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */
139#define SEQ_ID_RAMDAC_CNTL 0x18
140#define SEQ_ID_MORE_MAGIC 0x1A
141#define SEQ_ID_SIGNAL_SELECT 0x1C /* new for virge */
142
143/* CRT Controller: */
144#define CRT_ADDRESS 0x03D4
145#define CRT_ADDRESS_R 0x03D5
146#define CRT_ADDRESS_W 0x03D5
147#define CRT_ID_HOR_TOTAL 0x00
148#define CRT_ID_HOR_DISP_ENA_END 0x01
149#define CRT_ID_START_HOR_BLANK 0x02
150#define CRT_ID_END_HOR_BLANK 0x03
151#define CRT_ID_START_HOR_RETR 0x04
152#define CRT_ID_END_HOR_RETR 0x05
153#define CRT_ID_VER_TOTAL 0x06
154#define CRT_ID_OVERFLOW 0x07
155#define CRT_ID_PRESET_ROW_SCAN 0x08
156#define CRT_ID_MAX_SCAN_LINE 0x09
157#define CRT_ID_CURSOR_START 0x0A
158#define CRT_ID_CURSOR_END 0x0B
159#define CRT_ID_START_ADDR_HIGH 0x0C
160#define CRT_ID_START_ADDR_LOW 0x0D
161#define CRT_ID_CURSOR_LOC_HIGH 0x0E
162#define CRT_ID_CURSOR_LOC_LOW 0x0F
163#define CRT_ID_START_VER_RETR 0x10
164#define CRT_ID_END_VER_RETR 0x11
165#define CRT_ID_VER_DISP_ENA_END 0x12
166#define CRT_ID_SCREEN_OFFSET 0x13
167#define CRT_ID_UNDERLINE_LOC 0x14
168#define CRT_ID_START_VER_BLANK 0x15
169#define CRT_ID_END_VER_BLANK 0x16
170#define CRT_ID_MODE_CONTROL 0x17
171#define CRT_ID_LINE_COMPARE 0x18
172#define CRT_ID_GD_LATCH_RBACK 0x22
173#define CRT_ID_ACT_TOGGLE_RBACK 0x24
174#define CRT_ID_ACT_INDEX_RBACK 0x26
175/* S3 extensions: S3 VGA Registers */
176#define CRT_ID_DEVICE_HIGH 0x2D
177#define CRT_ID_DEVICE_LOW 0x2E
178#define CRT_ID_REVISION 0x2F
179#define CRT_ID_CHIP_ID_REV 0x30
180#define CRT_ID_MEMORY_CONF 0x31
181#define CRT_ID_BACKWAD_COMP_1 0x32
182#define CRT_ID_BACKWAD_COMP_2 0x33
183#define CRT_ID_BACKWAD_COMP_3 0x34
184#define CRT_ID_REGISTER_LOCK 0x35
185#define CRT_ID_CONFIG_1 0x36
186#define CRT_ID_CONFIG_2 0x37
187#define CRT_ID_REGISTER_LOCK_1 0x38
188#define CRT_ID_REGISTER_LOCK_2 0x39
189#define CRT_ID_MISC_1 0x3A
190#define CRT_ID_DISPLAY_FIFO 0x3B
191#define CRT_ID_LACE_RETR_START 0x3C
192/* S3 extensions: System Control Registers */
193#define CRT_ID_SYSTEM_CONFIG 0x40
194#define CRT_ID_BIOS_FLAG 0x41
195#define CRT_ID_LACE_CONTROL 0x42
196#define CRT_ID_EXT_MODE 0x43
197#define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */
198#define CRT_ID_HWGC_ORIGIN_X_HI 0x46
199#define CRT_ID_HWGC_ORIGIN_X_LO 0x47
200#define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
201#define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
202#define CRT_ID_HWGC_FG_STACK 0x4A
203#define CRT_ID_HWGC_BG_STACK 0x4B
204#define CRT_ID_HWGC_START_AD_HI 0x4C
205#define CRT_ID_HWGC_START_AD_LO 0x4D
206#define CRT_ID_HWGC_DSTART_X 0x4E
207#define CRT_ID_HWGC_DSTART_Y 0x4F
208/* S3 extensions: System Extension Registers */
209#define CRT_ID_EXT_SYS_CNTL_1 0x50 /* NOT a virge register */
210#define CRT_ID_EXT_SYS_CNTL_2 0x51
211#define CRT_ID_EXT_BIOS_FLAG_1 0x52
212#define CRT_ID_EXT_MEM_CNTL_1 0x53
213#define CRT_ID_EXT_MEM_CNTL_2 0x54
214#define CRT_ID_EXT_DAC_CNTL 0x55
215#define CRT_ID_EX_SYNC_1 0x56
216#define CRT_ID_EX_SYNC_2 0x57
217#define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */
218#define CRT_ID_LAW_POS_HI 0x59
219#define CRT_ID_LAW_POS_LO 0x5A
220#define CRT_ID_GOUT_PORT 0x5C
221#define CRT_ID_EXT_HOR_OVF 0x5D
222#define CRT_ID_EXT_VER_OVF 0x5E
223#define CRT_ID_EXT_MEM_CNTL_3 0x60 /* NOT a virge register */
224#define CRT_ID_EXT_MEM_CNTL_4 0x61
225#define CRT_ID_EX_SYNC_3 0x63 /* NOT a virge register */
226#define CRT_ID_EXT_MISC_CNTL 0x65
227#define CRT_ID_EXT_MISC_CNTL_1 0x66
228#define CRT_ID_EXT_MISC_CNTL_2 0x67
229#define CRT_ID_CONFIG_3 0x68
230#define CRT_ID_EXT_SYS_CNTL_3 0x69
231#define CRT_ID_EXT_SYS_CNTL_4 0x6A
232#define CRT_ID_EXT_BIOS_FLAG_3 0x6B
233#define CRT_ID_EXT_BIOS_FLAG_4 0x6C
234/* S3 virge extensions: more System Extension Registers */
235#define CRT_ID_EXT_BIOS_FLAG_5 0x6D
236#define CRT_ID_EXT_DAC_TEST 0x6E
237#define CRT_ID_CONFIG_4 0x6F
238
239/* Video DAC */
240#define VDAC_ADDRESS 0x03c8
241#define VDAC_ADDRESS_W 0x03c8
242#define VDAC_ADDRESS_R 0x03c7
243#define VDAC_STATE 0x03c7
244#define VDAC_DATA 0x03c9
245#define VDAC_MASK 0x03c6
246
247/* Miscellaneous Registers */
248#define MR_SUBSYSTEM_STATUS_R 0x8504 /* new for virge */
249#define MR_SUBSYSTEM_CNTL_W 0x8504 /* new for virge */
250#define MR_ADVANCED_FUNCTION_CONTROL 0x850C /* new for virge */
251
252/* Blitter */
253#define BLT_COMMAND_SET 0xA500
254#define BLT_SIZE_X_Y 0xA504
255#define BLT_SRC_X_Y 0xA508
256#define BLT_DEST_X_Y 0xA50C
257
258#define BLT_SRC_BASE 0xa4d4
259#define BLT_DEST_BASE 0xa4d8
260#define BLT_CLIP_LEFT_RIGHT 0xa4dc
261#define BLT_CLIP_TOP_BOTTOM 0xa4e0
262#define BLT_SRC_DEST_STRIDE 0xa4e4
263#define BLT_MONO_PATTERN_0 0xa4e8
264#define BLT_MONO_PATTERN_1 0xa4ec
265#define BLT_PATTERN_COLOR 0xa4f4
266
267#define L2D_COMMAND_SET 0xA900
268#define L2D_CLIP_LEFT_RIGHT 0xA8DC
269#define L2D_CLIP_TOP_BOTTOM 0xA8E0
270
271#define P2D_COMMAND_SET 0xAD00
272#define P2D_CLIP_LEFT_RIGHT 0xACDC
273#define P2D_CLIP_TOP_BOTTOM 0xACE0
274
275#define CMD_NOP (0xf << 27) /* %1111 << 27, was 0x07 */
276#define S3V_BITBLT (0x0 << 27)
277#define S3V_RECTFILL (0x2 << 27)
278#define S3V_AUTOEXE 0x01
279#define S3V_HWCLIP 0x02
280#define S3V_DRAW 0x20
281#define S3V_DST_8BPP 0x00
282#define S3V_DST_16BPP 0x04
283#define S3V_DST_24BPP 0x08
284#define S3V_MONO_PAT 0x100
285
286#define S3V_BLT_COPY (0xcc<<17)
287#define S3V_BLT_CLEAR (0x00<<17)
288#define S3V_BLT_SET (0xff<<17)