Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/seq_file.h> |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
| 31 | #include "radeon_reg.h" |
| 32 | #include "radeon.h" |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 33 | #include "radeon_drm.h" |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 34 | #include "r100_track.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 35 | #include "r300d.h" |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 36 | #include "rv350d.h" |
Dave Airlie | 50f1530 | 2009-08-21 13:21:01 +1000 | [diff] [blame] | 37 | #include "r300_reg_safe.h" |
| 38 | |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 39 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 40 | |
| 41 | /* |
| 42 | * rv370,rv380 PCIE GART |
| 43 | */ |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 44 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
| 45 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 46 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
| 47 | { |
| 48 | uint32_t tmp; |
| 49 | int i; |
| 50 | |
| 51 | /* Workaround HW bug do flush 2 times */ |
| 52 | for (i = 0; i < 2; i++) { |
| 53 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| 54 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
| 55 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| 56 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 57 | } |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 58 | mb(); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 59 | } |
| 60 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 61 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
| 62 | { |
| 63 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
| 64 | |
| 65 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
| 66 | return -EINVAL; |
| 67 | } |
| 68 | addr = (lower_32_bits(addr) >> 8) | |
| 69 | ((upper_32_bits(addr) & 0xff) << 24) | |
| 70 | 0xc; |
| 71 | /* on x86 we want this to be CPU endian, on powerpc |
| 72 | * on powerpc without HW swappers, it'll get swapped on way |
| 73 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
| 74 | writel(addr, ((void __iomem *)ptr) + (i * 4)); |
| 75 | return 0; |
| 76 | } |
| 77 | |
| 78 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
| 79 | { |
| 80 | int r; |
| 81 | |
| 82 | if (rdev->gart.table.vram.robj) { |
| 83 | WARN(1, "RV370 PCIE GART already initialized.\n"); |
| 84 | return 0; |
| 85 | } |
| 86 | /* Initialize common gart structure */ |
| 87 | r = radeon_gart_init(rdev); |
| 88 | if (r) |
| 89 | return r; |
| 90 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
| 91 | if (r) |
| 92 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
| 93 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
| 94 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 95 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| 96 | return radeon_gart_table_vram_alloc(rdev); |
| 97 | } |
| 98 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 99 | int rv370_pcie_gart_enable(struct radeon_device *rdev) |
| 100 | { |
| 101 | uint32_t table_addr; |
| 102 | uint32_t tmp; |
| 103 | int r; |
| 104 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 105 | if (rdev->gart.table.vram.robj == NULL) { |
| 106 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 107 | return -EINVAL; |
| 108 | } |
| 109 | r = radeon_gart_table_vram_pin(rdev); |
| 110 | if (r) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 111 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 112 | /* discard memory request outside of configured range */ |
| 113 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
| 114 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
| 115 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 116 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 117 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
| 118 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
| 119 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
| 120 | table_addr = rdev->gart.table_addr; |
| 121 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
| 122 | /* FIXME: setup default page */ |
| 123 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); |
| 124 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
| 125 | /* Clear error */ |
| 126 | WREG32_PCIE(0x18, 0); |
| 127 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| 128 | tmp |= RADEON_PCIE_TX_GART_EN; |
| 129 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
| 130 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
| 131 | rv370_pcie_gart_tlb_flush(rdev); |
| 132 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 133 | (unsigned)(rdev->mc.gtt_size >> 20), table_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 134 | rdev->gart.ready = true; |
| 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
| 139 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 140 | u32 tmp; |
| 141 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 142 | |
| 143 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| 144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
| 145 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
| 146 | if (rdev->gart.table.vram.robj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 147 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
| 148 | if (likely(r == 0)) { |
| 149 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
| 150 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
| 151 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
| 152 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 156 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | { |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 158 | rv370_pcie_gart_disable(rdev); |
| 159 | radeon_gart_table_vram_free(rdev); |
| 160 | radeon_gart_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | } |
| 162 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 163 | void r300_fence_ring_emit(struct radeon_device *rdev, |
| 164 | struct radeon_fence *fence) |
| 165 | { |
| 166 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
| 167 | * for enough space (today caller are ib schedule and buffer move) */ |
| 168 | /* Write SC register so SC & US assert idle */ |
| 169 | radeon_ring_write(rdev, PACKET0(0x43E0, 0)); |
| 170 | radeon_ring_write(rdev, 0); |
| 171 | radeon_ring_write(rdev, PACKET0(0x43E4, 0)); |
| 172 | radeon_ring_write(rdev, 0); |
| 173 | /* Flush 3D cache */ |
| 174 | radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); |
| 175 | radeon_ring_write(rdev, (2 << 0)); |
| 176 | radeon_ring_write(rdev, PACKET0(0x4F18, 0)); |
| 177 | radeon_ring_write(rdev, (1 << 0)); |
| 178 | /* Wait until IDLE & CLEAN */ |
| 179 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
| 180 | radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); |
| 181 | /* Emit fence sequence & fire IRQ */ |
| 182 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
| 183 | radeon_ring_write(rdev, fence->seq); |
| 184 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
| 185 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
| 186 | } |
| 187 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 188 | int r300_copy_dma(struct radeon_device *rdev, |
| 189 | uint64_t src_offset, |
| 190 | uint64_t dst_offset, |
| 191 | unsigned num_pages, |
| 192 | struct radeon_fence *fence) |
| 193 | { |
| 194 | uint32_t size; |
| 195 | uint32_t cur_size; |
| 196 | int i, num_loops; |
| 197 | int r = 0; |
| 198 | |
| 199 | /* radeon pitch is /64 */ |
| 200 | size = num_pages << PAGE_SHIFT; |
| 201 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
| 202 | r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
| 203 | if (r) { |
| 204 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
| 205 | return r; |
| 206 | } |
| 207 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 208 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 209 | radeon_ring_write(rdev, (1 << 16)); |
| 210 | for (i = 0; i < num_loops; i++) { |
| 211 | cur_size = size; |
| 212 | if (cur_size > 0x1FFFFF) { |
| 213 | cur_size = 0x1FFFFF; |
| 214 | } |
| 215 | size -= cur_size; |
| 216 | radeon_ring_write(rdev, PACKET0(0x720, 2)); |
| 217 | radeon_ring_write(rdev, src_offset); |
| 218 | radeon_ring_write(rdev, dst_offset); |
| 219 | radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
| 220 | src_offset += cur_size; |
| 221 | dst_offset += cur_size; |
| 222 | } |
| 223 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 224 | radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
| 225 | if (fence) { |
| 226 | r = radeon_fence_emit(rdev, fence); |
| 227 | } |
| 228 | radeon_ring_unlock_commit(rdev); |
| 229 | return r; |
| 230 | } |
| 231 | |
| 232 | void r300_ring_start(struct radeon_device *rdev) |
| 233 | { |
| 234 | unsigned gb_tile_config; |
| 235 | int r; |
| 236 | |
| 237 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
| 238 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 239 | switch(rdev->num_gb_pipes) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 240 | case 2: |
| 241 | gb_tile_config |= R300_PIPE_COUNT_R300; |
| 242 | break; |
| 243 | case 3: |
| 244 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
| 245 | break; |
| 246 | case 4: |
| 247 | gb_tile_config |= R300_PIPE_COUNT_R420; |
| 248 | break; |
| 249 | case 1: |
| 250 | default: |
| 251 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
| 252 | break; |
| 253 | } |
| 254 | |
| 255 | r = radeon_ring_lock(rdev, 64); |
| 256 | if (r) { |
| 257 | return; |
| 258 | } |
| 259 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
| 260 | radeon_ring_write(rdev, |
| 261 | RADEON_ISYNC_ANY2D_IDLE3D | |
| 262 | RADEON_ISYNC_ANY3D_IDLE2D | |
| 263 | RADEON_ISYNC_WAIT_IDLEGUI | |
| 264 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
| 265 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
| 266 | radeon_ring_write(rdev, gb_tile_config); |
| 267 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 268 | radeon_ring_write(rdev, |
| 269 | RADEON_WAIT_2D_IDLECLEAN | |
| 270 | RADEON_WAIT_3D_IDLECLEAN); |
| 271 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
| 272 | radeon_ring_write(rdev, 1 << 31); |
| 273 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
| 274 | radeon_ring_write(rdev, 0); |
| 275 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
| 276 | radeon_ring_write(rdev, 0); |
| 277 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
| 278 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
| 279 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
| 280 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
| 281 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 282 | radeon_ring_write(rdev, |
| 283 | RADEON_WAIT_2D_IDLECLEAN | |
| 284 | RADEON_WAIT_3D_IDLECLEAN); |
| 285 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
| 286 | radeon_ring_write(rdev, 0); |
| 287 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
| 288 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
| 289 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
| 290 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
| 291 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
| 292 | radeon_ring_write(rdev, |
| 293 | ((6 << R300_MS_X0_SHIFT) | |
| 294 | (6 << R300_MS_Y0_SHIFT) | |
| 295 | (6 << R300_MS_X1_SHIFT) | |
| 296 | (6 << R300_MS_Y1_SHIFT) | |
| 297 | (6 << R300_MS_X2_SHIFT) | |
| 298 | (6 << R300_MS_Y2_SHIFT) | |
| 299 | (6 << R300_MSBD0_Y_SHIFT) | |
| 300 | (6 << R300_MSBD0_X_SHIFT))); |
| 301 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
| 302 | radeon_ring_write(rdev, |
| 303 | ((6 << R300_MS_X3_SHIFT) | |
| 304 | (6 << R300_MS_Y3_SHIFT) | |
| 305 | (6 << R300_MS_X4_SHIFT) | |
| 306 | (6 << R300_MS_Y4_SHIFT) | |
| 307 | (6 << R300_MS_X5_SHIFT) | |
| 308 | (6 << R300_MS_Y5_SHIFT) | |
| 309 | (6 << R300_MSBD1_SHIFT))); |
| 310 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
| 311 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
| 312 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
| 313 | radeon_ring_write(rdev, |
| 314 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
| 315 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
| 316 | radeon_ring_write(rdev, |
| 317 | R300_GEOMETRY_ROUND_NEAREST | |
| 318 | R300_COLOR_ROUND_NEAREST); |
| 319 | radeon_ring_unlock_commit(rdev); |
| 320 | } |
| 321 | |
| 322 | void r300_errata(struct radeon_device *rdev) |
| 323 | { |
| 324 | rdev->pll_errata = 0; |
| 325 | |
| 326 | if (rdev->family == CHIP_R300 && |
| 327 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { |
| 328 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | int r300_mc_wait_for_idle(struct radeon_device *rdev) |
| 333 | { |
| 334 | unsigned i; |
| 335 | uint32_t tmp; |
| 336 | |
| 337 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 338 | /* read MC_STATUS */ |
| 339 | tmp = RREG32(0x0150); |
| 340 | if (tmp & (1 << 4)) { |
| 341 | return 0; |
| 342 | } |
| 343 | DRM_UDELAY(1); |
| 344 | } |
| 345 | return -1; |
| 346 | } |
| 347 | |
| 348 | void r300_gpu_init(struct radeon_device *rdev) |
| 349 | { |
| 350 | uint32_t gb_tile_config, tmp; |
| 351 | |
| 352 | r100_hdp_reset(rdev); |
| 353 | /* FIXME: rv380 one pipes ? */ |
| 354 | if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { |
| 355 | /* r300,r350 */ |
| 356 | rdev->num_gb_pipes = 2; |
| 357 | } else { |
| 358 | /* rv350,rv370,rv380 */ |
| 359 | rdev->num_gb_pipes = 1; |
| 360 | } |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 361 | rdev->num_z_pipes = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 362 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
| 363 | switch (rdev->num_gb_pipes) { |
| 364 | case 2: |
| 365 | gb_tile_config |= R300_PIPE_COUNT_R300; |
| 366 | break; |
| 367 | case 3: |
| 368 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
| 369 | break; |
| 370 | case 4: |
| 371 | gb_tile_config |= R300_PIPE_COUNT_R420; |
| 372 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 373 | default: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 374 | case 1: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 375 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
| 376 | break; |
| 377 | } |
| 378 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); |
| 379 | |
| 380 | if (r100_gui_wait_for_idle(rdev)) { |
| 381 | printk(KERN_WARNING "Failed to wait GUI idle while " |
| 382 | "programming pipes. Bad things might happen.\n"); |
| 383 | } |
| 384 | |
| 385 | tmp = RREG32(0x170C); |
| 386 | WREG32(0x170C, tmp | (1 << 31)); |
| 387 | |
| 388 | WREG32(R300_RB2D_DSTCACHE_MODE, |
| 389 | R300_DC_AUTOFLUSH_ENABLE | |
| 390 | R300_DC_DC_DISABLE_IGNORE_PE); |
| 391 | |
| 392 | if (r100_gui_wait_for_idle(rdev)) { |
| 393 | printk(KERN_WARNING "Failed to wait GUI idle while " |
| 394 | "programming pipes. Bad things might happen.\n"); |
| 395 | } |
| 396 | if (r300_mc_wait_for_idle(rdev)) { |
| 397 | printk(KERN_WARNING "Failed to wait MC idle while " |
| 398 | "programming pipes. Bad things might happen.\n"); |
| 399 | } |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 400 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
| 401 | rdev->num_gb_pipes, rdev->num_z_pipes); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 402 | } |
| 403 | |
| 404 | int r300_ga_reset(struct radeon_device *rdev) |
| 405 | { |
| 406 | uint32_t tmp; |
| 407 | bool reinit_cp; |
| 408 | int i; |
| 409 | |
| 410 | reinit_cp = rdev->cp.ready; |
| 411 | rdev->cp.ready = false; |
| 412 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 413 | WREG32(RADEON_CP_CSQ_MODE, 0); |
| 414 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 415 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
| 416 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
| 417 | udelay(200); |
| 418 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| 419 | /* Wait to prevent race in RBBM_STATUS */ |
| 420 | mdelay(1); |
| 421 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 422 | if (tmp & ((1 << 20) | (1 << 26))) { |
| 423 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); |
| 424 | /* GA still busy soft reset it */ |
| 425 | WREG32(0x429C, 0x200); |
| 426 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
| 427 | WREG32(0x43E0, 0); |
| 428 | WREG32(0x43E4, 0); |
| 429 | WREG32(0x24AC, 0); |
| 430 | } |
| 431 | /* Wait to prevent race in RBBM_STATUS */ |
| 432 | mdelay(1); |
| 433 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 434 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
| 435 | break; |
| 436 | } |
| 437 | } |
| 438 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 439 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 440 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
| 441 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
| 442 | tmp); |
| 443 | if (reinit_cp) { |
| 444 | return r100_cp_init(rdev, rdev->cp.ring_size); |
| 445 | } |
| 446 | return 0; |
| 447 | } |
| 448 | DRM_UDELAY(1); |
| 449 | } |
| 450 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 451 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
| 452 | return -1; |
| 453 | } |
| 454 | |
| 455 | int r300_gpu_reset(struct radeon_device *rdev) |
| 456 | { |
| 457 | uint32_t status; |
| 458 | |
| 459 | /* reset order likely matter */ |
| 460 | status = RREG32(RADEON_RBBM_STATUS); |
| 461 | /* reset HDP */ |
| 462 | r100_hdp_reset(rdev); |
| 463 | /* reset rb2d */ |
| 464 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
| 465 | r100_rb2d_reset(rdev); |
| 466 | } |
| 467 | /* reset GA */ |
| 468 | if (status & ((1 << 20) | (1 << 26))) { |
| 469 | r300_ga_reset(rdev); |
| 470 | } |
| 471 | /* reset CP */ |
| 472 | status = RREG32(RADEON_RBBM_STATUS); |
| 473 | if (status & (1 << 16)) { |
| 474 | r100_cp_reset(rdev); |
| 475 | } |
| 476 | /* Check if GPU is idle */ |
| 477 | status = RREG32(RADEON_RBBM_STATUS); |
| 478 | if (status & (1 << 31)) { |
| 479 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
| 480 | return -1; |
| 481 | } |
| 482 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | |
| 487 | /* |
| 488 | * r300,r350,rv350,rv380 VRAM info |
| 489 | */ |
| 490 | void r300_vram_info(struct radeon_device *rdev) |
| 491 | { |
| 492 | uint32_t tmp; |
| 493 | |
| 494 | /* DDR for all card after R300 & IGP */ |
| 495 | rdev->mc.vram_is_ddr = true; |
| 496 | tmp = RREG32(RADEON_MEM_CNTL); |
| 497 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
| 498 | rdev->mc.vram_width = 128; |
| 499 | } else { |
| 500 | rdev->mc.vram_width = 64; |
| 501 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 502 | |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 503 | r100_vram_init_sizes(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 504 | } |
| 505 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 506 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
| 507 | { |
| 508 | uint32_t link_width_cntl, mask; |
| 509 | |
| 510 | if (rdev->flags & RADEON_IS_IGP) |
| 511 | return; |
| 512 | |
| 513 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 514 | return; |
| 515 | |
| 516 | /* FIXME wait for idle */ |
| 517 | |
| 518 | switch (lanes) { |
| 519 | case 0: |
| 520 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
| 521 | break; |
| 522 | case 1: |
| 523 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
| 524 | break; |
| 525 | case 2: |
| 526 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
| 527 | break; |
| 528 | case 4: |
| 529 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
| 530 | break; |
| 531 | case 8: |
| 532 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
| 533 | break; |
| 534 | case 12: |
| 535 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
| 536 | break; |
| 537 | case 16: |
| 538 | default: |
| 539 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
| 540 | break; |
| 541 | } |
| 542 | |
| 543 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
| 544 | |
| 545 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
| 546 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
| 547 | return; |
| 548 | |
| 549 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
| 550 | RADEON_PCIE_LC_RECONFIG_NOW | |
| 551 | RADEON_PCIE_LC_RECONFIG_LATER | |
| 552 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); |
| 553 | link_width_cntl |= mask; |
| 554 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 555 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
| 556 | RADEON_PCIE_LC_RECONFIG_NOW)); |
| 557 | |
| 558 | /* wait for lane set to complete */ |
| 559 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
| 560 | while (link_width_cntl == 0xffffffff) |
| 561 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
| 562 | |
| 563 | } |
| 564 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 565 | #if defined(CONFIG_DEBUG_FS) |
| 566 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
| 567 | { |
| 568 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 569 | struct drm_device *dev = node->minor->dev; |
| 570 | struct radeon_device *rdev = dev->dev_private; |
| 571 | uint32_t tmp; |
| 572 | |
| 573 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| 574 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); |
| 575 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); |
| 576 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); |
| 577 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); |
| 578 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); |
| 579 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); |
| 580 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); |
| 581 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); |
| 582 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); |
| 583 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); |
| 584 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); |
| 585 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); |
| 586 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); |
| 587 | return 0; |
| 588 | } |
| 589 | |
| 590 | static struct drm_info_list rv370_pcie_gart_info_list[] = { |
| 591 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, |
| 592 | }; |
| 593 | #endif |
| 594 | |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 595 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 596 | { |
| 597 | #if defined(CONFIG_DEBUG_FS) |
| 598 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
| 599 | #else |
| 600 | return 0; |
| 601 | #endif |
| 602 | } |
| 603 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 604 | static int r300_packet0_check(struct radeon_cs_parser *p, |
| 605 | struct radeon_cs_packet *pkt, |
| 606 | unsigned idx, unsigned reg) |
| 607 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 608 | struct radeon_cs_reloc *reloc; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 609 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 610 | volatile uint32_t *ib; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 611 | uint32_t tmp, tile_flags = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 612 | unsigned i; |
| 613 | int r; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 614 | u32 idx_value; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 615 | |
| 616 | ib = p->ib->ptr; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 617 | track = (struct r100_cs_track *)p->track; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 618 | idx_value = radeon_get_ib_value(p, idx); |
| 619 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 620 | switch(reg) { |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 621 | case AVIVO_D1MODE_VLINE_START_END: |
| 622 | case RADEON_CRTC_GUI_TRIG_VLINE: |
| 623 | r = r100_cs_packet_parse_vline(p); |
| 624 | if (r) { |
| 625 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 626 | idx, reg); |
| 627 | r100_cs_dump_packet(p, pkt); |
| 628 | return r; |
| 629 | } |
| 630 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 631 | case RADEON_DST_PITCH_OFFSET: |
| 632 | case RADEON_SRC_PITCH_OFFSET: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 633 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
| 634 | if (r) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 635 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 636 | break; |
| 637 | case R300_RB3D_COLOROFFSET0: |
| 638 | case R300_RB3D_COLOROFFSET1: |
| 639 | case R300_RB3D_COLOROFFSET2: |
| 640 | case R300_RB3D_COLOROFFSET3: |
| 641 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; |
| 642 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 643 | if (r) { |
| 644 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 645 | idx, reg); |
| 646 | r100_cs_dump_packet(p, pkt); |
| 647 | return r; |
| 648 | } |
| 649 | track->cb[i].robj = reloc->robj; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 650 | track->cb[i].offset = idx_value; |
| 651 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 652 | break; |
| 653 | case R300_ZB_DEPTHOFFSET: |
| 654 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 655 | if (r) { |
| 656 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 657 | idx, reg); |
| 658 | r100_cs_dump_packet(p, pkt); |
| 659 | return r; |
| 660 | } |
| 661 | track->zb.robj = reloc->robj; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 662 | track->zb.offset = idx_value; |
| 663 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 664 | break; |
| 665 | case R300_TX_OFFSET_0: |
| 666 | case R300_TX_OFFSET_0+4: |
| 667 | case R300_TX_OFFSET_0+8: |
| 668 | case R300_TX_OFFSET_0+12: |
| 669 | case R300_TX_OFFSET_0+16: |
| 670 | case R300_TX_OFFSET_0+20: |
| 671 | case R300_TX_OFFSET_0+24: |
| 672 | case R300_TX_OFFSET_0+28: |
| 673 | case R300_TX_OFFSET_0+32: |
| 674 | case R300_TX_OFFSET_0+36: |
| 675 | case R300_TX_OFFSET_0+40: |
| 676 | case R300_TX_OFFSET_0+44: |
| 677 | case R300_TX_OFFSET_0+48: |
| 678 | case R300_TX_OFFSET_0+52: |
| 679 | case R300_TX_OFFSET_0+56: |
| 680 | case R300_TX_OFFSET_0+60: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 681 | i = (reg - R300_TX_OFFSET_0) >> 2; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 682 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 683 | if (r) { |
| 684 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 685 | idx, reg); |
| 686 | r100_cs_dump_packet(p, pkt); |
| 687 | return r; |
| 688 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 689 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 690 | track->textures[i].robj = reloc->robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 691 | break; |
| 692 | /* Tracked registers */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 693 | case 0x2084: |
| 694 | /* VAP_VF_CNTL */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 695 | track->vap_vf_cntl = idx_value; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 696 | break; |
| 697 | case 0x20B4: |
| 698 | /* VAP_VTX_SIZE */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 699 | track->vtx_size = idx_value & 0x7F; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 700 | break; |
| 701 | case 0x2134: |
| 702 | /* VAP_VF_MAX_VTX_INDX */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 703 | track->max_indx = idx_value & 0x00FFFFFFUL; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 704 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 705 | case 0x43E4: |
| 706 | /* SC_SCISSOR1 */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 707 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 708 | if (p->rdev->family < CHIP_RV515) { |
| 709 | track->maxy -= 1440; |
| 710 | } |
| 711 | break; |
| 712 | case 0x4E00: |
| 713 | /* RB3D_CCTL */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 714 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 715 | break; |
| 716 | case 0x4E38: |
| 717 | case 0x4E3C: |
| 718 | case 0x4E40: |
| 719 | case 0x4E44: |
| 720 | /* RB3D_COLORPITCH0 */ |
| 721 | /* RB3D_COLORPITCH1 */ |
| 722 | /* RB3D_COLORPITCH2 */ |
| 723 | /* RB3D_COLORPITCH3 */ |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 724 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 725 | if (r) { |
| 726 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 727 | idx, reg); |
| 728 | r100_cs_dump_packet(p, pkt); |
| 729 | return r; |
| 730 | } |
| 731 | |
| 732 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| 733 | tile_flags |= R300_COLOR_TILE_ENABLE; |
| 734 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| 735 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
| 736 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 737 | tmp = idx_value & ~(0x7 << 16); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 738 | tmp |= tile_flags; |
| 739 | ib[idx] = tmp; |
| 740 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 741 | i = (reg - 0x4E38) >> 2; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 742 | track->cb[i].pitch = idx_value & 0x3FFE; |
| 743 | switch (((idx_value >> 21) & 0xF)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 744 | case 9: |
| 745 | case 11: |
| 746 | case 12: |
| 747 | track->cb[i].cpp = 1; |
| 748 | break; |
| 749 | case 3: |
| 750 | case 4: |
| 751 | case 13: |
| 752 | case 15: |
| 753 | track->cb[i].cpp = 2; |
| 754 | break; |
| 755 | case 6: |
| 756 | track->cb[i].cpp = 4; |
| 757 | break; |
| 758 | case 10: |
| 759 | track->cb[i].cpp = 8; |
| 760 | break; |
| 761 | case 7: |
| 762 | track->cb[i].cpp = 16; |
| 763 | break; |
| 764 | default: |
| 765 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 766 | ((idx_value >> 21) & 0xF)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 767 | return -EINVAL; |
| 768 | } |
| 769 | break; |
| 770 | case 0x4F00: |
| 771 | /* ZB_CNTL */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 772 | if (idx_value & 2) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 773 | track->z_enabled = true; |
| 774 | } else { |
| 775 | track->z_enabled = false; |
| 776 | } |
| 777 | break; |
| 778 | case 0x4F10: |
| 779 | /* ZB_FORMAT */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 780 | switch ((idx_value & 0xF)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 781 | case 0: |
| 782 | case 1: |
| 783 | track->zb.cpp = 2; |
| 784 | break; |
| 785 | case 2: |
| 786 | track->zb.cpp = 4; |
| 787 | break; |
| 788 | default: |
| 789 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 790 | (idx_value & 0xF)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 791 | return -EINVAL; |
| 792 | } |
| 793 | break; |
| 794 | case 0x4F24: |
| 795 | /* ZB_DEPTHPITCH */ |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 796 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 797 | if (r) { |
| 798 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 799 | idx, reg); |
| 800 | r100_cs_dump_packet(p, pkt); |
| 801 | return r; |
| 802 | } |
| 803 | |
| 804 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| 805 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
| 806 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| 807 | tile_flags |= R300_DEPTHMICROTILE_TILED;; |
| 808 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 809 | tmp = idx_value & ~(0x7 << 16); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 810 | tmp |= tile_flags; |
| 811 | ib[idx] = tmp; |
| 812 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 813 | track->zb.pitch = idx_value & 0x3FFC; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 814 | break; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 815 | case 0x4104: |
| 816 | for (i = 0; i < 16; i++) { |
| 817 | bool enabled; |
| 818 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 819 | enabled = !!(idx_value & (1 << i)); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 820 | track->textures[i].enabled = enabled; |
| 821 | } |
| 822 | break; |
| 823 | case 0x44C0: |
| 824 | case 0x44C4: |
| 825 | case 0x44C8: |
| 826 | case 0x44CC: |
| 827 | case 0x44D0: |
| 828 | case 0x44D4: |
| 829 | case 0x44D8: |
| 830 | case 0x44DC: |
| 831 | case 0x44E0: |
| 832 | case 0x44E4: |
| 833 | case 0x44E8: |
| 834 | case 0x44EC: |
| 835 | case 0x44F0: |
| 836 | case 0x44F4: |
| 837 | case 0x44F8: |
| 838 | case 0x44FC: |
| 839 | /* TX_FORMAT1_[0-15] */ |
| 840 | i = (reg - 0x44C0) >> 2; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 841 | tmp = (idx_value >> 25) & 0x3; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 842 | track->textures[i].tex_coord_type = tmp; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 843 | switch ((idx_value & 0x1F)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 844 | case R300_TX_FORMAT_X8: |
| 845 | case R300_TX_FORMAT_Y4X4: |
| 846 | case R300_TX_FORMAT_Z3Y3X2: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 847 | track->textures[i].cpp = 1; |
| 848 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 849 | case R300_TX_FORMAT_X16: |
| 850 | case R300_TX_FORMAT_Y8X8: |
| 851 | case R300_TX_FORMAT_Z5Y6X5: |
| 852 | case R300_TX_FORMAT_Z6Y5X5: |
| 853 | case R300_TX_FORMAT_W4Z4Y4X4: |
| 854 | case R300_TX_FORMAT_W1Z5Y5X5: |
| 855 | case R300_TX_FORMAT_DXT1: |
| 856 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
| 857 | case R300_TX_FORMAT_B8G8_B8G8: |
| 858 | case R300_TX_FORMAT_G8R8_G8B8: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 859 | track->textures[i].cpp = 2; |
| 860 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 861 | case R300_TX_FORMAT_Y16X16: |
| 862 | case R300_TX_FORMAT_Z11Y11X10: |
| 863 | case R300_TX_FORMAT_Z10Y11X11: |
| 864 | case R300_TX_FORMAT_W8Z8Y8X8: |
| 865 | case R300_TX_FORMAT_W2Z10Y10X10: |
| 866 | case 0x17: |
| 867 | case R300_TX_FORMAT_FL_I32: |
| 868 | case 0x1e: |
| 869 | case R300_TX_FORMAT_DXT3: |
| 870 | case R300_TX_FORMAT_DXT5: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 871 | track->textures[i].cpp = 4; |
| 872 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 873 | case R300_TX_FORMAT_W16Z16Y16X16: |
| 874 | case R300_TX_FORMAT_FL_R16G16B16A16: |
| 875 | case R300_TX_FORMAT_FL_I32A32: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 876 | track->textures[i].cpp = 8; |
| 877 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 878 | case R300_TX_FORMAT_FL_R32G32B32A32: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 879 | track->textures[i].cpp = 16; |
| 880 | break; |
| 881 | default: |
| 882 | DRM_ERROR("Invalid texture format %u\n", |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 883 | (idx_value & 0x1F)); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 884 | return -EINVAL; |
| 885 | break; |
| 886 | } |
| 887 | break; |
| 888 | case 0x4400: |
| 889 | case 0x4404: |
| 890 | case 0x4408: |
| 891 | case 0x440C: |
| 892 | case 0x4410: |
| 893 | case 0x4414: |
| 894 | case 0x4418: |
| 895 | case 0x441C: |
| 896 | case 0x4420: |
| 897 | case 0x4424: |
| 898 | case 0x4428: |
| 899 | case 0x442C: |
| 900 | case 0x4430: |
| 901 | case 0x4434: |
| 902 | case 0x4438: |
| 903 | case 0x443C: |
| 904 | /* TX_FILTER0_[0-15] */ |
| 905 | i = (reg - 0x4400) >> 2; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 906 | tmp = idx_value & 0x7; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 907 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
| 908 | track->textures[i].roundup_w = false; |
| 909 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 910 | tmp = (idx_value >> 3) & 0x7; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 911 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
| 912 | track->textures[i].roundup_h = false; |
| 913 | } |
| 914 | break; |
| 915 | case 0x4500: |
| 916 | case 0x4504: |
| 917 | case 0x4508: |
| 918 | case 0x450C: |
| 919 | case 0x4510: |
| 920 | case 0x4514: |
| 921 | case 0x4518: |
| 922 | case 0x451C: |
| 923 | case 0x4520: |
| 924 | case 0x4524: |
| 925 | case 0x4528: |
| 926 | case 0x452C: |
| 927 | case 0x4530: |
| 928 | case 0x4534: |
| 929 | case 0x4538: |
| 930 | case 0x453C: |
| 931 | /* TX_FORMAT2_[0-15] */ |
| 932 | i = (reg - 0x4500) >> 2; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 933 | tmp = idx_value & 0x3FFF; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 934 | track->textures[i].pitch = tmp + 1; |
| 935 | if (p->rdev->family >= CHIP_RV515) { |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 936 | tmp = ((idx_value >> 15) & 1) << 11; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 937 | track->textures[i].width_11 = tmp; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 938 | tmp = ((idx_value >> 16) & 1) << 11; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 939 | track->textures[i].height_11 = tmp; |
| 940 | } |
| 941 | break; |
| 942 | case 0x4480: |
| 943 | case 0x4484: |
| 944 | case 0x4488: |
| 945 | case 0x448C: |
| 946 | case 0x4490: |
| 947 | case 0x4494: |
| 948 | case 0x4498: |
| 949 | case 0x449C: |
| 950 | case 0x44A0: |
| 951 | case 0x44A4: |
| 952 | case 0x44A8: |
| 953 | case 0x44AC: |
| 954 | case 0x44B0: |
| 955 | case 0x44B4: |
| 956 | case 0x44B8: |
| 957 | case 0x44BC: |
| 958 | /* TX_FORMAT0_[0-15] */ |
| 959 | i = (reg - 0x4480) >> 2; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 960 | tmp = idx_value & 0x7FF; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 961 | track->textures[i].width = tmp + 1; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 962 | tmp = (idx_value >> 11) & 0x7FF; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 963 | track->textures[i].height = tmp + 1; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 964 | tmp = (idx_value >> 26) & 0xF; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 965 | track->textures[i].num_levels = tmp; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 966 | tmp = idx_value & (1 << 31); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 967 | track->textures[i].use_pitch = !!tmp; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 968 | tmp = (idx_value >> 22) & 0xF; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 969 | track->textures[i].txdepth = tmp; |
| 970 | break; |
Dave Airlie | 3f8befe | 2009-08-15 20:54:13 +1000 | [diff] [blame] | 971 | case R300_ZB_ZPASS_ADDR: |
| 972 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 973 | if (r) { |
| 974 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 975 | idx, reg); |
| 976 | r100_cs_dump_packet(p, pkt); |
| 977 | return r; |
| 978 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 979 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 3f8befe | 2009-08-15 20:54:13 +1000 | [diff] [blame] | 980 | break; |
| 981 | case 0x4be8: |
| 982 | /* valid register only on RV530 */ |
| 983 | if (p->rdev->family == CHIP_RV530) |
| 984 | break; |
| 985 | /* fallthrough do not move */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 986 | default: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 987 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
| 988 | reg, idx); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 989 | return -EINVAL; |
| 990 | } |
| 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | static int r300_packet3_check(struct radeon_cs_parser *p, |
| 995 | struct radeon_cs_packet *pkt) |
| 996 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 997 | struct radeon_cs_reloc *reloc; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 998 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 999 | volatile uint32_t *ib; |
| 1000 | unsigned idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1001 | int r; |
| 1002 | |
| 1003 | ib = p->ib->ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1004 | idx = pkt->idx + 1; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1005 | track = (struct r100_cs_track *)p->track; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1006 | switch(pkt->opcode) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1007 | case PACKET3_3D_LOAD_VBPNTR: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1008 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
| 1009 | if (r) |
| 1010 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1011 | break; |
| 1012 | case PACKET3_INDX_BUFFER: |
| 1013 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1014 | if (r) { |
| 1015 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
| 1016 | r100_cs_dump_packet(p, pkt); |
| 1017 | return r; |
| 1018 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1019 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1020 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
| 1021 | if (r) { |
| 1022 | return r; |
| 1023 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1024 | break; |
| 1025 | /* Draw packet */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1026 | case PACKET3_3D_DRAW_IMMD: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1027 | /* Number of dwords is vtx_size * (num_vertices - 1) |
| 1028 | * PRIM_WALK must be equal to 3 vertex data in embedded |
| 1029 | * in cmd stream */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1030 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1031 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| 1032 | return -EINVAL; |
| 1033 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1034 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1035 | track->immd_dwords = pkt->count - 1; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1036 | r = r100_cs_track_check(p->rdev, track); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1037 | if (r) { |
| 1038 | return r; |
| 1039 | } |
| 1040 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1041 | case PACKET3_3D_DRAW_IMMD_2: |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1042 | /* Number of dwords is vtx_size * (num_vertices - 1) |
| 1043 | * PRIM_WALK must be equal to 3 vertex data in embedded |
| 1044 | * in cmd stream */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1045 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1046 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| 1047 | return -EINVAL; |
| 1048 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1049 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1050 | track->immd_dwords = pkt->count; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1051 | r = r100_cs_track_check(p->rdev, track); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1052 | if (r) { |
| 1053 | return r; |
| 1054 | } |
| 1055 | break; |
| 1056 | case PACKET3_3D_DRAW_VBUF: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1057 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1058 | r = r100_cs_track_check(p->rdev, track); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1059 | if (r) { |
| 1060 | return r; |
| 1061 | } |
| 1062 | break; |
| 1063 | case PACKET3_3D_DRAW_VBUF_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1064 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1065 | r = r100_cs_track_check(p->rdev, track); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1066 | if (r) { |
| 1067 | return r; |
| 1068 | } |
| 1069 | break; |
| 1070 | case PACKET3_3D_DRAW_INDX: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1071 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1072 | r = r100_cs_track_check(p->rdev, track); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1073 | if (r) { |
| 1074 | return r; |
| 1075 | } |
| 1076 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1077 | case PACKET3_3D_DRAW_INDX_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1078 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1079 | r = r100_cs_track_check(p->rdev, track); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1080 | if (r) { |
| 1081 | return r; |
| 1082 | } |
| 1083 | break; |
| 1084 | case PACKET3_NOP: |
| 1085 | break; |
| 1086 | default: |
| 1087 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
| 1088 | return -EINVAL; |
| 1089 | } |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
| 1093 | int r300_cs_parse(struct radeon_cs_parser *p) |
| 1094 | { |
| 1095 | struct radeon_cs_packet pkt; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1096 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1097 | int r; |
| 1098 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1099 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
| 1100 | r100_cs_track_clear(p->rdev, track); |
| 1101 | p->track = track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1102 | do { |
| 1103 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
| 1104 | if (r) { |
| 1105 | return r; |
| 1106 | } |
| 1107 | p->idx += pkt.count + 2; |
| 1108 | switch (pkt.type) { |
| 1109 | case PACKET_TYPE0: |
| 1110 | r = r100_cs_parse_packet0(p, &pkt, |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1111 | p->rdev->config.r300.reg_safe_bm, |
| 1112 | p->rdev->config.r300.reg_safe_bm_size, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1113 | &r300_packet0_check); |
| 1114 | break; |
| 1115 | case PACKET_TYPE2: |
| 1116 | break; |
| 1117 | case PACKET_TYPE3: |
| 1118 | r = r300_packet3_check(p, &pkt); |
| 1119 | break; |
| 1120 | default: |
| 1121 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
| 1122 | return -EINVAL; |
| 1123 | } |
| 1124 | if (r) { |
| 1125 | return r; |
| 1126 | } |
| 1127 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
| 1128 | return 0; |
| 1129 | } |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1130 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1131 | void r300_set_reg_safe(struct radeon_device *rdev) |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1132 | { |
| 1133 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
| 1134 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1135 | } |
| 1136 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1137 | void r300_mc_program(struct radeon_device *rdev) |
| 1138 | { |
| 1139 | struct r100_mc_save save; |
| 1140 | int r; |
| 1141 | |
| 1142 | r = r100_debugfs_mc_info_init(rdev); |
| 1143 | if (r) { |
| 1144 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
| 1145 | } |
| 1146 | |
| 1147 | /* Stops all mc clients */ |
| 1148 | r100_mc_stop(rdev, &save); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1149 | if (rdev->flags & RADEON_IS_AGP) { |
| 1150 | WREG32(R_00014C_MC_AGP_LOCATION, |
| 1151 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
| 1152 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
| 1153 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
| 1154 | WREG32(R_00015C_AGP_BASE_2, |
| 1155 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
| 1156 | } else { |
| 1157 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
| 1158 | WREG32(R_000170_AGP_BASE, 0); |
| 1159 | WREG32(R_00015C_AGP_BASE_2, 0); |
| 1160 | } |
| 1161 | /* Wait for mc idle */ |
| 1162 | if (r300_mc_wait_for_idle(rdev)) |
| 1163 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); |
| 1164 | /* Program MC, should be a 32bits limited address space */ |
| 1165 | WREG32(R_000148_MC_FB_LOCATION, |
| 1166 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
| 1167 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| 1168 | r100_mc_resume(rdev, &save); |
| 1169 | } |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1170 | |
| 1171 | void r300_clock_startup(struct radeon_device *rdev) |
| 1172 | { |
| 1173 | u32 tmp; |
| 1174 | |
| 1175 | if (radeon_dynclks != -1 && radeon_dynclks) |
| 1176 | radeon_legacy_set_clock_gating(rdev, 1); |
| 1177 | /* We need to force on some of the block */ |
| 1178 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
| 1179 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
| 1180 | if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) |
| 1181 | tmp |= S_00000D_FORCE_VAP(1); |
| 1182 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
| 1183 | } |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1184 | |
| 1185 | static int r300_startup(struct radeon_device *rdev) |
| 1186 | { |
| 1187 | int r; |
| 1188 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame^] | 1189 | /* set common regs */ |
| 1190 | r100_set_common_regs(rdev); |
| 1191 | /* program mc */ |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1192 | r300_mc_program(rdev); |
| 1193 | /* Resume clock */ |
| 1194 | r300_clock_startup(rdev); |
| 1195 | /* Initialize GPU configuration (# pipes, ...) */ |
| 1196 | r300_gpu_init(rdev); |
| 1197 | /* Initialize GART (initialize after TTM so we can allocate |
| 1198 | * memory through TTM but finalize after TTM) */ |
| 1199 | if (rdev->flags & RADEON_IS_PCIE) { |
| 1200 | r = rv370_pcie_gart_enable(rdev); |
| 1201 | if (r) |
| 1202 | return r; |
| 1203 | } |
Dave Airlie | 17e15b0 | 2009-11-05 15:36:53 +1000 | [diff] [blame] | 1204 | |
| 1205 | if (rdev->family == CHIP_R300 || |
| 1206 | rdev->family == CHIP_R350 || |
| 1207 | rdev->family == CHIP_RV350) |
| 1208 | r100_enable_bm(rdev); |
| 1209 | |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1210 | if (rdev->flags & RADEON_IS_PCI) { |
| 1211 | r = r100_pci_gart_enable(rdev); |
| 1212 | if (r) |
| 1213 | return r; |
| 1214 | } |
| 1215 | /* Enable IRQ */ |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1216 | r100_irq_set(rdev); |
| 1217 | /* 1M ring buffer */ |
| 1218 | r = r100_cp_init(rdev, 1024 * 1024); |
| 1219 | if (r) { |
| 1220 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| 1221 | return r; |
| 1222 | } |
| 1223 | r = r100_wb_init(rdev); |
| 1224 | if (r) |
| 1225 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| 1226 | r = r100_ib_init(rdev); |
| 1227 | if (r) { |
| 1228 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| 1229 | return r; |
| 1230 | } |
| 1231 | return 0; |
| 1232 | } |
| 1233 | |
| 1234 | int r300_resume(struct radeon_device *rdev) |
| 1235 | { |
| 1236 | /* Make sur GART are not working */ |
| 1237 | if (rdev->flags & RADEON_IS_PCIE) |
| 1238 | rv370_pcie_gart_disable(rdev); |
| 1239 | if (rdev->flags & RADEON_IS_PCI) |
| 1240 | r100_pci_gart_disable(rdev); |
| 1241 | /* Resume clock before doing reset */ |
| 1242 | r300_clock_startup(rdev); |
| 1243 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| 1244 | if (radeon_gpu_reset(rdev)) { |
| 1245 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 1246 | RREG32(R_000E40_RBBM_STATUS), |
| 1247 | RREG32(R_0007C0_CP_STAT)); |
| 1248 | } |
| 1249 | /* post */ |
| 1250 | radeon_combios_asic_init(rdev->ddev); |
| 1251 | /* Resume clock after posting */ |
| 1252 | r300_clock_startup(rdev); |
| 1253 | return r300_startup(rdev); |
| 1254 | } |
| 1255 | |
| 1256 | int r300_suspend(struct radeon_device *rdev) |
| 1257 | { |
| 1258 | r100_cp_disable(rdev); |
| 1259 | r100_wb_disable(rdev); |
| 1260 | r100_irq_disable(rdev); |
| 1261 | if (rdev->flags & RADEON_IS_PCIE) |
| 1262 | rv370_pcie_gart_disable(rdev); |
| 1263 | if (rdev->flags & RADEON_IS_PCI) |
| 1264 | r100_pci_gart_disable(rdev); |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
| 1268 | void r300_fini(struct radeon_device *rdev) |
| 1269 | { |
| 1270 | r300_suspend(rdev); |
| 1271 | r100_cp_fini(rdev); |
| 1272 | r100_wb_fini(rdev); |
| 1273 | r100_ib_fini(rdev); |
| 1274 | radeon_gem_fini(rdev); |
| 1275 | if (rdev->flags & RADEON_IS_PCIE) |
| 1276 | rv370_pcie_gart_fini(rdev); |
| 1277 | if (rdev->flags & RADEON_IS_PCI) |
| 1278 | r100_pci_gart_fini(rdev); |
| 1279 | radeon_irq_kms_fini(rdev); |
| 1280 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1281 | radeon_bo_fini(rdev); |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1282 | radeon_atombios_fini(rdev); |
| 1283 | kfree(rdev->bios); |
| 1284 | rdev->bios = NULL; |
| 1285 | } |
| 1286 | |
| 1287 | int r300_init(struct radeon_device *rdev) |
| 1288 | { |
| 1289 | int r; |
| 1290 | |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1291 | /* Disable VGA */ |
| 1292 | r100_vga_render_disable(rdev); |
| 1293 | /* Initialize scratch registers */ |
| 1294 | radeon_scratch_init(rdev); |
| 1295 | /* Initialize surface registers */ |
| 1296 | radeon_surface_init(rdev); |
| 1297 | /* TODO: disable VGA need to use VGA request */ |
| 1298 | /* BIOS*/ |
| 1299 | if (!radeon_get_bios(rdev)) { |
| 1300 | if (ASIC_IS_AVIVO(rdev)) |
| 1301 | return -EINVAL; |
| 1302 | } |
| 1303 | if (rdev->is_atom_bios) { |
| 1304 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
| 1305 | return -EINVAL; |
| 1306 | } else { |
| 1307 | r = radeon_combios_init(rdev); |
| 1308 | if (r) |
| 1309 | return r; |
| 1310 | } |
| 1311 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| 1312 | if (radeon_gpu_reset(rdev)) { |
| 1313 | dev_warn(rdev->dev, |
| 1314 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 1315 | RREG32(R_000E40_RBBM_STATUS), |
| 1316 | RREG32(R_0007C0_CP_STAT)); |
| 1317 | } |
| 1318 | /* check if cards are posted or not */ |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1319 | if (radeon_boot_test_post_card(rdev) == false) |
| 1320 | return -EINVAL; |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1321 | /* Set asic errata */ |
| 1322 | r300_errata(rdev); |
| 1323 | /* Initialize clocks */ |
| 1324 | radeon_get_clock_info(rdev->ddev); |
| 1325 | /* Get vram informations */ |
| 1326 | r300_vram_info(rdev); |
| 1327 | /* Initialize memory controller (also test AGP) */ |
| 1328 | r = r420_mc_init(rdev); |
| 1329 | if (r) |
| 1330 | return r; |
| 1331 | /* Fence driver */ |
| 1332 | r = radeon_fence_driver_init(rdev); |
| 1333 | if (r) |
| 1334 | return r; |
| 1335 | r = radeon_irq_kms_init(rdev); |
| 1336 | if (r) |
| 1337 | return r; |
| 1338 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1339 | r = radeon_bo_init(rdev); |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 1340 | if (r) |
| 1341 | return r; |
| 1342 | if (rdev->flags & RADEON_IS_PCIE) { |
| 1343 | r = rv370_pcie_gart_init(rdev); |
| 1344 | if (r) |
| 1345 | return r; |
| 1346 | } |
| 1347 | if (rdev->flags & RADEON_IS_PCI) { |
| 1348 | r = r100_pci_gart_init(rdev); |
| 1349 | if (r) |
| 1350 | return r; |
| 1351 | } |
| 1352 | r300_set_reg_safe(rdev); |
| 1353 | rdev->accel_working = true; |
| 1354 | r = r300_startup(rdev); |
| 1355 | if (r) { |
| 1356 | /* Somethings want wront with the accel init stop accel */ |
| 1357 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| 1358 | r300_suspend(rdev); |
| 1359 | r100_cp_fini(rdev); |
| 1360 | r100_wb_fini(rdev); |
| 1361 | r100_ib_fini(rdev); |
| 1362 | if (rdev->flags & RADEON_IS_PCIE) |
| 1363 | rv370_pcie_gart_fini(rdev); |
| 1364 | if (rdev->flags & RADEON_IS_PCI) |
| 1365 | r100_pci_gart_fini(rdev); |
| 1366 | radeon_irq_kms_fini(rdev); |
| 1367 | rdev->accel_working = false; |
| 1368 | } |
| 1369 | return 0; |
| 1370 | } |