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gerrit-public.fairphone.software / kernel / msm-4.9 / 93340a22943f3169de7d359ea14cd618114da6f6 / . / arch / arm / mach-omap2 / clock34xx_data.c
blob: 94f603b16c5ef7059ac93b1894968faf071c5e73 [file] [log] [blame]
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1/*
2 * OMAP3 clock data
3 *
Paul Walmsley93340a22010-02-22 22:09:12 -0700[diff] [blame^]4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]19#include <linux/kernel.h>
20#include <linux/clk.h>
Paul Walmsley93340a22010-02-22 22:09:12 -0700[diff] [blame^]21#include <linux/list.h>
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h>
25
26#include "clock.h"
27#include "clock34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30#include "prm.h"
31#include "prm-regbits-34xx.h"
32
33/*
34 * clocks
35 */
36
37#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
38
39/* Maximum DPLL multiplier, divider values for OMAP3 */
Paul Walmsley93340a22010-02-22 22:09:12 -0700[diff] [blame^]40#define OMAP3_MAX_DPLL_MULT 2047
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]41#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]42#define OMAP3_MAX_DPLL_DIV 128
43
44/*
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
50 */
51
52/* Forward declarations for DPLL bypass clocks */
53static struct clk dpll1_fck;
54static struct clk dpll2_fck;
55
56/* PRM CLOCKS */
57
58/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
59static struct clk omap_32k_fck = {
60 .name = "omap_32k_fck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .flags = RATE_FIXED,
64};
65
66static struct clk secure_32k_fck = {
67 .name = "secure_32k_fck",
68 .ops = &clkops_null,
69 .rate = 32768,
70 .flags = RATE_FIXED,
71};
72
73/* Virtual source clocks for osc_sys_ck */
74static struct clk virt_12m_ck = {
75 .name = "virt_12m_ck",
76 .ops = &clkops_null,
77 .rate = 12000000,
78 .flags = RATE_FIXED,
79};
80
81static struct clk virt_13m_ck = {
82 .name = "virt_13m_ck",
83 .ops = &clkops_null,
84 .rate = 13000000,
85 .flags = RATE_FIXED,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92 .flags = RATE_FIXED,
93};
94
95static struct clk virt_19_2m_ck = {
96 .name = "virt_19_2m_ck",
97 .ops = &clkops_null,
98 .rate = 19200000,
99 .flags = RATE_FIXED,
100};
101
102static struct clk virt_26m_ck = {
103 .name = "virt_26m_ck",
104 .ops = &clkops_null,
105 .rate = 26000000,
106 .flags = RATE_FIXED,
107};
108
109static struct clk virt_38_4m_ck = {
110 .name = "virt_38_4m_ck",
111 .ops = &clkops_null,
112 .rate = 38400000,
113 .flags = RATE_FIXED,
114};
115
116static const struct clksel_rate osc_sys_12m_rates[] = {
117 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
118 { .div = 0 }
119};
120
121static const struct clksel_rate osc_sys_13m_rates[] = {
122 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
123 { .div = 0 }
124};
125
126static const struct clksel_rate osc_sys_16_8m_rates[] = {
127 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
128 { .div = 0 }
129};
130
131static const struct clksel_rate osc_sys_19_2m_rates[] = {
132 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
133 { .div = 0 }
134};
135
136static const struct clksel_rate osc_sys_26m_rates[] = {
137 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
138 { .div = 0 }
139};
140
141static const struct clksel_rate osc_sys_38_4m_rates[] = {
142 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
143 { .div = 0 }
144};
145
146static const struct clksel osc_sys_clksel[] = {
147 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
148 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
149 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
150 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
151 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
152 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
153 { .parent = NULL },
154};
155
156/* Oscillator clock */
157/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
158static struct clk osc_sys_ck = {
159 .name = "osc_sys_ck",
160 .ops = &clkops_null,
161 .init = &omap2_init_clksel_parent,
162 .clksel_reg = OMAP3430_PRM_CLKSEL,
163 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
164 .clksel = osc_sys_clksel,
165 /* REVISIT: deal with autoextclkmode? */
166 .flags = RATE_FIXED,
167 .recalc = &omap2_clksel_recalc,
168};
169
170static const struct clksel_rate div2_rates[] = {
171 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
172 { .div = 2, .val = 2, .flags = RATE_IN_343X },
173 { .div = 0 }
174};
175
176static const struct clksel sys_clksel[] = {
177 { .parent = &osc_sys_ck, .rates = div2_rates },
178 { .parent = NULL }
179};
180
181/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
182/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
183static struct clk sys_ck = {
184 .name = "sys_ck",
185 .ops = &clkops_null,
186 .parent = &osc_sys_ck,
187 .init = &omap2_init_clksel_parent,
188 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
189 .clksel_mask = OMAP_SYSCLKDIV_MASK,
190 .clksel = sys_clksel,
191 .recalc = &omap2_clksel_recalc,
192};
193
194static struct clk sys_altclk = {
195 .name = "sys_altclk",
196 .ops = &clkops_null,
197};
198
199/* Optional external clock input for some McBSPs */
200static struct clk mcbsp_clks = {
201 .name = "mcbsp_clks",
202 .ops = &clkops_null,
203};
204
205/* PRM EXTERNAL CLOCK OUTPUT */
206
207static struct clk sys_clkout1 = {
208 .name = "sys_clkout1",
209 .ops = &clkops_omap2_dflt,
210 .parent = &osc_sys_ck,
211 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
212 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
213 .recalc = &followparent_recalc,
214};
215
216/* DPLLS */
217
218/* CM CLOCKS */
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]240static const struct clksel_rate div32_dpll4_rates_3630[] = {
241 { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
242 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
243 { .div = 3, .val = 3, .flags = RATE_IN_36XX },
244 { .div = 4, .val = 4, .flags = RATE_IN_36XX },
245 { .div = 5, .val = 5, .flags = RATE_IN_36XX },
246 { .div = 6, .val = 6, .flags = RATE_IN_36XX },
247 { .div = 7, .val = 7, .flags = RATE_IN_36XX },
248 { .div = 8, .val = 8, .flags = RATE_IN_36XX },
249 { .div = 9, .val = 9, .flags = RATE_IN_36XX },
250 { .div = 10, .val = 10, .flags = RATE_IN_36XX },
251 { .div = 11, .val = 11, .flags = RATE_IN_36XX },
252 { .div = 12, .val = 12, .flags = RATE_IN_36XX },
253 { .div = 13, .val = 13, .flags = RATE_IN_36XX },
254 { .div = 14, .val = 14, .flags = RATE_IN_36XX },
255 { .div = 15, .val = 15, .flags = RATE_IN_36XX },
256 { .div = 16, .val = 16, .flags = RATE_IN_36XX },
257 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
258 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
259 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
260 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
261 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
262 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
263 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
264 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
265 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
266 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
267 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
268 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
269 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
270 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
271 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
272 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
273 { .div = 0 }
274};
275
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]276/* DPLL1 */
277/* MPU clock source */
278/* Type: DPLL */
279static struct dpll_data dpll1_dd = {
280 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
281 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
282 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
283 .clk_bypass = &dpll1_fck,
284 .clk_ref = &sys_ck,
285 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
286 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
287 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
288 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
289 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
290 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
291 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
292 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
293 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
294 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
295 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
296 .max_multiplier = OMAP3_MAX_DPLL_MULT,
297 .min_divider = 1,
298 .max_divider = OMAP3_MAX_DPLL_DIV,
299 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
300};
301
302static struct clk dpll1_ck = {
303 .name = "dpll1_ck",
304 .ops = &clkops_null,
305 .parent = &sys_ck,
306 .dpll_data = &dpll1_dd,
307 .round_rate = &omap2_dpll_round_rate,
308 .set_rate = &omap3_noncore_dpll_set_rate,
309 .clkdm_name = "dpll1_clkdm",
310 .recalc = &omap3_dpll_recalc,
311};
312
313/*
314 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
315 * DPLL isn't bypassed.
316 */
317static struct clk dpll1_x2_ck = {
318 .name = "dpll1_x2_ck",
319 .ops = &clkops_null,
320 .parent = &dpll1_ck,
321 .clkdm_name = "dpll1_clkdm",
322 .recalc = &omap3_clkoutx2_recalc,
323};
324
325/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
326static const struct clksel div16_dpll1_x2m2_clksel[] = {
327 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
328 { .parent = NULL }
329};
330
331/*
332 * Does not exist in the TRM - needed to separate the M2 divider from
333 * bypass selection in mpu_ck
334 */
335static struct clk dpll1_x2m2_ck = {
336 .name = "dpll1_x2m2_ck",
337 .ops = &clkops_null,
338 .parent = &dpll1_x2_ck,
339 .init = &omap2_init_clksel_parent,
340 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
341 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
342 .clksel = div16_dpll1_x2m2_clksel,
343 .clkdm_name = "dpll1_clkdm",
344 .recalc = &omap2_clksel_recalc,
345};
346
347/* DPLL2 */
348/* IVA2 clock source */
349/* Type: DPLL */
350
351static struct dpll_data dpll2_dd = {
352 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
353 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
354 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
355 .clk_bypass = &dpll2_fck,
356 .clk_ref = &sys_ck,
357 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
358 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
359 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
360 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
361 (1 << DPLL_LOW_POWER_BYPASS),
362 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
363 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
364 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
365 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
366 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
367 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
368 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
369 .max_multiplier = OMAP3_MAX_DPLL_MULT,
370 .min_divider = 1,
371 .max_divider = OMAP3_MAX_DPLL_DIV,
372 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
373};
374
375static struct clk dpll2_ck = {
376 .name = "dpll2_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]377 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]378 .parent = &sys_ck,
379 .dpll_data = &dpll2_dd,
380 .round_rate = &omap2_dpll_round_rate,
381 .set_rate = &omap3_noncore_dpll_set_rate,
382 .clkdm_name = "dpll2_clkdm",
383 .recalc = &omap3_dpll_recalc,
384};
385
386static const struct clksel div16_dpll2_m2x2_clksel[] = {
387 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
388 { .parent = NULL }
389};
390
391/*
392 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
393 * or CLKOUTX2. CLKOUT seems most plausible.
394 */
395static struct clk dpll2_m2_ck = {
396 .name = "dpll2_m2_ck",
397 .ops = &clkops_null,
398 .parent = &dpll2_ck,
399 .init = &omap2_init_clksel_parent,
400 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
401 OMAP3430_CM_CLKSEL2_PLL),
402 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
403 .clksel = div16_dpll2_m2x2_clksel,
404 .clkdm_name = "dpll2_clkdm",
405 .recalc = &omap2_clksel_recalc,
406};
407
408/*
409 * DPLL3
410 * Source clock for all interfaces and for some device fclks
411 * REVISIT: Also supports fast relock bypass - not included below
412 */
413static struct dpll_data dpll3_dd = {
414 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
415 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
416 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
417 .clk_bypass = &sys_ck,
418 .clk_ref = &sys_ck,
419 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
420 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
421 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
422 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
423 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
424 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
425 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
426 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
427 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
428 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
429 .max_multiplier = OMAP3_MAX_DPLL_MULT,
430 .min_divider = 1,
431 .max_divider = OMAP3_MAX_DPLL_DIV,
432 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
433};
434
435static struct clk dpll3_ck = {
436 .name = "dpll3_ck",
437 .ops = &clkops_null,
438 .parent = &sys_ck,
439 .dpll_data = &dpll3_dd,
440 .round_rate = &omap2_dpll_round_rate,
441 .clkdm_name = "dpll3_clkdm",
442 .recalc = &omap3_dpll_recalc,
443};
444
445/*
446 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
447 * DPLL isn't bypassed
448 */
449static struct clk dpll3_x2_ck = {
450 .name = "dpll3_x2_ck",
451 .ops = &clkops_null,
452 .parent = &dpll3_ck,
453 .clkdm_name = "dpll3_clkdm",
454 .recalc = &omap3_clkoutx2_recalc,
455};
456
457static const struct clksel_rate div31_dpll3_rates[] = {
458 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
459 { .div = 2, .val = 2, .flags = RATE_IN_343X },
460 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
461 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
462 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
463 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
464 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
465 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
466 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
467 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
468 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
469 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
470 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
471 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
472 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
473 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
474 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
475 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
476 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
477 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
478 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
479 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
480 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
481 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
482 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
483 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
484 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
485 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
486 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
487 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
488 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
489 { .div = 0 },
490};
491
492static const struct clksel div31_dpll3m2_clksel[] = {
493 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
494 { .parent = NULL }
495};
496
497/* DPLL3 output M2 - primary control point for CORE speed */
498static struct clk dpll3_m2_ck = {
499 .name = "dpll3_m2_ck",
500 .ops = &clkops_null,
501 .parent = &dpll3_ck,
502 .init = &omap2_init_clksel_parent,
503 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
504 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
505 .clksel = div31_dpll3m2_clksel,
506 .clkdm_name = "dpll3_clkdm",
507 .round_rate = &omap2_clksel_round_rate,
508 .set_rate = &omap3_core_dpll_m2_set_rate,
509 .recalc = &omap2_clksel_recalc,
510};
511
512static struct clk core_ck = {
513 .name = "core_ck",
514 .ops = &clkops_null,
515 .parent = &dpll3_m2_ck,
516 .recalc = &followparent_recalc,
517};
518
519static struct clk dpll3_m2x2_ck = {
520 .name = "dpll3_m2x2_ck",
521 .ops = &clkops_null,
522 .parent = &dpll3_m2_ck,
523 .clkdm_name = "dpll3_clkdm",
524 .recalc = &omap3_clkoutx2_recalc,
525};
526
527/* The PWRDN bit is apparently only available on 3430ES2 and above */
528static const struct clksel div16_dpll3_clksel[] = {
529 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
530 { .parent = NULL }
531};
532
533/* This virtual clock is the source for dpll3_m3x2_ck */
534static struct clk dpll3_m3_ck = {
535 .name = "dpll3_m3_ck",
536 .ops = &clkops_null,
537 .parent = &dpll3_ck,
538 .init = &omap2_init_clksel_parent,
539 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
540 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
541 .clksel = div16_dpll3_clksel,
542 .clkdm_name = "dpll3_clkdm",
543 .recalc = &omap2_clksel_recalc,
544};
545
546/* The PWRDN bit is apparently only available on 3430ES2 and above */
547static struct clk dpll3_m3x2_ck = {
548 .name = "dpll3_m3x2_ck",
549 .ops = &clkops_omap2_dflt_wait,
550 .parent = &dpll3_m3_ck,
551 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
552 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
553 .flags = INVERT_ENABLE,
554 .clkdm_name = "dpll3_clkdm",
555 .recalc = &omap3_clkoutx2_recalc,
556};
557
558static struct clk emu_core_alwon_ck = {
559 .name = "emu_core_alwon_ck",
560 .ops = &clkops_null,
561 .parent = &dpll3_m3x2_ck,
562 .clkdm_name = "dpll3_clkdm",
563 .recalc = &followparent_recalc,
564};
565
566/* DPLL4 */
567/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
568/* Type: DPLL */
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]569static struct dpll_data dpll4_dd;
570static struct dpll_data dpll4_dd_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]571 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
572 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
573 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
574 .clk_bypass = &sys_ck,
575 .clk_ref = &sys_ck,
576 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
577 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
578 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
579 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
580 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
581 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
582 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
583 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
584 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
585 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
586 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
587 .max_multiplier = OMAP3_MAX_DPLL_MULT,
588 .min_divider = 1,
589 .max_divider = OMAP3_MAX_DPLL_DIV,
590 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
591};
592
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]593static struct dpll_data dpll4_dd_3630 __initdata = {
594 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
595 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
596 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
597 .clk_bypass = &sys_ck,
598 .clk_ref = &sys_ck,
599 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
600 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
601 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
602 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
603 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
604 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
605 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
606 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
607 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
608 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
609 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
610 .min_divider = 1,
611 .max_divider = OMAP3_MAX_DPLL_DIV,
612 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
613 .flags = DPLL_J_TYPE
614};
615
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]616static struct clk dpll4_ck = {
617 .name = "dpll4_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]618 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]619 .parent = &sys_ck,
620 .dpll_data = &dpll4_dd,
621 .round_rate = &omap2_dpll_round_rate,
622 .set_rate = &omap3_dpll4_set_rate,
623 .clkdm_name = "dpll4_clkdm",
624 .recalc = &omap3_dpll_recalc,
625};
626
627/*
628 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
629 * DPLL isn't bypassed --
630 * XXX does this serve any downstream clocks?
631 */
632static struct clk dpll4_x2_ck = {
633 .name = "dpll4_x2_ck",
634 .ops = &clkops_null,
635 .parent = &dpll4_ck,
636 .clkdm_name = "dpll4_clkdm",
637 .recalc = &omap3_clkoutx2_recalc,
638};
639
640static const struct clksel div16_dpll4_clksel[] = {
641 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
642 { .parent = NULL }
643};
644
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]645static const struct clksel div32_dpll4_clksel[] = {
646 { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
647 { .parent = NULL }
648};
649
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]650/* This virtual clock is the source for dpll4_m2x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]651static struct clk dpll4_m2_ck;
652
653static struct clk dpll4_m2_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]654 .name = "dpll4_m2_ck",
655 .ops = &clkops_null,
656 .parent = &dpll4_ck,
657 .init = &omap2_init_clksel_parent,
658 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
659 .clksel_mask = OMAP3430_DIV_96M_MASK,
660 .clksel = div16_dpll4_clksel,
661 .clkdm_name = "dpll4_clkdm",
662 .recalc = &omap2_clksel_recalc,
663};
664
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]665static struct clk dpll4_m2_ck_3630 __initdata = {
666 .name = "dpll4_m2_ck",
667 .ops = &clkops_null,
668 .parent = &dpll4_ck,
669 .init = &omap2_init_clksel_parent,
670 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
671 .clksel_mask = OMAP3630_DIV_96M_MASK,
672 .clksel = div32_dpll4_clksel,
673 .clkdm_name = "dpll4_clkdm",
674 .recalc = &omap2_clksel_recalc,
675};
676
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]677/* The PWRDN bit is apparently only available on 3430ES2 and above */
678static struct clk dpll4_m2x2_ck = {
679 .name = "dpll4_m2x2_ck",
680 .ops = &clkops_omap2_dflt_wait,
681 .parent = &dpll4_m2_ck,
682 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
683 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
684 .flags = INVERT_ENABLE,
685 .clkdm_name = "dpll4_clkdm",
686 .recalc = &omap3_clkoutx2_recalc,
687};
688
689/*
690 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
691 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
692 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
693 * CM_96K_(F)CLK.
694 */
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]695
696/* Adding 192MHz Clock node needed by SGX */
697static struct clk omap_192m_alwon_fck = {
698 .name = "omap_192m_alwon_fck",
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]699 .ops = &clkops_null,
700 .parent = &dpll4_m2x2_ck,
701 .recalc = &followparent_recalc,
702};
703
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]704static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
705 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
706 { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
707 { .div = 0 }
708};
709
710static const struct clksel omap_96m_alwon_fck_clksel[] = {
711 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
712 { .parent = NULL }
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]713};
714
715static const struct clksel_rate omap_96m_dpll_rates[] = {
716 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
717 { .div = 0 }
718};
719
720static const struct clksel_rate omap_96m_sys_rates[] = {
721 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
722 { .div = 0 }
723};
724
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]725static struct clk omap_96m_alwon_fck = {
726 .name = "omap_96m_alwon_fck",
727 .ops = &clkops_null,
728 .parent = &dpll4_m2x2_ck,
729 .recalc = &followparent_recalc,
730};
731
732static struct clk omap_96m_alwon_fck_3630 = {
733 .name = "omap_96m_alwon_fck",
734 .parent = &omap_192m_alwon_fck,
735 .init = &omap2_init_clksel_parent,
736 .ops = &clkops_null,
737 .recalc = &omap2_clksel_recalc,
738 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
739 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
740 .clksel = omap_96m_alwon_fck_clksel
741};
742
743static struct clk cm_96m_fck = {
744 .name = "cm_96m_fck",
745 .ops = &clkops_null,
746 .parent = &omap_96m_alwon_fck,
747 .recalc = &followparent_recalc,
748};
749
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]750static const struct clksel omap_96m_fck_clksel[] = {
751 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
752 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
753 { .parent = NULL }
754};
755
756static struct clk omap_96m_fck = {
757 .name = "omap_96m_fck",
758 .ops = &clkops_null,
759 .parent = &sys_ck,
760 .init = &omap2_init_clksel_parent,
761 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
762 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
763 .clksel = omap_96m_fck_clksel,
764 .recalc = &omap2_clksel_recalc,
765};
766
767/* This virtual clock is the source for dpll4_m3x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]768static struct clk dpll4_m3_ck;
769
770static struct clk dpll4_m3_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]771 .name = "dpll4_m3_ck",
772 .ops = &clkops_null,
773 .parent = &dpll4_ck,
774 .init = &omap2_init_clksel_parent,
775 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
776 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
777 .clksel = div16_dpll4_clksel,
778 .clkdm_name = "dpll4_clkdm",
779 .recalc = &omap2_clksel_recalc,
780};
781
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]782static struct clk dpll4_m3_ck_3630 __initdata = {
783 .name = "dpll4_m3_ck",
784 .ops = &clkops_null,
785 .parent = &dpll4_ck,
786 .init = &omap2_init_clksel_parent,
787 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
788 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
789 .clksel = div32_dpll4_clksel,
790 .clkdm_name = "dpll4_clkdm",
791 .recalc = &omap2_clksel_recalc,
792};
793
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]794/* The PWRDN bit is apparently only available on 3430ES2 and above */
795static struct clk dpll4_m3x2_ck = {
796 .name = "dpll4_m3x2_ck",
797 .ops = &clkops_omap2_dflt_wait,
798 .parent = &dpll4_m3_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]799 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
800 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
801 .flags = INVERT_ENABLE,
802 .clkdm_name = "dpll4_clkdm",
803 .recalc = &omap3_clkoutx2_recalc,
804};
805
806static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
807 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
808 { .div = 0 }
809};
810
811static const struct clksel_rate omap_54m_alt_rates[] = {
812 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
813 { .div = 0 }
814};
815
816static const struct clksel omap_54m_clksel[] = {
817 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
818 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
819 { .parent = NULL }
820};
821
822static struct clk omap_54m_fck = {
823 .name = "omap_54m_fck",
824 .ops = &clkops_null,
825 .init = &omap2_init_clksel_parent,
826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
827 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
828 .clksel = omap_54m_clksel,
829 .recalc = &omap2_clksel_recalc,
830};
831
832static const struct clksel_rate omap_48m_cm96m_rates[] = {
833 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
834 { .div = 0 }
835};
836
837static const struct clksel_rate omap_48m_alt_rates[] = {
838 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
839 { .div = 0 }
840};
841
842static const struct clksel omap_48m_clksel[] = {
843 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
844 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
845 { .parent = NULL }
846};
847
848static struct clk omap_48m_fck = {
849 .name = "omap_48m_fck",
850 .ops = &clkops_null,
851 .init = &omap2_init_clksel_parent,
852 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
853 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
854 .clksel = omap_48m_clksel,
855 .recalc = &omap2_clksel_recalc,
856};
857
858static struct clk omap_12m_fck = {
859 .name = "omap_12m_fck",
860 .ops = &clkops_null,
861 .parent = &omap_48m_fck,
862 .fixed_div = 4,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]863 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]864};
865
866/* This virstual clock is the source for dpll4_m4x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]867static struct clk dpll4_m4_ck;
868
869static struct clk dpll4_m4_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]870 .name = "dpll4_m4_ck",
871 .ops = &clkops_null,
872 .parent = &dpll4_ck,
873 .init = &omap2_init_clksel_parent,
874 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
875 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
876 .clksel = div16_dpll4_clksel,
877 .clkdm_name = "dpll4_clkdm",
878 .recalc = &omap2_clksel_recalc,
879 .set_rate = &omap2_clksel_set_rate,
880 .round_rate = &omap2_clksel_round_rate,
881};
882
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]883static struct clk dpll4_m4_ck_3630 __initdata = {
884 .name = "dpll4_m4_ck",
885 .ops = &clkops_null,
886 .parent = &dpll4_ck,
887 .init = &omap2_init_clksel_parent,
888 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
889 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
890 .clksel = div32_dpll4_clksel,
891 .clkdm_name = "dpll4_clkdm",
892 .recalc = &omap2_clksel_recalc,
893 .set_rate = &omap2_clksel_set_rate,
894 .round_rate = &omap2_clksel_round_rate,
895};
896
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]897/* The PWRDN bit is apparently only available on 3430ES2 and above */
898static struct clk dpll4_m4x2_ck = {
899 .name = "dpll4_m4x2_ck",
900 .ops = &clkops_omap2_dflt_wait,
901 .parent = &dpll4_m4_ck,
902 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
903 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
904 .flags = INVERT_ENABLE,
905 .clkdm_name = "dpll4_clkdm",
906 .recalc = &omap3_clkoutx2_recalc,
907};
908
909/* This virtual clock is the source for dpll4_m5x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]910static struct clk dpll4_m5_ck;
911
912static struct clk dpll4_m5_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]913 .name = "dpll4_m5_ck",
914 .ops = &clkops_null,
915 .parent = &dpll4_ck,
916 .init = &omap2_init_clksel_parent,
917 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
918 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
919 .clksel = div16_dpll4_clksel,
920 .clkdm_name = "dpll4_clkdm",
Tuukka Toivonen3e3ee152010-01-08 15:23:08 -0700[diff] [blame]921 .set_rate = &omap2_clksel_set_rate,
922 .round_rate = &omap2_clksel_round_rate,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]923 .recalc = &omap2_clksel_recalc,
924};
925
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]926static struct clk dpll4_m5_ck_3630 __initdata = {
927 .name = "dpll4_m5_ck",
928 .ops = &clkops_null,
929 .parent = &dpll4_ck,
930 .init = &omap2_init_clksel_parent,
931 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
932 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
933 .clksel = div32_dpll4_clksel,
934 .clkdm_name = "dpll4_clkdm",
935 .recalc = &omap2_clksel_recalc,
936};
937
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]938/* The PWRDN bit is apparently only available on 3430ES2 and above */
939static struct clk dpll4_m5x2_ck = {
940 .name = "dpll4_m5x2_ck",
941 .ops = &clkops_omap2_dflt_wait,
942 .parent = &dpll4_m5_ck,
943 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
944 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
945 .flags = INVERT_ENABLE,
946 .clkdm_name = "dpll4_clkdm",
947 .recalc = &omap3_clkoutx2_recalc,
948};
949
950/* This virtual clock is the source for dpll4_m6x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]951static struct clk dpll4_m6_ck;
952
953static struct clk dpll4_m6_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]954 .name = "dpll4_m6_ck",
955 .ops = &clkops_null,
956 .parent = &dpll4_ck,
957 .init = &omap2_init_clksel_parent,
958 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
959 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
960 .clksel = div16_dpll4_clksel,
961 .clkdm_name = "dpll4_clkdm",
962 .recalc = &omap2_clksel_recalc,
963};
964
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]965static struct clk dpll4_m6_ck_3630 __initdata = {
966 .name = "dpll4_m6_ck",
967 .ops = &clkops_null,
968 .parent = &dpll4_ck,
969 .init = &omap2_init_clksel_parent,
970 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
971 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
972 .clksel = div32_dpll4_clksel,
973 .clkdm_name = "dpll4_clkdm",
974 .recalc = &omap2_clksel_recalc,
975};
976
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]977/* The PWRDN bit is apparently only available on 3430ES2 and above */
978static struct clk dpll4_m6x2_ck = {
979 .name = "dpll4_m6x2_ck",
980 .ops = &clkops_omap2_dflt_wait,
981 .parent = &dpll4_m6_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]982 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
983 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
984 .flags = INVERT_ENABLE,
985 .clkdm_name = "dpll4_clkdm",
986 .recalc = &omap3_clkoutx2_recalc,
987};
988
989static struct clk emu_per_alwon_ck = {
990 .name = "emu_per_alwon_ck",
991 .ops = &clkops_null,
992 .parent = &dpll4_m6x2_ck,
993 .clkdm_name = "dpll4_clkdm",
994 .recalc = &followparent_recalc,
995};
996
997/* DPLL5 */
998/* Supplies 120MHz clock, USIM source clock */
999/* Type: DPLL */
1000/* 3430ES2 only */
1001static struct dpll_data dpll5_dd = {
1002 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
1003 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
1004 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
1005 .clk_bypass = &sys_ck,
1006 .clk_ref = &sys_ck,
1007 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
1008 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
1009 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
1010 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
1011 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
1012 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
1013 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
1014 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
1015 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
1016 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1017 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1018 .max_multiplier = OMAP3_MAX_DPLL_MULT,
1019 .min_divider = 1,
1020 .max_divider = OMAP3_MAX_DPLL_DIV,
1021 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
1022};
1023
1024static struct clk dpll5_ck = {
1025 .name = "dpll5_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]1026 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1027 .parent = &sys_ck,
1028 .dpll_data = &dpll5_dd,
1029 .round_rate = &omap2_dpll_round_rate,
1030 .set_rate = &omap3_noncore_dpll_set_rate,
1031 .clkdm_name = "dpll5_clkdm",
1032 .recalc = &omap3_dpll_recalc,
1033};
1034
1035static const struct clksel div16_dpll5_clksel[] = {
1036 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
1037 { .parent = NULL }
1038};
1039
1040static struct clk dpll5_m2_ck = {
1041 .name = "dpll5_m2_ck",
1042 .ops = &clkops_null,
1043 .parent = &dpll5_ck,
1044 .init = &omap2_init_clksel_parent,
1045 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1046 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
1047 .clksel = div16_dpll5_clksel,
1048 .clkdm_name = "dpll5_clkdm",
1049 .recalc = &omap2_clksel_recalc,
1050};
1051
1052/* CM EXTERNAL CLOCK OUTPUTS */
1053
1054static const struct clksel_rate clkout2_src_core_rates[] = {
1055 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1056 { .div = 0 }
1057};
1058
1059static const struct clksel_rate clkout2_src_sys_rates[] = {
1060 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1061 { .div = 0 }
1062};
1063
1064static const struct clksel_rate clkout2_src_96m_rates[] = {
1065 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1066 { .div = 0 }
1067};
1068
1069static const struct clksel_rate clkout2_src_54m_rates[] = {
1070 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1071 { .div = 0 }
1072};
1073
1074static const struct clksel clkout2_src_clksel[] = {
1075 { .parent = &core_ck, .rates = clkout2_src_core_rates },
1076 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
1077 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
1078 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
1079 { .parent = NULL }
1080};
1081
1082static struct clk clkout2_src_ck = {
1083 .name = "clkout2_src_ck",
1084 .ops = &clkops_omap2_dflt,
1085 .init = &omap2_init_clksel_parent,
1086 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1087 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1088 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1089 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1090 .clksel = clkout2_src_clksel,
1091 .clkdm_name = "core_clkdm",
1092 .recalc = &omap2_clksel_recalc,
1093};
1094
1095static const struct clksel_rate sys_clkout2_rates[] = {
1096 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1097 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1098 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1099 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1100 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1101 { .div = 0 },
1102};
1103
1104static const struct clksel sys_clkout2_clksel[] = {
1105 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1106 { .parent = NULL },
1107};
1108
1109static struct clk sys_clkout2 = {
1110 .name = "sys_clkout2",
1111 .ops = &clkops_null,
1112 .init = &omap2_init_clksel_parent,
1113 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1114 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1115 .clksel = sys_clkout2_clksel,
1116 .recalc = &omap2_clksel_recalc,
1117};
1118
1119/* CM OUTPUT CLOCKS */
1120
1121static struct clk corex2_fck = {
1122 .name = "corex2_fck",
1123 .ops = &clkops_null,
1124 .parent = &dpll3_m2x2_ck,
1125 .recalc = &followparent_recalc,
1126};
1127
1128/* DPLL power domain clock controls */
1129
1130static const struct clksel_rate div4_rates[] = {
1131 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1132 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1133 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1134 { .div = 0 }
1135};
1136
1137static const struct clksel div4_core_clksel[] = {
1138 { .parent = &core_ck, .rates = div4_rates },
1139 { .parent = NULL }
1140};
1141
1142/*
1143 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1144 * may be inconsistent here?
1145 */
1146static struct clk dpll1_fck = {
1147 .name = "dpll1_fck",
1148 .ops = &clkops_null,
1149 .parent = &core_ck,
1150 .init = &omap2_init_clksel_parent,
1151 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1152 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1153 .clksel = div4_core_clksel,
1154 .recalc = &omap2_clksel_recalc,
1155};
1156
1157static struct clk mpu_ck = {
1158 .name = "mpu_ck",
1159 .ops = &clkops_null,
1160 .parent = &dpll1_x2m2_ck,
1161 .clkdm_name = "mpu_clkdm",
1162 .recalc = &followparent_recalc,
1163};
1164
1165/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1166static const struct clksel_rate arm_fck_rates[] = {
1167 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1168 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1169 { .div = 0 },
1170};
1171
1172static const struct clksel arm_fck_clksel[] = {
1173 { .parent = &mpu_ck, .rates = arm_fck_rates },
1174 { .parent = NULL }
1175};
1176
1177static struct clk arm_fck = {
1178 .name = "arm_fck",
1179 .ops = &clkops_null,
1180 .parent = &mpu_ck,
1181 .init = &omap2_init_clksel_parent,
1182 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1183 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1184 .clksel = arm_fck_clksel,
1185 .clkdm_name = "mpu_clkdm",
1186 .recalc = &omap2_clksel_recalc,
1187};
1188
1189/* XXX What about neon_clkdm ? */
1190
1191/*
1192 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1193 * although it is referenced - so this is a guess
1194 */
1195static struct clk emu_mpu_alwon_ck = {
1196 .name = "emu_mpu_alwon_ck",
1197 .ops = &clkops_null,
1198 .parent = &mpu_ck,
1199 .recalc = &followparent_recalc,
1200};
1201
1202static struct clk dpll2_fck = {
1203 .name = "dpll2_fck",
1204 .ops = &clkops_null,
1205 .parent = &core_ck,
1206 .init = &omap2_init_clksel_parent,
1207 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1208 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1209 .clksel = div4_core_clksel,
1210 .recalc = &omap2_clksel_recalc,
1211};
1212
1213static struct clk iva2_ck = {
1214 .name = "iva2_ck",
1215 .ops = &clkops_omap2_dflt_wait,
1216 .parent = &dpll2_m2_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1217 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1218 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1219 .clkdm_name = "iva2_clkdm",
1220 .recalc = &followparent_recalc,
1221};
1222
1223/* Common interface clocks */
1224
1225static const struct clksel div2_core_clksel[] = {
1226 { .parent = &core_ck, .rates = div2_rates },
1227 { .parent = NULL }
1228};
1229
1230static struct clk l3_ick = {
1231 .name = "l3_ick",
1232 .ops = &clkops_null,
1233 .parent = &core_ck,
1234 .init = &omap2_init_clksel_parent,
1235 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1236 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1237 .clksel = div2_core_clksel,
1238 .clkdm_name = "core_l3_clkdm",
1239 .recalc = &omap2_clksel_recalc,
1240};
1241
1242static const struct clksel div2_l3_clksel[] = {
1243 { .parent = &l3_ick, .rates = div2_rates },
1244 { .parent = NULL }
1245};
1246
1247static struct clk l4_ick = {
1248 .name = "l4_ick",
1249 .ops = &clkops_null,
1250 .parent = &l3_ick,
1251 .init = &omap2_init_clksel_parent,
1252 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1253 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1254 .clksel = div2_l3_clksel,
1255 .clkdm_name = "core_l4_clkdm",
1256 .recalc = &omap2_clksel_recalc,
1257
1258};
1259
1260static const struct clksel div2_l4_clksel[] = {
1261 { .parent = &l4_ick, .rates = div2_rates },
1262 { .parent = NULL }
1263};
1264
1265static struct clk rm_ick = {
1266 .name = "rm_ick",
1267 .ops = &clkops_null,
1268 .parent = &l4_ick,
1269 .init = &omap2_init_clksel_parent,
1270 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1271 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1272 .clksel = div2_l4_clksel,
1273 .recalc = &omap2_clksel_recalc,
1274};
1275
1276/* GFX power domain */
1277
1278/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1279
1280static const struct clksel gfx_l3_clksel[] = {
1281 { .parent = &l3_ick, .rates = gfx_l3_rates },
1282 { .parent = NULL }
1283};
1284
1285/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1286static struct clk gfx_l3_ck = {
1287 .name = "gfx_l3_ck",
1288 .ops = &clkops_omap2_dflt_wait,
1289 .parent = &l3_ick,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1290 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1291 .enable_bit = OMAP_EN_GFX_SHIFT,
1292 .recalc = &followparent_recalc,
1293};
1294
1295static struct clk gfx_l3_fck = {
1296 .name = "gfx_l3_fck",
1297 .ops = &clkops_null,
1298 .parent = &gfx_l3_ck,
1299 .init = &omap2_init_clksel_parent,
1300 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1301 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1302 .clksel = gfx_l3_clksel,
1303 .clkdm_name = "gfx_3430es1_clkdm",
1304 .recalc = &omap2_clksel_recalc,
1305};
1306
1307static struct clk gfx_l3_ick = {
1308 .name = "gfx_l3_ick",
1309 .ops = &clkops_null,
1310 .parent = &gfx_l3_ck,
1311 .clkdm_name = "gfx_3430es1_clkdm",
1312 .recalc = &followparent_recalc,
1313};
1314
1315static struct clk gfx_cg1_ck = {
1316 .name = "gfx_cg1_ck",
1317 .ops = &clkops_omap2_dflt_wait,
1318 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1319 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1320 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1321 .clkdm_name = "gfx_3430es1_clkdm",
1322 .recalc = &followparent_recalc,
1323};
1324
1325static struct clk gfx_cg2_ck = {
1326 .name = "gfx_cg2_ck",
1327 .ops = &clkops_omap2_dflt_wait,
1328 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1329 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1330 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1331 .clkdm_name = "gfx_3430es1_clkdm",
1332 .recalc = &followparent_recalc,
1333};
1334
1335/* SGX power domain - 3430ES2 only */
1336
1337static const struct clksel_rate sgx_core_rates[] = {
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]1338 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1339 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1340 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1341 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1342 { .div = 0 },
1343};
1344
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]1345static const struct clksel_rate sgx_192m_rates[] = {
1346 { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
1347 { .div = 0 },
1348};
1349
1350static const struct clksel_rate sgx_corex2_rates[] = {
1351 { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
1352 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1353 { .div = 0 },
1354};
1355
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1356static const struct clksel_rate sgx_96m_rates[] = {
1357 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1358 { .div = 0 },
1359};
1360
1361static const struct clksel sgx_clksel[] = {
1362 { .parent = &core_ck, .rates = sgx_core_rates },
1363 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]1364 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1365 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1366 { .parent = NULL }
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1367};
1368
1369static struct clk sgx_fck = {
1370 .name = "sgx_fck",
1371 .ops = &clkops_omap2_dflt_wait,
1372 .init = &omap2_init_clksel_parent,
1373 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1374 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1375 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1376 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1377 .clksel = sgx_clksel,
1378 .clkdm_name = "sgx_clkdm",
1379 .recalc = &omap2_clksel_recalc,
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]1380 .set_rate = &omap2_clksel_set_rate,
1381 .round_rate = &omap2_clksel_round_rate
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1382};
1383
1384static struct clk sgx_ick = {
1385 .name = "sgx_ick",
1386 .ops = &clkops_omap2_dflt_wait,
1387 .parent = &l3_ick,
1388 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1389 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1390 .clkdm_name = "sgx_clkdm",
1391 .recalc = &followparent_recalc,
1392};
1393
1394/* CORE power domain */
1395
1396static struct clk d2d_26m_fck = {
1397 .name = "d2d_26m_fck",
1398 .ops = &clkops_omap2_dflt_wait,
1399 .parent = &sys_ck,
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1402 .clkdm_name = "d2d_clkdm",
1403 .recalc = &followparent_recalc,
1404};
1405
1406static struct clk modem_fck = {
1407 .name = "modem_fck",
1408 .ops = &clkops_omap2_dflt_wait,
1409 .parent = &sys_ck,
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1412 .clkdm_name = "d2d_clkdm",
1413 .recalc = &followparent_recalc,
1414};
1415
1416static struct clk sad2d_ick = {
1417 .name = "sad2d_ick",
1418 .ops = &clkops_omap2_dflt_wait,
1419 .parent = &l3_ick,
1420 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1421 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1422 .clkdm_name = "d2d_clkdm",
1423 .recalc = &followparent_recalc,
1424};
1425
1426static struct clk mad2d_ick = {
1427 .name = "mad2d_ick",
1428 .ops = &clkops_omap2_dflt_wait,
1429 .parent = &l3_ick,
1430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1431 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1432 .clkdm_name = "d2d_clkdm",
1433 .recalc = &followparent_recalc,
1434};
1435
1436static const struct clksel omap343x_gpt_clksel[] = {
1437 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1438 { .parent = &sys_ck, .rates = gpt_sys_rates },
1439 { .parent = NULL}
1440};
1441
1442static struct clk gpt10_fck = {
1443 .name = "gpt10_fck",
1444 .ops = &clkops_omap2_dflt_wait,
1445 .parent = &sys_ck,
1446 .init = &omap2_init_clksel_parent,
1447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1449 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1450 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1451 .clksel = omap343x_gpt_clksel,
1452 .clkdm_name = "core_l4_clkdm",
1453 .recalc = &omap2_clksel_recalc,
1454};
1455
1456static struct clk gpt11_fck = {
1457 .name = "gpt11_fck",
1458 .ops = &clkops_omap2_dflt_wait,
1459 .parent = &sys_ck,
1460 .init = &omap2_init_clksel_parent,
1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1463 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1464 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1465 .clksel = omap343x_gpt_clksel,
1466 .clkdm_name = "core_l4_clkdm",
1467 .recalc = &omap2_clksel_recalc,
1468};
1469
1470static struct clk cpefuse_fck = {
1471 .name = "cpefuse_fck",
1472 .ops = &clkops_omap2_dflt,
1473 .parent = &sys_ck,
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1475 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1476 .recalc = &followparent_recalc,
1477};
1478
1479static struct clk ts_fck = {
1480 .name = "ts_fck",
1481 .ops = &clkops_omap2_dflt,
1482 .parent = &omap_32k_fck,
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1484 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk usbtll_fck = {
1489 .name = "usbtll_fck",
1490 .ops = &clkops_omap2_dflt,
1491 .parent = &dpll5_m2_ck,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1493 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1494 .recalc = &followparent_recalc,
1495};
1496
1497/* CORE 96M FCLK-derived clocks */
1498
1499static struct clk core_96m_fck = {
1500 .name = "core_96m_fck",
1501 .ops = &clkops_null,
1502 .parent = &omap_96m_fck,
1503 .clkdm_name = "core_l4_clkdm",
1504 .recalc = &followparent_recalc,
1505};
1506
1507static struct clk mmchs3_fck = {
1508 .name = "mmchs_fck",
1509 .ops = &clkops_omap2_dflt_wait,
1510 .id = 2,
1511 .parent = &core_96m_fck,
1512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1513 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1514 .clkdm_name = "core_l4_clkdm",
1515 .recalc = &followparent_recalc,
1516};
1517
1518static struct clk mmchs2_fck = {
1519 .name = "mmchs_fck",
1520 .ops = &clkops_omap2_dflt_wait,
1521 .id = 1,
1522 .parent = &core_96m_fck,
1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1525 .clkdm_name = "core_l4_clkdm",
1526 .recalc = &followparent_recalc,
1527};
1528
1529static struct clk mspro_fck = {
1530 .name = "mspro_fck",
1531 .ops = &clkops_omap2_dflt_wait,
1532 .parent = &core_96m_fck,
1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1535 .clkdm_name = "core_l4_clkdm",
1536 .recalc = &followparent_recalc,
1537};
1538
1539static struct clk mmchs1_fck = {
1540 .name = "mmchs_fck",
1541 .ops = &clkops_omap2_dflt_wait,
1542 .parent = &core_96m_fck,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1545 .clkdm_name = "core_l4_clkdm",
1546 .recalc = &followparent_recalc,
1547};
1548
1549static struct clk i2c3_fck = {
1550 .name = "i2c_fck",
1551 .ops = &clkops_omap2_dflt_wait,
1552 .id = 3,
1553 .parent = &core_96m_fck,
1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1555 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1556 .clkdm_name = "core_l4_clkdm",
1557 .recalc = &followparent_recalc,
1558};
1559
1560static struct clk i2c2_fck = {
1561 .name = "i2c_fck",
1562 .ops = &clkops_omap2_dflt_wait,
1563 .id = 2,
1564 .parent = &core_96m_fck,
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1567 .clkdm_name = "core_l4_clkdm",
1568 .recalc = &followparent_recalc,
1569};
1570
1571static struct clk i2c1_fck = {
1572 .name = "i2c_fck",
1573 .ops = &clkops_omap2_dflt_wait,
1574 .id = 1,
1575 .parent = &core_96m_fck,
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1578 .clkdm_name = "core_l4_clkdm",
1579 .recalc = &followparent_recalc,
1580};
1581
1582/*
1583 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1584 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1585 */
1586static const struct clksel_rate common_mcbsp_96m_rates[] = {
1587 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1588 { .div = 0 }
1589};
1590
1591static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1592 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1593 { .div = 0 }
1594};
1595
1596static const struct clksel mcbsp_15_clksel[] = {
1597 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1598 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1599 { .parent = NULL }
1600};
1601
1602static struct clk mcbsp5_fck = {
1603 .name = "mcbsp_fck",
1604 .ops = &clkops_omap2_dflt_wait,
1605 .id = 5,
1606 .init = &omap2_init_clksel_parent,
1607 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1608 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1609 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1610 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1611 .clksel = mcbsp_15_clksel,
1612 .clkdm_name = "core_l4_clkdm",
1613 .recalc = &omap2_clksel_recalc,
1614};
1615
1616static struct clk mcbsp1_fck = {
1617 .name = "mcbsp_fck",
1618 .ops = &clkops_omap2_dflt_wait,
1619 .id = 1,
1620 .init = &omap2_init_clksel_parent,
1621 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1622 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1623 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1624 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1625 .clksel = mcbsp_15_clksel,
1626 .clkdm_name = "core_l4_clkdm",
1627 .recalc = &omap2_clksel_recalc,
1628};
1629
1630/* CORE_48M_FCK-derived clocks */
1631
1632static struct clk core_48m_fck = {
1633 .name = "core_48m_fck",
1634 .ops = &clkops_null,
1635 .parent = &omap_48m_fck,
1636 .clkdm_name = "core_l4_clkdm",
1637 .recalc = &followparent_recalc,
1638};
1639
1640static struct clk mcspi4_fck = {
1641 .name = "mcspi_fck",
1642 .ops = &clkops_omap2_dflt_wait,
1643 .id = 4,
1644 .parent = &core_48m_fck,
1645 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1646 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1647 .recalc = &followparent_recalc,
1648};
1649
1650static struct clk mcspi3_fck = {
1651 .name = "mcspi_fck",
1652 .ops = &clkops_omap2_dflt_wait,
1653 .id = 3,
1654 .parent = &core_48m_fck,
1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1656 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1657 .recalc = &followparent_recalc,
1658};
1659
1660static struct clk mcspi2_fck = {
1661 .name = "mcspi_fck",
1662 .ops = &clkops_omap2_dflt_wait,
1663 .id = 2,
1664 .parent = &core_48m_fck,
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1667 .recalc = &followparent_recalc,
1668};
1669
1670static struct clk mcspi1_fck = {
1671 .name = "mcspi_fck",
1672 .ops = &clkops_omap2_dflt_wait,
1673 .id = 1,
1674 .parent = &core_48m_fck,
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1676 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1677 .recalc = &followparent_recalc,
1678};
1679
1680static struct clk uart2_fck = {
1681 .name = "uart2_fck",
1682 .ops = &clkops_omap2_dflt_wait,
1683 .parent = &core_48m_fck,
1684 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1685 .enable_bit = OMAP3430_EN_UART2_SHIFT,
Kevin Hilman9b5bc5f2010-01-08 15:23:06 -0700[diff] [blame]1686 .clkdm_name = "core_l4_clkdm",
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1687 .recalc = &followparent_recalc,
1688};
1689
1690static struct clk uart1_fck = {
1691 .name = "uart1_fck",
1692 .ops = &clkops_omap2_dflt_wait,
1693 .parent = &core_48m_fck,
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1695 .enable_bit = OMAP3430_EN_UART1_SHIFT,
Kevin Hilman9b5bc5f2010-01-08 15:23:06 -0700[diff] [blame]1696 .clkdm_name = "core_l4_clkdm",
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1697 .recalc = &followparent_recalc,
1698};
1699
1700static struct clk fshostusb_fck = {
1701 .name = "fshostusb_fck",
1702 .ops = &clkops_omap2_dflt_wait,
1703 .parent = &core_48m_fck,
1704 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1705 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1706 .recalc = &followparent_recalc,
1707};
1708
1709/* CORE_12M_FCK based clocks */
1710
1711static struct clk core_12m_fck = {
1712 .name = "core_12m_fck",
1713 .ops = &clkops_null,
1714 .parent = &omap_12m_fck,
1715 .clkdm_name = "core_l4_clkdm",
1716 .recalc = &followparent_recalc,
1717};
1718
1719static struct clk hdq_fck = {
1720 .name = "hdq_fck",
1721 .ops = &clkops_omap2_dflt_wait,
1722 .parent = &core_12m_fck,
1723 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1724 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1725 .recalc = &followparent_recalc,
1726};
1727
1728/* DPLL3-derived clock */
1729
1730static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1731 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1732 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1733 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1734 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1735 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1736 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1737 { .div = 0 }
1738};
1739
1740static const struct clksel ssi_ssr_clksel[] = {
1741 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1742 { .parent = NULL }
1743};
1744
1745static struct clk ssi_ssr_fck_3430es1 = {
1746 .name = "ssi_ssr_fck",
1747 .ops = &clkops_omap2_dflt,
1748 .init = &omap2_init_clksel_parent,
1749 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1750 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1751 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1752 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1753 .clksel = ssi_ssr_clksel,
1754 .clkdm_name = "core_l4_clkdm",
1755 .recalc = &omap2_clksel_recalc,
1756};
1757
1758static struct clk ssi_ssr_fck_3430es2 = {
1759 .name = "ssi_ssr_fck",
1760 .ops = &clkops_omap3430es2_ssi_wait,
1761 .init = &omap2_init_clksel_parent,
1762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1763 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1764 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1765 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1766 .clksel = ssi_ssr_clksel,
1767 .clkdm_name = "core_l4_clkdm",
1768 .recalc = &omap2_clksel_recalc,
1769};
1770
1771static struct clk ssi_sst_fck_3430es1 = {
1772 .name = "ssi_sst_fck",
1773 .ops = &clkops_null,
1774 .parent = &ssi_ssr_fck_3430es1,
1775 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]1776 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1777};
1778
1779static struct clk ssi_sst_fck_3430es2 = {
1780 .name = "ssi_sst_fck",
1781 .ops = &clkops_null,
1782 .parent = &ssi_ssr_fck_3430es2,
1783 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]1784 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1785};
1786
1787
1788
1789/* CORE_L3_ICK based clocks */
1790
1791/*
1792 * XXX must add clk_enable/clk_disable for these if standard code won't
1793 * handle it
1794 */
1795static struct clk core_l3_ick = {
1796 .name = "core_l3_ick",
1797 .ops = &clkops_null,
1798 .parent = &l3_ick,
1799 .clkdm_name = "core_l3_clkdm",
1800 .recalc = &followparent_recalc,
1801};
1802
1803static struct clk hsotgusb_ick_3430es1 = {
1804 .name = "hsotgusb_ick",
1805 .ops = &clkops_omap2_dflt,
1806 .parent = &core_l3_ick,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1809 .clkdm_name = "core_l3_clkdm",
1810 .recalc = &followparent_recalc,
1811};
1812
1813static struct clk hsotgusb_ick_3430es2 = {
1814 .name = "hsotgusb_ick",
1815 .ops = &clkops_omap3430es2_hsotgusb_wait,
1816 .parent = &core_l3_ick,
1817 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1818 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1819 .clkdm_name = "core_l3_clkdm",
1820 .recalc = &followparent_recalc,
1821};
1822
1823static struct clk sdrc_ick = {
1824 .name = "sdrc_ick",
1825 .ops = &clkops_omap2_dflt_wait,
1826 .parent = &core_l3_ick,
1827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1828 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1829 .flags = ENABLE_ON_INIT,
1830 .clkdm_name = "core_l3_clkdm",
1831 .recalc = &followparent_recalc,
1832};
1833
1834static struct clk gpmc_fck = {
1835 .name = "gpmc_fck",
1836 .ops = &clkops_null,
1837 .parent = &core_l3_ick,
1838 .flags = ENABLE_ON_INIT, /* huh? */
1839 .clkdm_name = "core_l3_clkdm",
1840 .recalc = &followparent_recalc,
1841};
1842
1843/* SECURITY_L3_ICK based clocks */
1844
1845static struct clk security_l3_ick = {
1846 .name = "security_l3_ick",
1847 .ops = &clkops_null,
1848 .parent = &l3_ick,
1849 .recalc = &followparent_recalc,
1850};
1851
1852static struct clk pka_ick = {
1853 .name = "pka_ick",
1854 .ops = &clkops_omap2_dflt_wait,
1855 .parent = &security_l3_ick,
1856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1857 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1858 .recalc = &followparent_recalc,
1859};
1860
1861/* CORE_L4_ICK based clocks */
1862
1863static struct clk core_l4_ick = {
1864 .name = "core_l4_ick",
1865 .ops = &clkops_null,
1866 .parent = &l4_ick,
1867 .clkdm_name = "core_l4_clkdm",
1868 .recalc = &followparent_recalc,
1869};
1870
1871static struct clk usbtll_ick = {
1872 .name = "usbtll_ick",
1873 .ops = &clkops_omap2_dflt_wait,
1874 .parent = &core_l4_ick,
1875 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1876 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1877 .clkdm_name = "core_l4_clkdm",
1878 .recalc = &followparent_recalc,
1879};
1880
1881static struct clk mmchs3_ick = {
1882 .name = "mmchs_ick",
1883 .ops = &clkops_omap2_dflt_wait,
1884 .id = 2,
1885 .parent = &core_l4_ick,
1886 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1888 .clkdm_name = "core_l4_clkdm",
1889 .recalc = &followparent_recalc,
1890};
1891
1892/* Intersystem Communication Registers - chassis mode only */
1893static struct clk icr_ick = {
1894 .name = "icr_ick",
1895 .ops = &clkops_omap2_dflt_wait,
1896 .parent = &core_l4_ick,
1897 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1898 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1899 .clkdm_name = "core_l4_clkdm",
1900 .recalc = &followparent_recalc,
1901};
1902
1903static struct clk aes2_ick = {
1904 .name = "aes2_ick",
1905 .ops = &clkops_omap2_dflt_wait,
1906 .parent = &core_l4_ick,
1907 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1908 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1909 .clkdm_name = "core_l4_clkdm",
1910 .recalc = &followparent_recalc,
1911};
1912
1913static struct clk sha12_ick = {
1914 .name = "sha12_ick",
1915 .ops = &clkops_omap2_dflt_wait,
1916 .parent = &core_l4_ick,
1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1918 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1919 .clkdm_name = "core_l4_clkdm",
1920 .recalc = &followparent_recalc,
1921};
1922
1923static struct clk des2_ick = {
1924 .name = "des2_ick",
1925 .ops = &clkops_omap2_dflt_wait,
1926 .parent = &core_l4_ick,
1927 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1928 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1929 .clkdm_name = "core_l4_clkdm",
1930 .recalc = &followparent_recalc,
1931};
1932
1933static struct clk mmchs2_ick = {
1934 .name = "mmchs_ick",
1935 .ops = &clkops_omap2_dflt_wait,
1936 .id = 1,
1937 .parent = &core_l4_ick,
1938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1940 .clkdm_name = "core_l4_clkdm",
1941 .recalc = &followparent_recalc,
1942};
1943
1944static struct clk mmchs1_ick = {
1945 .name = "mmchs_ick",
1946 .ops = &clkops_omap2_dflt_wait,
1947 .parent = &core_l4_ick,
1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1950 .clkdm_name = "core_l4_clkdm",
1951 .recalc = &followparent_recalc,
1952};
1953
1954static struct clk mspro_ick = {
1955 .name = "mspro_ick",
1956 .ops = &clkops_omap2_dflt_wait,
1957 .parent = &core_l4_ick,
1958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1959 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1960 .clkdm_name = "core_l4_clkdm",
1961 .recalc = &followparent_recalc,
1962};
1963
1964static struct clk hdq_ick = {
1965 .name = "hdq_ick",
1966 .ops = &clkops_omap2_dflt_wait,
1967 .parent = &core_l4_ick,
1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1969 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1970 .clkdm_name = "core_l4_clkdm",
1971 .recalc = &followparent_recalc,
1972};
1973
1974static struct clk mcspi4_ick = {
1975 .name = "mcspi_ick",
1976 .ops = &clkops_omap2_dflt_wait,
1977 .id = 4,
1978 .parent = &core_l4_ick,
1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1980 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1981 .clkdm_name = "core_l4_clkdm",
1982 .recalc = &followparent_recalc,
1983};
1984
1985static struct clk mcspi3_ick = {
1986 .name = "mcspi_ick",
1987 .ops = &clkops_omap2_dflt_wait,
1988 .id = 3,
1989 .parent = &core_l4_ick,
1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1991 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1992 .clkdm_name = "core_l4_clkdm",
1993 .recalc = &followparent_recalc,
1994};
1995
1996static struct clk mcspi2_ick = {
1997 .name = "mcspi_ick",
1998 .ops = &clkops_omap2_dflt_wait,
1999 .id = 2,
2000 .parent = &core_l4_ick,
2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2003 .clkdm_name = "core_l4_clkdm",
2004 .recalc = &followparent_recalc,
2005};
2006
2007static struct clk mcspi1_ick = {
2008 .name = "mcspi_ick",
2009 .ops = &clkops_omap2_dflt_wait,
2010 .id = 1,
2011 .parent = &core_l4_ick,
2012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2014 .clkdm_name = "core_l4_clkdm",
2015 .recalc = &followparent_recalc,
2016};
2017
2018static struct clk i2c3_ick = {
2019 .name = "i2c_ick",
2020 .ops = &clkops_omap2_dflt_wait,
2021 .id = 3,
2022 .parent = &core_l4_ick,
2023 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2024 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2025 .clkdm_name = "core_l4_clkdm",
2026 .recalc = &followparent_recalc,
2027};
2028
2029static struct clk i2c2_ick = {
2030 .name = "i2c_ick",
2031 .ops = &clkops_omap2_dflt_wait,
2032 .id = 2,
2033 .parent = &core_l4_ick,
2034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2035 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2036 .clkdm_name = "core_l4_clkdm",
2037 .recalc = &followparent_recalc,
2038};
2039
2040static struct clk i2c1_ick = {
2041 .name = "i2c_ick",
2042 .ops = &clkops_omap2_dflt_wait,
2043 .id = 1,
2044 .parent = &core_l4_ick,
2045 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2046 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2047 .clkdm_name = "core_l4_clkdm",
2048 .recalc = &followparent_recalc,
2049};
2050
2051static struct clk uart2_ick = {
2052 .name = "uart2_ick",
2053 .ops = &clkops_omap2_dflt_wait,
2054 .parent = &core_l4_ick,
2055 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2056 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2057 .clkdm_name = "core_l4_clkdm",
2058 .recalc = &followparent_recalc,
2059};
2060
2061static struct clk uart1_ick = {
2062 .name = "uart1_ick",
2063 .ops = &clkops_omap2_dflt_wait,
2064 .parent = &core_l4_ick,
2065 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2066 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2067 .clkdm_name = "core_l4_clkdm",
2068 .recalc = &followparent_recalc,
2069};
2070
2071static struct clk gpt11_ick = {
2072 .name = "gpt11_ick",
2073 .ops = &clkops_omap2_dflt_wait,
2074 .parent = &core_l4_ick,
2075 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2076 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2077 .clkdm_name = "core_l4_clkdm",
2078 .recalc = &followparent_recalc,
2079};
2080
2081static struct clk gpt10_ick = {
2082 .name = "gpt10_ick",
2083 .ops = &clkops_omap2_dflt_wait,
2084 .parent = &core_l4_ick,
2085 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2086 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2087 .clkdm_name = "core_l4_clkdm",
2088 .recalc = &followparent_recalc,
2089};
2090
2091static struct clk mcbsp5_ick = {
2092 .name = "mcbsp_ick",
2093 .ops = &clkops_omap2_dflt_wait,
2094 .id = 5,
2095 .parent = &core_l4_ick,
2096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2097 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2098 .clkdm_name = "core_l4_clkdm",
2099 .recalc = &followparent_recalc,
2100};
2101
2102static struct clk mcbsp1_ick = {
2103 .name = "mcbsp_ick",
2104 .ops = &clkops_omap2_dflt_wait,
2105 .id = 1,
2106 .parent = &core_l4_ick,
2107 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2108 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2109 .clkdm_name = "core_l4_clkdm",
2110 .recalc = &followparent_recalc,
2111};
2112
2113static struct clk fac_ick = {
2114 .name = "fac_ick",
2115 .ops = &clkops_omap2_dflt_wait,
2116 .parent = &core_l4_ick,
2117 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2118 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2119 .clkdm_name = "core_l4_clkdm",
2120 .recalc = &followparent_recalc,
2121};
2122
2123static struct clk mailboxes_ick = {
2124 .name = "mailboxes_ick",
2125 .ops = &clkops_omap2_dflt_wait,
2126 .parent = &core_l4_ick,
2127 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2128 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2129 .clkdm_name = "core_l4_clkdm",
2130 .recalc = &followparent_recalc,
2131};
2132
2133static struct clk omapctrl_ick = {
2134 .name = "omapctrl_ick",
2135 .ops = &clkops_omap2_dflt_wait,
2136 .parent = &core_l4_ick,
2137 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2138 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2139 .flags = ENABLE_ON_INIT,
2140 .recalc = &followparent_recalc,
2141};
2142
2143/* SSI_L4_ICK based clocks */
2144
2145static struct clk ssi_l4_ick = {
2146 .name = "ssi_l4_ick",
2147 .ops = &clkops_null,
2148 .parent = &l4_ick,
2149 .clkdm_name = "core_l4_clkdm",
2150 .recalc = &followparent_recalc,
2151};
2152
2153static struct clk ssi_ick_3430es1 = {
2154 .name = "ssi_ick",
2155 .ops = &clkops_omap2_dflt,
2156 .parent = &ssi_l4_ick,
2157 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2158 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2159 .clkdm_name = "core_l4_clkdm",
2160 .recalc = &followparent_recalc,
2161};
2162
2163static struct clk ssi_ick_3430es2 = {
2164 .name = "ssi_ick",
2165 .ops = &clkops_omap3430es2_ssi_wait,
2166 .parent = &ssi_l4_ick,
2167 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2168 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2169 .clkdm_name = "core_l4_clkdm",
2170 .recalc = &followparent_recalc,
2171};
2172
2173/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2174 * but l4_ick makes more sense to me */
2175
2176static const struct clksel usb_l4_clksel[] = {
2177 { .parent = &l4_ick, .rates = div2_rates },
2178 { .parent = NULL },
2179};
2180
2181static struct clk usb_l4_ick = {
2182 .name = "usb_l4_ick",
2183 .ops = &clkops_omap2_dflt_wait,
2184 .parent = &l4_ick,
2185 .init = &omap2_init_clksel_parent,
2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2187 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2188 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2189 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2190 .clksel = usb_l4_clksel,
2191 .recalc = &omap2_clksel_recalc,
2192};
2193
2194/* SECURITY_L4_ICK2 based clocks */
2195
2196static struct clk security_l4_ick2 = {
2197 .name = "security_l4_ick2",
2198 .ops = &clkops_null,
2199 .parent = &l4_ick,
2200 .recalc = &followparent_recalc,
2201};
2202
2203static struct clk aes1_ick = {
2204 .name = "aes1_ick",
2205 .ops = &clkops_omap2_dflt_wait,
2206 .parent = &security_l4_ick2,
2207 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2208 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2209 .recalc = &followparent_recalc,
2210};
2211
2212static struct clk rng_ick = {
2213 .name = "rng_ick",
2214 .ops = &clkops_omap2_dflt_wait,
2215 .parent = &security_l4_ick2,
2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2217 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2218 .recalc = &followparent_recalc,
2219};
2220
2221static struct clk sha11_ick = {
2222 .name = "sha11_ick",
2223 .ops = &clkops_omap2_dflt_wait,
2224 .parent = &security_l4_ick2,
2225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2226 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2227 .recalc = &followparent_recalc,
2228};
2229
2230static struct clk des1_ick = {
2231 .name = "des1_ick",
2232 .ops = &clkops_omap2_dflt_wait,
2233 .parent = &security_l4_ick2,
2234 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2235 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2236 .recalc = &followparent_recalc,
2237};
2238
2239/* DSS */
2240static struct clk dss1_alwon_fck_3430es1 = {
2241 .name = "dss1_alwon_fck",
2242 .ops = &clkops_omap2_dflt,
2243 .parent = &dpll4_m4x2_ck,
2244 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2245 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2246 .clkdm_name = "dss_clkdm",
2247 .recalc = &followparent_recalc,
2248};
2249
2250static struct clk dss1_alwon_fck_3430es2 = {
2251 .name = "dss1_alwon_fck",
2252 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2253 .parent = &dpll4_m4x2_ck,
2254 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2255 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2256 .clkdm_name = "dss_clkdm",
2257 .recalc = &followparent_recalc,
2258};
2259
2260static struct clk dss_tv_fck = {
2261 .name = "dss_tv_fck",
2262 .ops = &clkops_omap2_dflt,
2263 .parent = &omap_54m_fck,
2264 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2265 .enable_bit = OMAP3430_EN_TV_SHIFT,
2266 .clkdm_name = "dss_clkdm",
2267 .recalc = &followparent_recalc,
2268};
2269
2270static struct clk dss_96m_fck = {
2271 .name = "dss_96m_fck",
2272 .ops = &clkops_omap2_dflt,
2273 .parent = &omap_96m_fck,
2274 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2275 .enable_bit = OMAP3430_EN_TV_SHIFT,
2276 .clkdm_name = "dss_clkdm",
2277 .recalc = &followparent_recalc,
2278};
2279
2280static struct clk dss2_alwon_fck = {
2281 .name = "dss2_alwon_fck",
2282 .ops = &clkops_omap2_dflt,
2283 .parent = &sys_ck,
2284 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2285 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2286 .clkdm_name = "dss_clkdm",
2287 .recalc = &followparent_recalc,
2288};
2289
2290static struct clk dss_ick_3430es1 = {
2291 /* Handles both L3 and L4 clocks */
2292 .name = "dss_ick",
2293 .ops = &clkops_omap2_dflt,
2294 .parent = &l4_ick,
2295 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2296 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2297 .clkdm_name = "dss_clkdm",
2298 .recalc = &followparent_recalc,
2299};
2300
2301static struct clk dss_ick_3430es2 = {
2302 /* Handles both L3 and L4 clocks */
2303 .name = "dss_ick",
2304 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2305 .parent = &l4_ick,
2306 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2307 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2308 .clkdm_name = "dss_clkdm",
2309 .recalc = &followparent_recalc,
2310};
2311
2312/* CAM */
2313
2314static struct clk cam_mclk = {
2315 .name = "cam_mclk",
2316 .ops = &clkops_omap2_dflt,
2317 .parent = &dpll4_m5x2_ck,
2318 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2319 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2320 .clkdm_name = "cam_clkdm",
2321 .recalc = &followparent_recalc,
2322};
2323
2324static struct clk cam_ick = {
2325 /* Handles both L3 and L4 clocks */
2326 .name = "cam_ick",
2327 .ops = &clkops_omap2_dflt,
2328 .parent = &l4_ick,
2329 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2330 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2331 .clkdm_name = "cam_clkdm",
2332 .recalc = &followparent_recalc,
2333};
2334
2335static struct clk csi2_96m_fck = {
2336 .name = "csi2_96m_fck",
2337 .ops = &clkops_omap2_dflt,
2338 .parent = &core_96m_fck,
2339 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2340 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2341 .clkdm_name = "cam_clkdm",
2342 .recalc = &followparent_recalc,
2343};
2344
2345/* USBHOST - 3430ES2 only */
2346
2347static struct clk usbhost_120m_fck = {
2348 .name = "usbhost_120m_fck",
2349 .ops = &clkops_omap2_dflt,
2350 .parent = &dpll5_m2_ck,
2351 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2352 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2353 .clkdm_name = "usbhost_clkdm",
2354 .recalc = &followparent_recalc,
2355};
2356
2357static struct clk usbhost_48m_fck = {
2358 .name = "usbhost_48m_fck",
2359 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2360 .parent = &omap_48m_fck,
2361 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2362 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2363 .clkdm_name = "usbhost_clkdm",
2364 .recalc = &followparent_recalc,
2365};
2366
2367static struct clk usbhost_ick = {
2368 /* Handles both L3 and L4 clocks */
2369 .name = "usbhost_ick",
2370 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2371 .parent = &l4_ick,
2372 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2373 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2374 .clkdm_name = "usbhost_clkdm",
2375 .recalc = &followparent_recalc,
2376};
2377
2378/* WKUP */
2379
2380static const struct clksel_rate usim_96m_rates[] = {
2381 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2382 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2383 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2384 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2385 { .div = 0 },
2386};
2387
2388static const struct clksel_rate usim_120m_rates[] = {
2389 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2390 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2391 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2392 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2393 { .div = 0 },
2394};
2395
2396static const struct clksel usim_clksel[] = {
2397 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2398 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2399 { .parent = &sys_ck, .rates = div2_rates },
2400 { .parent = NULL },
2401};
2402
2403/* 3430ES2 only */
2404static struct clk usim_fck = {
2405 .name = "usim_fck",
2406 .ops = &clkops_omap2_dflt_wait,
2407 .init = &omap2_init_clksel_parent,
2408 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2409 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2410 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2411 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2412 .clksel = usim_clksel,
2413 .recalc = &omap2_clksel_recalc,
2414};
2415
2416/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2417static struct clk gpt1_fck = {
2418 .name = "gpt1_fck",
2419 .ops = &clkops_omap2_dflt_wait,
2420 .init = &omap2_init_clksel_parent,
2421 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2422 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2423 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2424 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2425 .clksel = omap343x_gpt_clksel,
2426 .clkdm_name = "wkup_clkdm",
2427 .recalc = &omap2_clksel_recalc,
2428};
2429
2430static struct clk wkup_32k_fck = {
2431 .name = "wkup_32k_fck",
2432 .ops = &clkops_null,
2433 .parent = &omap_32k_fck,
2434 .clkdm_name = "wkup_clkdm",
2435 .recalc = &followparent_recalc,
2436};
2437
2438static struct clk gpio1_dbck = {
2439 .name = "gpio1_dbck",
2440 .ops = &clkops_omap2_dflt,
2441 .parent = &wkup_32k_fck,
2442 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2443 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2444 .clkdm_name = "wkup_clkdm",
2445 .recalc = &followparent_recalc,
2446};
2447
2448static struct clk wdt2_fck = {
2449 .name = "wdt2_fck",
2450 .ops = &clkops_omap2_dflt_wait,
2451 .parent = &wkup_32k_fck,
2452 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2453 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2454 .clkdm_name = "wkup_clkdm",
2455 .recalc = &followparent_recalc,
2456};
2457
2458static struct clk wkup_l4_ick = {
2459 .name = "wkup_l4_ick",
2460 .ops = &clkops_null,
2461 .parent = &sys_ck,
2462 .clkdm_name = "wkup_clkdm",
2463 .recalc = &followparent_recalc,
2464};
2465
2466/* 3430ES2 only */
2467/* Never specifically named in the TRM, so we have to infer a likely name */
2468static struct clk usim_ick = {
2469 .name = "usim_ick",
2470 .ops = &clkops_omap2_dflt_wait,
2471 .parent = &wkup_l4_ick,
2472 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2473 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2474 .clkdm_name = "wkup_clkdm",
2475 .recalc = &followparent_recalc,
2476};
2477
2478static struct clk wdt2_ick = {
2479 .name = "wdt2_ick",
2480 .ops = &clkops_omap2_dflt_wait,
2481 .parent = &wkup_l4_ick,
2482 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2483 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2484 .clkdm_name = "wkup_clkdm",
2485 .recalc = &followparent_recalc,
2486};
2487
2488static struct clk wdt1_ick = {
2489 .name = "wdt1_ick",
2490 .ops = &clkops_omap2_dflt_wait,
2491 .parent = &wkup_l4_ick,
2492 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2493 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2494 .clkdm_name = "wkup_clkdm",
2495 .recalc = &followparent_recalc,
2496};
2497
2498static struct clk gpio1_ick = {
2499 .name = "gpio1_ick",
2500 .ops = &clkops_omap2_dflt_wait,
2501 .parent = &wkup_l4_ick,
2502 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2503 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2504 .clkdm_name = "wkup_clkdm",
2505 .recalc = &followparent_recalc,
2506};
2507
2508static struct clk omap_32ksync_ick = {
2509 .name = "omap_32ksync_ick",
2510 .ops = &clkops_omap2_dflt_wait,
2511 .parent = &wkup_l4_ick,
2512 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2513 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2514 .clkdm_name = "wkup_clkdm",
2515 .recalc = &followparent_recalc,
2516};
2517
2518/* XXX This clock no longer exists in 3430 TRM rev F */
2519static struct clk gpt12_ick = {
2520 .name = "gpt12_ick",
2521 .ops = &clkops_omap2_dflt_wait,
2522 .parent = &wkup_l4_ick,
2523 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2524 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2525 .clkdm_name = "wkup_clkdm",
2526 .recalc = &followparent_recalc,
2527};
2528
2529static struct clk gpt1_ick = {
2530 .name = "gpt1_ick",
2531 .ops = &clkops_omap2_dflt_wait,
2532 .parent = &wkup_l4_ick,
2533 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2534 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2535 .clkdm_name = "wkup_clkdm",
2536 .recalc = &followparent_recalc,
2537};
2538
2539
2540
2541/* PER clock domain */
2542
2543static struct clk per_96m_fck = {
2544 .name = "per_96m_fck",
2545 .ops = &clkops_null,
2546 .parent = &omap_96m_alwon_fck,
2547 .clkdm_name = "per_clkdm",
2548 .recalc = &followparent_recalc,
2549};
2550
2551static struct clk per_48m_fck = {
2552 .name = "per_48m_fck",
2553 .ops = &clkops_null,
2554 .parent = &omap_48m_fck,
2555 .clkdm_name = "per_clkdm",
2556 .recalc = &followparent_recalc,
2557};
2558
2559static struct clk uart3_fck = {
2560 .name = "uart3_fck",
2561 .ops = &clkops_omap2_dflt_wait,
2562 .parent = &per_48m_fck,
2563 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2565 .clkdm_name = "per_clkdm",
2566 .recalc = &followparent_recalc,
2567};
2568
2569static struct clk gpt2_fck = {
2570 .name = "gpt2_fck",
2571 .ops = &clkops_omap2_dflt_wait,
2572 .init = &omap2_init_clksel_parent,
2573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2574 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2575 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2576 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2577 .clksel = omap343x_gpt_clksel,
2578 .clkdm_name = "per_clkdm",
2579 .recalc = &omap2_clksel_recalc,
2580};
2581
2582static struct clk gpt3_fck = {
2583 .name = "gpt3_fck",
2584 .ops = &clkops_omap2_dflt_wait,
2585 .init = &omap2_init_clksel_parent,
2586 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2587 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2588 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2589 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2590 .clksel = omap343x_gpt_clksel,
2591 .clkdm_name = "per_clkdm",
2592 .recalc = &omap2_clksel_recalc,
2593};
2594
2595static struct clk gpt4_fck = {
2596 .name = "gpt4_fck",
2597 .ops = &clkops_omap2_dflt_wait,
2598 .init = &omap2_init_clksel_parent,
2599 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2600 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2601 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2602 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2603 .clksel = omap343x_gpt_clksel,
2604 .clkdm_name = "per_clkdm",
2605 .recalc = &omap2_clksel_recalc,
2606};
2607
2608static struct clk gpt5_fck = {
2609 .name = "gpt5_fck",
2610 .ops = &clkops_omap2_dflt_wait,
2611 .init = &omap2_init_clksel_parent,
2612 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2613 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2614 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2615 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2616 .clksel = omap343x_gpt_clksel,
2617 .clkdm_name = "per_clkdm",
2618 .recalc = &omap2_clksel_recalc,
2619};
2620
2621static struct clk gpt6_fck = {
2622 .name = "gpt6_fck",
2623 .ops = &clkops_omap2_dflt_wait,
2624 .init = &omap2_init_clksel_parent,
2625 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2626 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2627 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2628 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2629 .clksel = omap343x_gpt_clksel,
2630 .clkdm_name = "per_clkdm",
2631 .recalc = &omap2_clksel_recalc,
2632};
2633
2634static struct clk gpt7_fck = {
2635 .name = "gpt7_fck",
2636 .ops = &clkops_omap2_dflt_wait,
2637 .init = &omap2_init_clksel_parent,
2638 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2639 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2640 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2641 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2642 .clksel = omap343x_gpt_clksel,
2643 .clkdm_name = "per_clkdm",
2644 .recalc = &omap2_clksel_recalc,
2645};
2646
2647static struct clk gpt8_fck = {
2648 .name = "gpt8_fck",
2649 .ops = &clkops_omap2_dflt_wait,
2650 .init = &omap2_init_clksel_parent,
2651 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2652 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2653 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2654 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2655 .clksel = omap343x_gpt_clksel,
2656 .clkdm_name = "per_clkdm",
2657 .recalc = &omap2_clksel_recalc,
2658};
2659
2660static struct clk gpt9_fck = {
2661 .name = "gpt9_fck",
2662 .ops = &clkops_omap2_dflt_wait,
2663 .init = &omap2_init_clksel_parent,
2664 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2665 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2666 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2667 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2668 .clksel = omap343x_gpt_clksel,
2669 .clkdm_name = "per_clkdm",
2670 .recalc = &omap2_clksel_recalc,
2671};
2672
2673static struct clk per_32k_alwon_fck = {
2674 .name = "per_32k_alwon_fck",
2675 .ops = &clkops_null,
2676 .parent = &omap_32k_fck,
2677 .clkdm_name = "per_clkdm",
2678 .recalc = &followparent_recalc,
2679};
2680
2681static struct clk gpio6_dbck = {
2682 .name = "gpio6_dbck",
2683 .ops = &clkops_omap2_dflt,
2684 .parent = &per_32k_alwon_fck,
2685 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2686 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2687 .clkdm_name = "per_clkdm",
2688 .recalc = &followparent_recalc,
2689};
2690
2691static struct clk gpio5_dbck = {
2692 .name = "gpio5_dbck",
2693 .ops = &clkops_omap2_dflt,
2694 .parent = &per_32k_alwon_fck,
2695 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2696 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2697 .clkdm_name = "per_clkdm",
2698 .recalc = &followparent_recalc,
2699};
2700
2701static struct clk gpio4_dbck = {
2702 .name = "gpio4_dbck",
2703 .ops = &clkops_omap2_dflt,
2704 .parent = &per_32k_alwon_fck,
2705 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2706 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2707 .clkdm_name = "per_clkdm",
2708 .recalc = &followparent_recalc,
2709};
2710
2711static struct clk gpio3_dbck = {
2712 .name = "gpio3_dbck",
2713 .ops = &clkops_omap2_dflt,
2714 .parent = &per_32k_alwon_fck,
2715 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2716 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2717 .clkdm_name = "per_clkdm",
2718 .recalc = &followparent_recalc,
2719};
2720
2721static struct clk gpio2_dbck = {
2722 .name = "gpio2_dbck",
2723 .ops = &clkops_omap2_dflt,
2724 .parent = &per_32k_alwon_fck,
2725 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2726 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2727 .clkdm_name = "per_clkdm",
2728 .recalc = &followparent_recalc,
2729};
2730
2731static struct clk wdt3_fck = {
2732 .name = "wdt3_fck",
2733 .ops = &clkops_omap2_dflt_wait,
2734 .parent = &per_32k_alwon_fck,
2735 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2736 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2737 .clkdm_name = "per_clkdm",
2738 .recalc = &followparent_recalc,
2739};
2740
2741static struct clk per_l4_ick = {
2742 .name = "per_l4_ick",
2743 .ops = &clkops_null,
2744 .parent = &l4_ick,
2745 .clkdm_name = "per_clkdm",
2746 .recalc = &followparent_recalc,
2747};
2748
2749static struct clk gpio6_ick = {
2750 .name = "gpio6_ick",
2751 .ops = &clkops_omap2_dflt_wait,
2752 .parent = &per_l4_ick,
2753 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2754 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2755 .clkdm_name = "per_clkdm",
2756 .recalc = &followparent_recalc,
2757};
2758
2759static struct clk gpio5_ick = {
2760 .name = "gpio5_ick",
2761 .ops = &clkops_omap2_dflt_wait,
2762 .parent = &per_l4_ick,
2763 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2764 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2765 .clkdm_name = "per_clkdm",
2766 .recalc = &followparent_recalc,
2767};
2768
2769static struct clk gpio4_ick = {
2770 .name = "gpio4_ick",
2771 .ops = &clkops_omap2_dflt_wait,
2772 .parent = &per_l4_ick,
2773 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2774 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2775 .clkdm_name = "per_clkdm",
2776 .recalc = &followparent_recalc,
2777};
2778
2779static struct clk gpio3_ick = {
2780 .name = "gpio3_ick",
2781 .ops = &clkops_omap2_dflt_wait,
2782 .parent = &per_l4_ick,
2783 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2784 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2785 .clkdm_name = "per_clkdm",
2786 .recalc = &followparent_recalc,
2787};
2788
2789static struct clk gpio2_ick = {
2790 .name = "gpio2_ick",
2791 .ops = &clkops_omap2_dflt_wait,
2792 .parent = &per_l4_ick,
2793 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2794 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2795 .clkdm_name = "per_clkdm",
2796 .recalc = &followparent_recalc,
2797};
2798
2799static struct clk wdt3_ick = {
2800 .name = "wdt3_ick",
2801 .ops = &clkops_omap2_dflt_wait,
2802 .parent = &per_l4_ick,
2803 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2804 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2805 .clkdm_name = "per_clkdm",
2806 .recalc = &followparent_recalc,
2807};
2808
2809static struct clk uart3_ick = {
2810 .name = "uart3_ick",
2811 .ops = &clkops_omap2_dflt_wait,
2812 .parent = &per_l4_ick,
2813 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2814 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2815 .clkdm_name = "per_clkdm",
2816 .recalc = &followparent_recalc,
2817};
2818
2819static struct clk gpt9_ick = {
2820 .name = "gpt9_ick",
2821 .ops = &clkops_omap2_dflt_wait,
2822 .parent = &per_l4_ick,
2823 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2824 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2825 .clkdm_name = "per_clkdm",
2826 .recalc = &followparent_recalc,
2827};
2828
2829static struct clk gpt8_ick = {
2830 .name = "gpt8_ick",
2831 .ops = &clkops_omap2_dflt_wait,
2832 .parent = &per_l4_ick,
2833 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2834 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2835 .clkdm_name = "per_clkdm",
2836 .recalc = &followparent_recalc,
2837};
2838
2839static struct clk gpt7_ick = {
2840 .name = "gpt7_ick",
2841 .ops = &clkops_omap2_dflt_wait,
2842 .parent = &per_l4_ick,
2843 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2844 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2845 .clkdm_name = "per_clkdm",
2846 .recalc = &followparent_recalc,
2847};
2848
2849static struct clk gpt6_ick = {
2850 .name = "gpt6_ick",
2851 .ops = &clkops_omap2_dflt_wait,
2852 .parent = &per_l4_ick,
2853 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2854 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2855 .clkdm_name = "per_clkdm",
2856 .recalc = &followparent_recalc,
2857};
2858
2859static struct clk gpt5_ick = {
2860 .name = "gpt5_ick",
2861 .ops = &clkops_omap2_dflt_wait,
2862 .parent = &per_l4_ick,
2863 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2864 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2865 .clkdm_name = "per_clkdm",
2866 .recalc = &followparent_recalc,
2867};
2868
2869static struct clk gpt4_ick = {
2870 .name = "gpt4_ick",
2871 .ops = &clkops_omap2_dflt_wait,
2872 .parent = &per_l4_ick,
2873 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2874 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2875 .clkdm_name = "per_clkdm",
2876 .recalc = &followparent_recalc,
2877};
2878
2879static struct clk gpt3_ick = {
2880 .name = "gpt3_ick",
2881 .ops = &clkops_omap2_dflt_wait,
2882 .parent = &per_l4_ick,
2883 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2884 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2885 .clkdm_name = "per_clkdm",
2886 .recalc = &followparent_recalc,
2887};
2888
2889static struct clk gpt2_ick = {
2890 .name = "gpt2_ick",
2891 .ops = &clkops_omap2_dflt_wait,
2892 .parent = &per_l4_ick,
2893 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2894 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2895 .clkdm_name = "per_clkdm",
2896 .recalc = &followparent_recalc,
2897};
2898
2899static struct clk mcbsp2_ick = {
2900 .name = "mcbsp_ick",
2901 .ops = &clkops_omap2_dflt_wait,
2902 .id = 2,
2903 .parent = &per_l4_ick,
2904 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2905 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2906 .clkdm_name = "per_clkdm",
2907 .recalc = &followparent_recalc,
2908};
2909
2910static struct clk mcbsp3_ick = {
2911 .name = "mcbsp_ick",
2912 .ops = &clkops_omap2_dflt_wait,
2913 .id = 3,
2914 .parent = &per_l4_ick,
2915 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2916 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2917 .clkdm_name = "per_clkdm",
2918 .recalc = &followparent_recalc,
2919};
2920
2921static struct clk mcbsp4_ick = {
2922 .name = "mcbsp_ick",
2923 .ops = &clkops_omap2_dflt_wait,
2924 .id = 4,
2925 .parent = &per_l4_ick,
2926 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2927 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2928 .clkdm_name = "per_clkdm",
2929 .recalc = &followparent_recalc,
2930};
2931
2932static const struct clksel mcbsp_234_clksel[] = {
Paul Walmsley073463c2010-01-08 15:23:07 -0700[diff] [blame]2933 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]2934 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2935 { .parent = NULL }
2936};
2937
2938static struct clk mcbsp2_fck = {
2939 .name = "mcbsp_fck",
2940 .ops = &clkops_omap2_dflt_wait,
2941 .id = 2,
2942 .init = &omap2_init_clksel_parent,
2943 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2944 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2945 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2946 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2947 .clksel = mcbsp_234_clksel,
2948 .clkdm_name = "per_clkdm",
2949 .recalc = &omap2_clksel_recalc,
2950};
2951
2952static struct clk mcbsp3_fck = {
2953 .name = "mcbsp_fck",
2954 .ops = &clkops_omap2_dflt_wait,
2955 .id = 3,
2956 .init = &omap2_init_clksel_parent,
2957 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2958 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2959 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2960 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2961 .clksel = mcbsp_234_clksel,
2962 .clkdm_name = "per_clkdm",
2963 .recalc = &omap2_clksel_recalc,
2964};
2965
2966static struct clk mcbsp4_fck = {
2967 .name = "mcbsp_fck",
2968 .ops = &clkops_omap2_dflt_wait,
2969 .id = 4,
2970 .init = &omap2_init_clksel_parent,
2971 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2972 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2973 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2974 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2975 .clksel = mcbsp_234_clksel,
2976 .clkdm_name = "per_clkdm",
2977 .recalc = &omap2_clksel_recalc,
2978};
2979
2980/* EMU clocks */
2981
2982/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2983
2984static const struct clksel_rate emu_src_sys_rates[] = {
2985 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2986 { .div = 0 },
2987};
2988
2989static const struct clksel_rate emu_src_core_rates[] = {
2990 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2991 { .div = 0 },
2992};
2993
2994static const struct clksel_rate emu_src_per_rates[] = {
2995 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2996 { .div = 0 },
2997};
2998
2999static const struct clksel_rate emu_src_mpu_rates[] = {
3000 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3001 { .div = 0 },
3002};
3003
3004static const struct clksel emu_src_clksel[] = {
3005 { .parent = &sys_ck, .rates = emu_src_sys_rates },
3006 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3007 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
3008 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
3009 { .parent = NULL },
3010};
3011
3012/*
3013 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3014 * to switch the source of some of the EMU clocks.
3015 * XXX Are there CLKEN bits for these EMU clks?
3016 */
3017static struct clk emu_src_ck = {
3018 .name = "emu_src_ck",
3019 .ops = &clkops_null,
3020 .init = &omap2_init_clksel_parent,
3021 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3022 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
3023 .clksel = emu_src_clksel,
3024 .clkdm_name = "emu_clkdm",
3025 .recalc = &omap2_clksel_recalc,
3026};
3027
3028static const struct clksel_rate pclk_emu_rates[] = {
3029 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3030 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3031 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3032 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3033 { .div = 0 },
3034};
3035
3036static const struct clksel pclk_emu_clksel[] = {
3037 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3038 { .parent = NULL },
3039};
3040
3041static struct clk pclk_fck = {
3042 .name = "pclk_fck",
3043 .ops = &clkops_null,
3044 .init = &omap2_init_clksel_parent,
3045 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3046 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3047 .clksel = pclk_emu_clksel,
3048 .clkdm_name = "emu_clkdm",
3049 .recalc = &omap2_clksel_recalc,
3050};
3051
3052static const struct clksel_rate pclkx2_emu_rates[] = {
3053 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3054 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3055 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3056 { .div = 0 },
3057};
3058
3059static const struct clksel pclkx2_emu_clksel[] = {
3060 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3061 { .parent = NULL },
3062};
3063
3064static struct clk pclkx2_fck = {
3065 .name = "pclkx2_fck",
3066 .ops = &clkops_null,
3067 .init = &omap2_init_clksel_parent,
3068 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3069 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3070 .clksel = pclkx2_emu_clksel,
3071 .clkdm_name = "emu_clkdm",
3072 .recalc = &omap2_clksel_recalc,
3073};
3074
3075static const struct clksel atclk_emu_clksel[] = {
3076 { .parent = &emu_src_ck, .rates = div2_rates },
3077 { .parent = NULL },
3078};
3079
3080static struct clk atclk_fck = {
3081 .name = "atclk_fck",
3082 .ops = &clkops_null,
3083 .init = &omap2_init_clksel_parent,
3084 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3085 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3086 .clksel = atclk_emu_clksel,
3087 .clkdm_name = "emu_clkdm",
3088 .recalc = &omap2_clksel_recalc,
3089};
3090
3091static struct clk traceclk_src_fck = {
3092 .name = "traceclk_src_fck",
3093 .ops = &clkops_null,
3094 .init = &omap2_init_clksel_parent,
3095 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3096 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3097 .clksel = emu_src_clksel,
3098 .clkdm_name = "emu_clkdm",
3099 .recalc = &omap2_clksel_recalc,
3100};
3101
3102static const struct clksel_rate traceclk_rates[] = {
3103 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3104 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3105 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3106 { .div = 0 },
3107};
3108
3109static const struct clksel traceclk_clksel[] = {
3110 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3111 { .parent = NULL },
3112};
3113
3114static struct clk traceclk_fck = {
3115 .name = "traceclk_fck",
3116 .ops = &clkops_null,
3117 .init = &omap2_init_clksel_parent,
3118 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3119 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3120 .clksel = traceclk_clksel,
3121 .clkdm_name = "emu_clkdm",
3122 .recalc = &omap2_clksel_recalc,
3123};
3124
3125/* SR clocks */
3126
3127/* SmartReflex fclk (VDD1) */
3128static struct clk sr1_fck = {
3129 .name = "sr1_fck",
3130 .ops = &clkops_omap2_dflt_wait,
3131 .parent = &sys_ck,
3132 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3133 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3134 .recalc = &followparent_recalc,
3135};
3136
3137/* SmartReflex fclk (VDD2) */
3138static struct clk sr2_fck = {
3139 .name = "sr2_fck",
3140 .ops = &clkops_omap2_dflt_wait,
3141 .parent = &sys_ck,
3142 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3143 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3144 .recalc = &followparent_recalc,
3145};
3146
3147static struct clk sr_l4_ick = {
3148 .name = "sr_l4_ick",
3149 .ops = &clkops_null, /* RMK: missing? */
3150 .parent = &l4_ick,
3151 .clkdm_name = "core_l4_clkdm",
3152 .recalc = &followparent_recalc,
3153};
3154
3155/* SECURE_32K_FCK clocks */
3156
3157static struct clk gpt12_fck = {
3158 .name = "gpt12_fck",
3159 .ops = &clkops_null,
3160 .parent = &secure_32k_fck,
3161 .recalc = &followparent_recalc,
3162};
3163
3164static struct clk wdt1_fck = {
3165 .name = "wdt1_fck",
3166 .ops = &clkops_null,
3167 .parent = &secure_32k_fck,
3168 .recalc = &followparent_recalc,
3169};
3170
Ranjith Lohithakshan3cc4a2f2010-02-24 12:05:55 -0700[diff] [blame]3171/* Clocks for AM35XX */
3172static struct clk ipss_ick = {
3173 .name = "ipss_ick",
3174 .ops = &clkops_am35xx_ipss_wait,
3175 .parent = &core_l3_ick,
3176 .clkdm_name = "core_l3_clkdm",
3177 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3178 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3179 .recalc = &followparent_recalc,
3180};
3181
3182static struct clk emac_ick = {
3183 .name = "emac_ick",
3184 .ops = &clkops_am35xx_ipss_module_wait,
3185 .parent = &ipss_ick,
3186 .clkdm_name = "core_l3_clkdm",
3187 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3188 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3189 .recalc = &followparent_recalc,
3190};
3191
3192static struct clk rmii_ck = {
3193 .name = "rmii_ck",
3194 .ops = &clkops_null,
3195 .flags = RATE_FIXED,
3196 .rate = 50000000,
3197};
3198
3199static struct clk emac_fck = {
3200 .name = "emac_fck",
3201 .ops = &clkops_omap2_dflt,
3202 .parent = &rmii_ck,
3203 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3204 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3205 .recalc = &followparent_recalc,
3206};
3207
3208static struct clk hsotgusb_ick_am35xx = {
3209 .name = "hsotgusb_ick",
3210 .ops = &clkops_am35xx_ipss_module_wait,
3211 .parent = &ipss_ick,
3212 .clkdm_name = "core_l3_clkdm",
3213 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3214 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3215 .recalc = &followparent_recalc,
3216};
3217
3218static struct clk hsotgusb_fck_am35xx = {
3219 .name = "hsotgusb_fck",
3220 .ops = &clkops_omap2_dflt,
3221 .parent = &sys_ck,
3222 .clkdm_name = "core_l3_clkdm",
3223 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3224 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3225 .recalc = &followparent_recalc,
3226};
3227
3228static struct clk hecc_ck = {
3229 .name = "hecc_ck",
3230 .ops = &clkops_am35xx_ipss_module_wait,
3231 .parent = &sys_ck,
3232 .clkdm_name = "core_l3_clkdm",
3233 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3234 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3235 .recalc = &followparent_recalc,
3236};
3237
3238static struct clk vpfe_ick = {
3239 .name = "vpfe_ick",
3240 .ops = &clkops_am35xx_ipss_module_wait,
3241 .parent = &ipss_ick,
3242 .clkdm_name = "core_l3_clkdm",
3243 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3244 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3245 .recalc = &followparent_recalc,
3246};
3247
3248static struct clk pclk_ck = {
3249 .name = "pclk_ck",
3250 .ops = &clkops_null,
3251 .flags = RATE_FIXED,
3252 .rate = 27000000,
3253};
3254
3255static struct clk vpfe_fck = {
3256 .name = "vpfe_fck",
3257 .ops = &clkops_omap2_dflt,
3258 .parent = &pclk_ck,
3259 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3260 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3261 .recalc = &followparent_recalc,
3262};
3263
3264/*
3265 * The UART1/2 functional clock acts as the functional
3266 * clock for UART4. No separate fclk control available.
3267 */
3268static struct clk uart4_ick_am35xx = {
3269 .name = "uart4_ick",
3270 .ops = &clkops_omap2_dflt_wait,
3271 .parent = &core_l4_ick,
3272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3273 .enable_bit = AM35XX_EN_UART4_SHIFT,
3274 .clkdm_name = "core_l4_clkdm",
3275 .recalc = &followparent_recalc,
3276};
3277
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3278
3279/*
3280 * clkdev
3281 */
3282
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3283/* XXX At some point we should rename this file to clock3xxx_data.c */
3284static struct omap_clk omap3xxx_clks[] = {
3285 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3286 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3287 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3288 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3289 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3290 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3291 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3292 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3293 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3294 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3295 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3296 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3297 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3298 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3299 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3300 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
3301 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3302 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3303 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3304 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3305 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3306 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3307 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3308 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3309 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3310 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3311 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]3312 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3313 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3314 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3315 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3316 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3317 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3318 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3319 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3320 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3321 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3322 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3323 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3324 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3325 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3326 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3327 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3328 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3329 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3330 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
3331 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
3332 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3333 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3334 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3335 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3336 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3337 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3338 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3339 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
3340 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3341 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3342 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3343 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3344 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3345 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3346 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3347 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3348 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3349 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
3350 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3351 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3352 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
3353 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
3354 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3355 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3356 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3357 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
3358 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
3359 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
3360 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3361 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
3362 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3363 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3364 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3365 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
3366 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
3367 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
3368 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3369 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3370 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3371 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
3372 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
3373 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
3374 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
3375 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3376 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3377 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3378 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3379 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3380 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3381 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
3382 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3383 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3384 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3385 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3386 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3387 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3388 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3389 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
3390 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3391 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3392 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
3393 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3394 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3395 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
3396 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
3397 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3398 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3399 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3400 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3401 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3402 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3403 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3404 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3405 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3406 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
3407 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
3408 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
3409 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3410 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3411 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3412 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3413 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3414 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3415 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3416 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3417 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3418 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3419 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3420 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
3421 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3422 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
3423 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
3424 CLK("omap_rng", "ick", &rng_ick, CK_343X),
3425 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
3426 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3427 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3428 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3429 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3430 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3431 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3432 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3433 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3434 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
3435 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
3436 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3437 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3438 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3439 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3440 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3441 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3442 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3443 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3444 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3445 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
3446 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3447 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3448 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3449 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3450 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3451 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3452 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3453 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3454 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3455 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3456 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3457 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3458 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3459 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3460 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3461 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3462 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3463 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3464 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3465 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3466 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3467 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3468 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3469 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3470 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3471 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3472 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3473 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3474 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3475 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3476 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3477 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3478 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3479 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3480 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3481 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3482 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3483 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3484 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3485 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3486 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3487 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3488 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3489 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3490 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
3491 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
3492 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
3493 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3494 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3495 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3496 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3497 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3498 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3499 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
3500 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
3501 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3502 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3503 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3504 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
Ranjith Lohithakshan3cc4a2f2010-02-24 12:05:55 -0700[diff] [blame]3505 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3506 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3507 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3508 CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX),
3509 CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX),
3510 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3511 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3512 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3513 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3514 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3515 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3516};
3517
3518
Paul Walmsleye80a9722010-01-26 20:13:12 -0700[diff] [blame]3519int __init omap3xxx_clk_init(void)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3520{
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3521 struct omap_clk *c;
Paul Walmsley2c8a1772010-01-26 20:12:56 -0700[diff] [blame]3522 u32 cpu_clkflg = CK_3XXX;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3523
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3524 if (cpu_is_omap3517()) {
3525 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3526 cpu_clkflg |= CK_3517;
3527 } else if (cpu_is_omap3505()) {
3528 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3529 cpu_clkflg |= CK_3505;
3530 } else if (cpu_is_omap34xx()) {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3531 cpu_mask = RATE_IN_343X;
Paul Walmsley2c8a1772010-01-26 20:12:56 -0700[diff] [blame]3532 cpu_clkflg |= CK_343X;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3533
3534 /*
3535 * Update this if there are further clock changes between ES2
3536 * and production parts
3537 */
3538 if (omap_rev() == OMAP3430_REV_ES1_0) {
3539 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3540 cpu_clkflg |= CK_3430ES1;
3541 } else {
3542 cpu_mask |= RATE_IN_3430ES2;
3543 cpu_clkflg |= CK_3430ES2;
3544 }
3545 }
Vishwanath BS7356f0b2010-02-22 22:09:10 -0700[diff] [blame]3546 if (omap3_has_192mhz_clk())
3547 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3548
Mike Turquettea7e069f2010-02-24 12:06:00 -0700[diff] [blame]3549 if (cpu_is_omap3630()) {
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]3550 cpu_mask |= RATE_IN_36XX;
3551 cpu_clkflg |= CK_36XX;
3552
3553 /*
3554 * XXX This type of dynamic rewriting of the clock tree is
3555 * deprecated and should be revised soon.
3556 */
3557 dpll4_m2_ck = dpll4_m2_ck_3630;
3558 dpll4_m3_ck = dpll4_m3_ck_3630;
3559 dpll4_m4_ck = dpll4_m4_ck_3630;
3560 dpll4_m5_ck = dpll4_m5_ck_3630;
3561 dpll4_m6_ck = dpll4_m6_ck_3630;
3562
Mike Turquettea7e069f2010-02-24 12:06:00 -0700[diff] [blame]3563 /*
3564 * For 3630: override clkops_omap2_dflt_wait for the
3565 * clocks affected from PWRDN reset Limitation
3566 */
3567 dpll3_m3x2_ck.ops =
3568 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3569 dpll4_m2x2_ck.ops =
3570 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3571 dpll4_m3x2_ck.ops =
3572 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3573 dpll4_m4x2_ck.ops =
3574 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3575 dpll4_m5x2_ck.ops =
3576 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3577 dpll4_m6x2_ck.ops =
3578 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame]3579 } else {
3580 /*
3581 * XXX This type of dynamic rewriting of the clock tree is
3582 * deprecated and should be revised soon.
3583 */
3584 dpll4_m2_ck = dpll4_m2_ck_34xx;
3585 dpll4_m3_ck = dpll4_m3_ck_34xx;
3586 dpll4_m4_ck = dpll4_m4_ck_34xx;
3587 dpll4_m5_ck = dpll4_m5_ck_34xx;
3588 dpll4_m6_ck = dpll4_m6_ck_34xx;
Mike Turquettea7e069f2010-02-24 12:06:00 -0700[diff] [blame]3589 }
3590
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]3591 if (cpu_is_omap3630())
3592 dpll4_dd = dpll4_dd_3630;
3593 else
3594 dpll4_dd = dpll4_dd_34xx;
3595
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3596 clk_init(&omap2_clk_functions);
3597
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3598 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3599 clk_preinit(c->lk.clk);
3600
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3601 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3602 if (c->cpu & cpu_clkflg) {
3603 clkdev_add(&c->lk);
3604 clk_register(c->lk.clk);
3605 omap2_init_clk_clkdm(c->lk.clk);
3606 }
3607
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3608 recalculate_root_clocks();
3609
3610 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3611 "%ld.%01ld/%ld/%ld MHz\n",
3612 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3613 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3614
3615 /*
3616 * Only enable those clocks we will need, let the drivers
3617 * enable other clocks as necessary
3618 */
3619 clk_enable_init_clocks();
3620
3621 /*
3622 * Lock DPLL5 and put it in autoidle.
3623 */
3624 if (omap_rev() >= OMAP3430_REV_ES2_0)
3625 omap3_clk_lock_dpll5();
3626
3627 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3628 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3629 arm_fck_p = clk_get(NULL, "arm_fck");
3630
3631 return 0;
3632}