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Russell Kingf27ecac2005-08-18 21:31:00 +01001/*
2 * linux/arch/arm/common/gic.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Interrupt architecture for the GIC:
11 *
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
14 *
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010017 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
Russell Kingf27ecac2005-08-18 21:31:00 +010020 *
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
24 */
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/smp.h>
Catalin Marinasdcb86e82005-08-31 21:45:14 +010029#include <linux/cpumask.h>
Russell Kingfced80c2008-09-06 12:10:45 +010030#include <linux/io.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010031
32#include <asm/irq.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010033#include <asm/mach/irq.h>
34#include <asm/hardware/gic.h>
35
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010036static DEFINE_SPINLOCK(irq_controller_lock);
Russell Kingf27ecac2005-08-18 21:31:00 +010037
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010038struct gic_chip_data {
39 unsigned int irq_offset;
40 void __iomem *dist_base;
41 void __iomem *cpu_base;
42};
43
44#ifndef MAX_GIC_NR
45#define MAX_GIC_NR 1
46#endif
47
48static struct gic_chip_data gic_data[MAX_GIC_NR];
49
50static inline void __iomem *gic_dist_base(unsigned int irq)
51{
52 struct gic_chip_data *gic_data = get_irq_chip_data(irq);
53 return gic_data->dist_base;
54}
55
56static inline void __iomem *gic_cpu_base(unsigned int irq)
57{
58 struct gic_chip_data *gic_data = get_irq_chip_data(irq);
59 return gic_data->cpu_base;
60}
61
62static inline unsigned int gic_irq(unsigned int irq)
63{
64 struct gic_chip_data *gic_data = get_irq_chip_data(irq);
65 return irq - gic_data->irq_offset;
66}
67
Russell Kingf27ecac2005-08-18 21:31:00 +010068/*
69 * Routines to acknowledge, disable and enable interrupts
Russell Kingf27ecac2005-08-18 21:31:00 +010070 */
71static void gic_ack_irq(unsigned int irq)
72{
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010073
74 spin_lock(&irq_controller_lock);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010075 writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010076 spin_unlock(&irq_controller_lock);
Russell Kingf27ecac2005-08-18 21:31:00 +010077}
78
79static void gic_mask_irq(unsigned int irq)
80{
81 u32 mask = 1 << (irq % 32);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010082
83 spin_lock(&irq_controller_lock);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010084 writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010085 spin_unlock(&irq_controller_lock);
Russell Kingf27ecac2005-08-18 21:31:00 +010086}
87
88static void gic_unmask_irq(unsigned int irq)
89{
90 u32 mask = 1 << (irq % 32);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010091
92 spin_lock(&irq_controller_lock);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010093 writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +010094 spin_unlock(&irq_controller_lock);
Russell Kingf27ecac2005-08-18 21:31:00 +010095}
96
Rabin Vincent5c0c1f02010-05-28 04:37:38 +010097static int gic_set_type(unsigned int irq, unsigned int type)
98{
99 void __iomem *base = gic_dist_base(irq);
100 unsigned int gicirq = gic_irq(irq);
101 u32 enablemask = 1 << (gicirq % 32);
102 u32 enableoff = (gicirq / 32) * 4;
103 u32 confmask = 0x2 << ((gicirq % 16) * 2);
104 u32 confoff = (gicirq / 16) * 4;
105 bool enabled = false;
106 u32 val;
107
108 /* Interrupt configuration for SGIs can't be changed */
109 if (gicirq < 16)
110 return -EINVAL;
111
112 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
113 return -EINVAL;
114
115 spin_lock(&irq_controller_lock);
116
117 val = readl(base + GIC_DIST_CONFIG + confoff);
118 if (type == IRQ_TYPE_LEVEL_HIGH)
119 val &= ~confmask;
120 else if (type == IRQ_TYPE_EDGE_RISING)
121 val |= confmask;
122
123 /*
124 * As recommended by the spec, disable the interrupt before changing
125 * the configuration
126 */
127 if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
128 writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
129 enabled = true;
130 }
131
132 writel(val, base + GIC_DIST_CONFIG + confoff);
133
134 if (enabled)
135 writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
136
137 spin_unlock(&irq_controller_lock);
138
139 return 0;
140}
141
Catalin Marinasa06f5462005-09-30 16:07:05 +0100142#ifdef CONFIG_SMP
Yinghai Lud5dedd42009-04-27 17:59:21 -0700143static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
Russell Kingf27ecac2005-08-18 21:31:00 +0100144{
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100145 void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
Russell Kingf27ecac2005-08-18 21:31:00 +0100146 unsigned int shift = (irq % 4) * 8;
Rusty Russell0de26522008-12-13 21:20:26 +1030147 unsigned int cpu = cpumask_first(mask_val);
Russell Kingf27ecac2005-08-18 21:31:00 +0100148 u32 val;
149
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100150 spin_lock(&irq_controller_lock);
Catalin Marinas41184f62009-06-19 11:30:12 +0100151 irq_desc[irq].node = cpu;
Russell Kingf27ecac2005-08-18 21:31:00 +0100152 val = readl(reg) & ~(0xff << shift);
153 val |= 1 << (cpu + shift);
154 writel(val, reg);
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100155 spin_unlock(&irq_controller_lock);
Yinghai Lud5dedd42009-04-27 17:59:21 -0700156
157 return 0;
Russell Kingf27ecac2005-08-18 21:31:00 +0100158}
Catalin Marinasa06f5462005-09-30 16:07:05 +0100159#endif
Russell Kingf27ecac2005-08-18 21:31:00 +0100160
Russell King0f347bb2007-05-17 10:11:34 +0100161static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100162{
163 struct gic_chip_data *chip_data = get_irq_data(irq);
164 struct irq_chip *chip = get_irq_chip(irq);
Russell King0f347bb2007-05-17 10:11:34 +0100165 unsigned int cascade_irq, gic_irq;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100166 unsigned long status;
167
168 /* primary controller ack'ing */
169 chip->ack(irq);
170
171 spin_lock(&irq_controller_lock);
172 status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
173 spin_unlock(&irq_controller_lock);
174
Russell King0f347bb2007-05-17 10:11:34 +0100175 gic_irq = (status & 0x3ff);
176 if (gic_irq == 1023)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100177 goto out;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100178
Russell King0f347bb2007-05-17 10:11:34 +0100179 cascade_irq = gic_irq + chip_data->irq_offset;
180 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
181 do_bad_IRQ(cascade_irq, desc);
182 else
183 generic_handle_irq(cascade_irq);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100184
185 out:
186 /* primary controller unmasking */
187 chip->unmask(irq);
188}
189
David Brownell38c677c2006-08-01 22:26:25 +0100190static struct irq_chip gic_chip = {
191 .name = "GIC",
Russell Kingf27ecac2005-08-18 21:31:00 +0100192 .ack = gic_ack_irq,
193 .mask = gic_mask_irq,
194 .unmask = gic_unmask_irq,
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100195 .set_type = gic_set_type,
Russell Kingf27ecac2005-08-18 21:31:00 +0100196#ifdef CONFIG_SMP
Thomas Gleixnerc4bfa282006-07-01 22:32:14 +0100197 .set_affinity = gic_set_cpu,
Russell Kingf27ecac2005-08-18 21:31:00 +0100198#endif
199};
200
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100201void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
202{
203 if (gic_nr >= MAX_GIC_NR)
204 BUG();
205 if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
206 BUG();
207 set_irq_chained_handler(irq, gic_handle_cascade_irq);
208}
209
210void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
211 unsigned int irq_start)
Russell Kingf27ecac2005-08-18 21:31:00 +0100212{
213 unsigned int max_irq, i;
214 u32 cpumask = 1 << smp_processor_id();
215
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100216 if (gic_nr >= MAX_GIC_NR)
217 BUG();
218
Russell Kingf27ecac2005-08-18 21:31:00 +0100219 cpumask |= cpumask << 8;
220 cpumask |= cpumask << 16;
221
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100222 gic_data[gic_nr].dist_base = base;
223 gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
Russell Kingf27ecac2005-08-18 21:31:00 +0100224
225 writel(0, base + GIC_DIST_CTRL);
226
227 /*
228 * Find out how many interrupts are supported.
229 */
230 max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
231 max_irq = (max_irq + 1) * 32;
232
233 /*
234 * The GIC only supports up to 1020 interrupt sources.
235 * Limit this to either the architected maximum, or the
236 * platform maximum.
237 */
238 if (max_irq > max(1020, NR_IRQS))
239 max_irq = max(1020, NR_IRQS);
240
241 /*
242 * Set all global interrupts to be level triggered, active low.
243 */
244 for (i = 32; i < max_irq; i += 16)
245 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
246
247 /*
248 * Set all global interrupts to this CPU only.
249 */
250 for (i = 32; i < max_irq; i += 4)
251 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
252
253 /*
Russell King9395f6e2010-11-11 23:10:30 +0000254 * Set priority on all global interrupts.
Russell Kingf27ecac2005-08-18 21:31:00 +0100255 */
Russell King9395f6e2010-11-11 23:10:30 +0000256 for (i = 32; i < max_irq; i += 4)
Russell Kingf27ecac2005-08-18 21:31:00 +0100257 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
258
259 /*
Russell King9395f6e2010-11-11 23:10:30 +0000260 * Disable all interrupts. Leave the PPI and SGIs alone
261 * as these enables are banked registers.
Russell Kingf27ecac2005-08-18 21:31:00 +0100262 */
Russell King9395f6e2010-11-11 23:10:30 +0000263 for (i = 32; i < max_irq; i += 32)
Russell Kingf27ecac2005-08-18 21:31:00 +0100264 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
265
266 /*
267 * Setup the Linux IRQ subsystem.
268 */
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100269 for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
Russell Kingf27ecac2005-08-18 21:31:00 +0100270 set_irq_chip(i, &gic_chip);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100271 set_irq_chip_data(i, &gic_data[gic_nr]);
Russell King10dd5ce2006-11-23 11:41:32 +0000272 set_irq_handler(i, handle_level_irq);
Russell Kingf27ecac2005-08-18 21:31:00 +0100273 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
274 }
275
276 writel(1, base + GIC_DIST_CTRL);
277}
278
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100279void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
Russell Kingf27ecac2005-08-18 21:31:00 +0100280{
Russell King9395f6e2010-11-11 23:10:30 +0000281 void __iomem *dist_base;
282 int i;
283
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100284 if (gic_nr >= MAX_GIC_NR)
285 BUG();
286
Russell King9395f6e2010-11-11 23:10:30 +0000287 dist_base = gic_data[gic_nr].dist_base;
288 BUG_ON(!dist_base);
289
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100290 gic_data[gic_nr].cpu_base = base;
291
Russell King9395f6e2010-11-11 23:10:30 +0000292 /*
293 * Deal with the banked PPI and SGI interrupts - disable all
294 * PPI interrupts, ensure all SGI interrupts are enabled.
295 */
296 writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
297 writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
298
299 /*
300 * Set priority on PPI and SGI interrupts
301 */
302 for (i = 0; i < 32; i += 4)
303 writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
304
Russell Kingf27ecac2005-08-18 21:31:00 +0100305 writel(0xf0, base + GIC_CPU_PRIMASK);
306 writel(1, base + GIC_CPU_CTRL);
307}
308
309#ifdef CONFIG_SMP
Russell King82668102009-05-17 16:20:18 +0100310void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
Russell Kingf27ecac2005-08-18 21:31:00 +0100311{
Russell King82668102009-05-17 16:20:18 +0100312 unsigned long map = *cpus_addr(*mask);
Russell Kingf27ecac2005-08-18 21:31:00 +0100313
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100314 /* this always happens on GIC0 */
315 writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
Russell Kingf27ecac2005-08-18 21:31:00 +0100316}
317#endif