Tim Kryger | 93d1724 | 2013-11-14 13:02:13 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2013 Broadcom Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation version 2. |
| 7 | * |
| 8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 9 | * kind, whether express or implied; without even the implied warranty |
| 10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/device.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/sched.h> |
| 18 | #include <linux/i2c.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/slab.h> |
| 25 | |
| 26 | /* Hardware register offsets and field defintions */ |
| 27 | #define CS_OFFSET 0x00000020 |
| 28 | #define CS_ACK_SHIFT 3 |
| 29 | #define CS_ACK_MASK 0x00000008 |
| 30 | #define CS_ACK_CMD_GEN_START 0x00000000 |
| 31 | #define CS_ACK_CMD_GEN_RESTART 0x00000001 |
| 32 | #define CS_CMD_SHIFT 1 |
| 33 | #define CS_CMD_CMD_NO_ACTION 0x00000000 |
| 34 | #define CS_CMD_CMD_START_RESTART 0x00000001 |
| 35 | #define CS_CMD_CMD_STOP 0x00000002 |
| 36 | #define CS_EN_SHIFT 0 |
| 37 | #define CS_EN_CMD_ENABLE_BSC 0x00000001 |
| 38 | |
| 39 | #define TIM_OFFSET 0x00000024 |
| 40 | #define TIM_PRESCALE_SHIFT 6 |
| 41 | #define TIM_P_SHIFT 3 |
| 42 | #define TIM_NO_DIV_SHIFT 2 |
| 43 | #define TIM_DIV_SHIFT 0 |
| 44 | |
| 45 | #define DAT_OFFSET 0x00000028 |
| 46 | |
| 47 | #define TOUT_OFFSET 0x0000002c |
| 48 | |
| 49 | #define TXFCR_OFFSET 0x0000003c |
| 50 | #define TXFCR_FIFO_FLUSH_MASK 0x00000080 |
| 51 | #define TXFCR_FIFO_EN_MASK 0x00000040 |
| 52 | |
| 53 | #define IER_OFFSET 0x00000044 |
| 54 | #define IER_READ_COMPLETE_INT_MASK 0x00000010 |
| 55 | #define IER_I2C_INT_EN_MASK 0x00000008 |
| 56 | #define IER_FIFO_INT_EN_MASK 0x00000002 |
| 57 | #define IER_NOACK_EN_MASK 0x00000001 |
| 58 | |
| 59 | #define ISR_OFFSET 0x00000048 |
| 60 | #define ISR_RESERVED_MASK 0xffffff60 |
| 61 | #define ISR_CMDBUSY_MASK 0x00000080 |
| 62 | #define ISR_READ_COMPLETE_MASK 0x00000010 |
| 63 | #define ISR_SES_DONE_MASK 0x00000008 |
| 64 | #define ISR_ERR_MASK 0x00000004 |
| 65 | #define ISR_TXFIFOEMPTY_MASK 0x00000002 |
| 66 | #define ISR_NOACK_MASK 0x00000001 |
| 67 | |
| 68 | #define CLKEN_OFFSET 0x0000004C |
| 69 | #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 |
| 70 | #define CLKEN_M_SHIFT 4 |
| 71 | #define CLKEN_N_SHIFT 1 |
| 72 | #define CLKEN_CLKEN_MASK 0x00000001 |
| 73 | |
| 74 | #define FIFO_STATUS_OFFSET 0x00000054 |
| 75 | #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 |
| 76 | #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 |
| 77 | |
| 78 | #define HSTIM_OFFSET 0x00000058 |
| 79 | #define HSTIM_HS_MODE_MASK 0x00008000 |
| 80 | #define HSTIM_HS_HOLD_SHIFT 10 |
| 81 | #define HSTIM_HS_HIGH_PHASE_SHIFT 5 |
| 82 | #define HSTIM_HS_SETUP_SHIFT 0 |
| 83 | |
| 84 | #define PADCTL_OFFSET 0x0000005c |
| 85 | #define PADCTL_PAD_OUT_EN_MASK 0x00000004 |
| 86 | |
| 87 | #define RXFCR_OFFSET 0x00000068 |
| 88 | #define RXFCR_NACK_EN_SHIFT 7 |
| 89 | #define RXFCR_READ_COUNT_SHIFT 0 |
| 90 | #define RXFIFORDOUT_OFFSET 0x0000006c |
| 91 | |
| 92 | /* Locally used constants */ |
| 93 | #define MAX_RX_FIFO_SIZE 64U /* bytes */ |
| 94 | #define MAX_TX_FIFO_SIZE 64U /* bytes */ |
| 95 | |
| 96 | #define STD_EXT_CLK_FREQ 13000000UL |
| 97 | #define HS_EXT_CLK_FREQ 104000000UL |
| 98 | |
| 99 | #define MASTERCODE 0x08 /* Mastercodes are 0000_1xxxb */ |
| 100 | |
| 101 | #define I2C_TIMEOUT 100 /* msecs */ |
| 102 | |
| 103 | /* Operations that can be commanded to the controller */ |
| 104 | enum bcm_kona_cmd_t { |
| 105 | BCM_CMD_NOACTION = 0, |
| 106 | BCM_CMD_START, |
| 107 | BCM_CMD_RESTART, |
| 108 | BCM_CMD_STOP, |
| 109 | }; |
| 110 | |
| 111 | enum bus_speed_index { |
| 112 | BCM_SPD_100K = 0, |
| 113 | BCM_SPD_400K, |
| 114 | BCM_SPD_1MHZ, |
| 115 | }; |
| 116 | |
| 117 | enum hs_bus_speed_index { |
| 118 | BCM_SPD_3P4MHZ = 0, |
| 119 | }; |
| 120 | |
| 121 | /* Internal divider settings for standard mode, fast mode and fast mode plus */ |
| 122 | struct bus_speed_cfg { |
| 123 | uint8_t time_m; /* Number of cycles for setup time */ |
| 124 | uint8_t time_n; /* Number of cycles for hold time */ |
| 125 | uint8_t prescale; /* Prescale divider */ |
| 126 | uint8_t time_p; /* Timing coefficient */ |
| 127 | uint8_t no_div; /* Disable clock divider */ |
| 128 | uint8_t time_div; /* Post-prescale divider */ |
| 129 | }; |
| 130 | |
| 131 | /* Internal divider settings for high-speed mode */ |
| 132 | struct hs_bus_speed_cfg { |
| 133 | uint8_t hs_hold; /* Number of clock cycles SCL stays low until |
| 134 | the end of bit period */ |
| 135 | uint8_t hs_high_phase; /* Number of clock cycles SCL stays high |
| 136 | before it falls */ |
| 137 | uint8_t hs_setup; /* Number of clock cycles SCL stays low |
| 138 | before it rises */ |
| 139 | uint8_t prescale; /* Prescale divider */ |
| 140 | uint8_t time_p; /* Timing coefficient */ |
| 141 | uint8_t no_div; /* Disable clock divider */ |
| 142 | uint8_t time_div; /* Post-prescale divider */ |
| 143 | }; |
| 144 | |
| 145 | static const struct bus_speed_cfg std_cfg_table[] = { |
| 146 | [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, |
| 147 | [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, |
| 148 | [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, |
| 149 | }; |
| 150 | |
| 151 | static const struct hs_bus_speed_cfg hs_cfg_table[] = { |
| 152 | [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00}, |
| 153 | }; |
| 154 | |
| 155 | struct bcm_kona_i2c_dev { |
| 156 | struct device *device; |
| 157 | |
| 158 | void __iomem *base; |
| 159 | int irq; |
| 160 | struct clk *external_clk; |
| 161 | |
| 162 | struct i2c_adapter adapter; |
| 163 | |
| 164 | struct completion done; |
| 165 | |
| 166 | const struct bus_speed_cfg *std_cfg; |
| 167 | const struct hs_bus_speed_cfg *hs_cfg; |
| 168 | }; |
| 169 | |
| 170 | static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, |
| 171 | enum bcm_kona_cmd_t cmd) |
| 172 | { |
| 173 | dev_dbg(dev->device, "%s, %d\n", __func__, cmd); |
| 174 | |
| 175 | switch (cmd) { |
| 176 | case BCM_CMD_NOACTION: |
| 177 | writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | |
| 178 | (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), |
| 179 | dev->base + CS_OFFSET); |
| 180 | break; |
| 181 | |
| 182 | case BCM_CMD_START: |
| 183 | writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | |
| 184 | (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | |
| 185 | (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), |
| 186 | dev->base + CS_OFFSET); |
| 187 | break; |
| 188 | |
| 189 | case BCM_CMD_RESTART: |
| 190 | writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | |
| 191 | (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | |
| 192 | (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), |
| 193 | dev->base + CS_OFFSET); |
| 194 | break; |
| 195 | |
| 196 | case BCM_CMD_STOP: |
| 197 | writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | |
| 198 | (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), |
| 199 | dev->base + CS_OFFSET); |
| 200 | break; |
| 201 | |
| 202 | default: |
| 203 | dev_err(dev->device, "Unknown command %d\n", cmd); |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) |
| 208 | { |
| 209 | writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, |
| 210 | dev->base + CLKEN_OFFSET); |
| 211 | } |
| 212 | |
| 213 | static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) |
| 214 | { |
| 215 | writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, |
| 216 | dev->base + CLKEN_OFFSET); |
| 217 | } |
| 218 | |
| 219 | static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid) |
| 220 | { |
| 221 | struct bcm_kona_i2c_dev *dev = devid; |
| 222 | uint32_t status = readl(dev->base + ISR_OFFSET); |
| 223 | |
| 224 | if ((status & ~ISR_RESERVED_MASK) == 0) |
| 225 | return IRQ_NONE; |
| 226 | |
| 227 | /* Must flush the TX FIFO when NAK detected */ |
| 228 | if (status & ISR_NOACK_MASK) |
| 229 | writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, |
| 230 | dev->base + TXFCR_OFFSET); |
| 231 | |
| 232 | writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); |
| 233 | complete_all(&dev->done); |
| 234 | |
| 235 | return IRQ_HANDLED; |
| 236 | } |
| 237 | |
| 238 | /* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */ |
| 239 | static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev) |
| 240 | { |
| 241 | unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); |
| 242 | |
| 243 | while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK) |
| 244 | if (time_after(jiffies, timeout)) { |
| 245 | dev_err(dev->device, "CMDBUSY timeout\n"); |
| 246 | return -ETIMEDOUT; |
| 247 | } |
| 248 | |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | /* Send command to I2C bus */ |
| 253 | static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, |
| 254 | enum bcm_kona_cmd_t cmd) |
| 255 | { |
| 256 | int rc; |
| 257 | unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); |
| 258 | |
| 259 | /* Make sure the hardware is ready */ |
| 260 | rc = bcm_kona_i2c_wait_if_busy(dev); |
| 261 | if (rc < 0) |
| 262 | return rc; |
| 263 | |
| 264 | /* Unmask the session done interrupt */ |
| 265 | writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); |
| 266 | |
| 267 | /* Mark as incomplete before sending the command */ |
| 268 | INIT_COMPLETION(dev->done); |
| 269 | |
| 270 | /* Send the command */ |
| 271 | bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); |
| 272 | |
| 273 | /* Wait for transaction to finish or timeout */ |
| 274 | time_left = wait_for_completion_timeout(&dev->done, time_left); |
| 275 | |
| 276 | /* Mask all interrupts */ |
| 277 | writel(0, dev->base + IER_OFFSET); |
| 278 | |
| 279 | if (!time_left) { |
| 280 | dev_err(dev->device, "controller timed out\n"); |
| 281 | rc = -ETIMEDOUT; |
| 282 | } |
| 283 | |
| 284 | /* Clear command */ |
| 285 | bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); |
| 286 | |
| 287 | return rc; |
| 288 | } |
| 289 | |
| 290 | /* Read a single RX FIFO worth of data from the i2c bus */ |
| 291 | static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, |
| 292 | uint8_t *buf, unsigned int len, |
| 293 | unsigned int last_byte_nak) |
| 294 | { |
| 295 | unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); |
| 296 | |
| 297 | /* Mark as incomplete before starting the RX FIFO */ |
| 298 | INIT_COMPLETION(dev->done); |
| 299 | |
| 300 | /* Unmask the read complete interrupt */ |
| 301 | writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET); |
| 302 | |
| 303 | /* Start the RX FIFO */ |
| 304 | writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | |
| 305 | (len << RXFCR_READ_COUNT_SHIFT), |
| 306 | dev->base + RXFCR_OFFSET); |
| 307 | |
| 308 | /* Wait for FIFO read to complete */ |
| 309 | time_left = wait_for_completion_timeout(&dev->done, time_left); |
| 310 | |
| 311 | /* Mask all interrupts */ |
| 312 | writel(0, dev->base + IER_OFFSET); |
| 313 | |
| 314 | if (!time_left) { |
| 315 | dev_err(dev->device, "RX FIFO time out\n"); |
| 316 | return -EREMOTEIO; |
| 317 | } |
| 318 | |
| 319 | /* Read data from FIFO */ |
| 320 | for (; len > 0; len--, buf++) |
| 321 | *buf = readl(dev->base + RXFIFORDOUT_OFFSET); |
| 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | /* Read any amount of data using the RX FIFO from the i2c bus */ |
| 327 | static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, |
| 328 | struct i2c_msg *msg) |
| 329 | { |
| 330 | unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; |
| 331 | unsigned int last_byte_nak = 0; |
| 332 | unsigned int bytes_read = 0; |
| 333 | int rc; |
| 334 | |
| 335 | uint8_t *tmp_buf = msg->buf; |
| 336 | |
| 337 | while (bytes_read < msg->len) { |
| 338 | if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { |
| 339 | last_byte_nak = 1; /* NAK last byte of transfer */ |
| 340 | bytes_to_read = msg->len - bytes_read; |
| 341 | } |
| 342 | |
| 343 | rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, |
| 344 | last_byte_nak); |
| 345 | if (rc < 0) |
| 346 | return -EREMOTEIO; |
| 347 | |
| 348 | bytes_read += bytes_to_read; |
| 349 | tmp_buf += bytes_to_read; |
| 350 | } |
| 351 | |
| 352 | return 0; |
| 353 | } |
| 354 | |
| 355 | /* Write a single byte of data to the i2c bus */ |
| 356 | static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, |
| 357 | unsigned int nak_expected) |
| 358 | { |
| 359 | int rc; |
| 360 | unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); |
| 361 | unsigned int nak_received; |
| 362 | |
| 363 | /* Make sure the hardware is ready */ |
| 364 | rc = bcm_kona_i2c_wait_if_busy(dev); |
| 365 | if (rc < 0) |
| 366 | return rc; |
| 367 | |
| 368 | /* Clear pending session done interrupt */ |
| 369 | writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); |
| 370 | |
| 371 | /* Unmask the session done interrupt */ |
| 372 | writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); |
| 373 | |
| 374 | /* Mark as incomplete before sending the data */ |
| 375 | INIT_COMPLETION(dev->done); |
| 376 | |
| 377 | /* Send one byte of data */ |
| 378 | writel(data, dev->base + DAT_OFFSET); |
| 379 | |
| 380 | /* Wait for byte to be written */ |
| 381 | time_left = wait_for_completion_timeout(&dev->done, time_left); |
| 382 | |
| 383 | /* Mask all interrupts */ |
| 384 | writel(0, dev->base + IER_OFFSET); |
| 385 | |
| 386 | if (!time_left) { |
| 387 | dev_dbg(dev->device, "controller timed out\n"); |
| 388 | return -ETIMEDOUT; |
| 389 | } |
| 390 | |
| 391 | nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; |
| 392 | |
| 393 | if (nak_received ^ nak_expected) { |
| 394 | dev_dbg(dev->device, "unexpected NAK/ACK\n"); |
| 395 | return -EREMOTEIO; |
| 396 | } |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | /* Write a single TX FIFO worth of data to the i2c bus */ |
| 402 | static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, |
| 403 | uint8_t *buf, unsigned int len) |
| 404 | { |
| 405 | int k; |
| 406 | unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); |
| 407 | unsigned int fifo_status; |
| 408 | |
| 409 | /* Mark as incomplete before sending data to the TX FIFO */ |
| 410 | INIT_COMPLETION(dev->done); |
| 411 | |
| 412 | /* Unmask the fifo empty and nak interrupt */ |
| 413 | writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK, |
| 414 | dev->base + IER_OFFSET); |
| 415 | |
| 416 | /* Disable IRQ to load a FIFO worth of data without interruption */ |
| 417 | disable_irq(dev->irq); |
| 418 | |
| 419 | /* Write data into FIFO */ |
| 420 | for (k = 0; k < len; k++) |
| 421 | writel(buf[k], (dev->base + DAT_OFFSET)); |
| 422 | |
| 423 | /* Enable IRQ now that data has been loaded */ |
| 424 | enable_irq(dev->irq); |
| 425 | |
| 426 | /* Wait for FIFO to empty */ |
| 427 | do { |
| 428 | time_left = wait_for_completion_timeout(&dev->done, time_left); |
| 429 | fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); |
| 430 | } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); |
| 431 | |
| 432 | /* Mask all interrupts */ |
| 433 | writel(0, dev->base + IER_OFFSET); |
| 434 | |
| 435 | /* Check if there was a NAK */ |
| 436 | if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { |
| 437 | dev_err(dev->device, "unexpected NAK\n"); |
| 438 | return -EREMOTEIO; |
| 439 | } |
| 440 | |
| 441 | /* Check if a timeout occured */ |
| 442 | if (!time_left) { |
| 443 | dev_err(dev->device, "completion timed out\n"); |
| 444 | return -EREMOTEIO; |
| 445 | } |
| 446 | |
| 447 | return 0; |
| 448 | } |
| 449 | |
| 450 | |
| 451 | /* Write any amount of data using TX FIFO to the i2c bus */ |
| 452 | static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, |
| 453 | struct i2c_msg *msg) |
| 454 | { |
| 455 | unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; |
| 456 | unsigned int bytes_written = 0; |
| 457 | int rc; |
| 458 | |
| 459 | uint8_t *tmp_buf = msg->buf; |
| 460 | |
| 461 | while (bytes_written < msg->len) { |
| 462 | if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) |
| 463 | bytes_to_write = msg->len - bytes_written; |
| 464 | |
| 465 | rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, |
| 466 | bytes_to_write); |
| 467 | if (rc < 0) |
| 468 | return -EREMOTEIO; |
| 469 | |
| 470 | bytes_written += bytes_to_write; |
| 471 | tmp_buf += bytes_to_write; |
| 472 | } |
| 473 | |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | /* Send i2c address */ |
| 478 | static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, |
| 479 | struct i2c_msg *msg) |
| 480 | { |
| 481 | unsigned char addr; |
| 482 | |
| 483 | if (msg->flags & I2C_M_TEN) { |
| 484 | /* First byte is 11110XX0 where XX is upper 2 bits */ |
| 485 | addr = 0xF0 | ((msg->addr & 0x300) >> 7); |
| 486 | if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) |
| 487 | return -EREMOTEIO; |
| 488 | |
| 489 | /* Second byte is the remaining 8 bits */ |
| 490 | addr = msg->addr & 0xFF; |
| 491 | if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) |
| 492 | return -EREMOTEIO; |
| 493 | |
| 494 | if (msg->flags & I2C_M_RD) { |
| 495 | /* For read, send restart command */ |
| 496 | if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) |
| 497 | return -EREMOTEIO; |
| 498 | |
| 499 | /* Then re-send the first byte with the read bit set */ |
| 500 | addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; |
| 501 | if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) |
| 502 | return -EREMOTEIO; |
| 503 | } |
| 504 | } else { |
| 505 | addr = msg->addr << 1; |
| 506 | |
| 507 | if (msg->flags & I2C_M_RD) |
| 508 | addr |= 1; |
| 509 | |
| 510 | if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) |
| 511 | return -EREMOTEIO; |
| 512 | } |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
| 517 | static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) |
| 518 | { |
| 519 | writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, |
| 520 | dev->base + CLKEN_OFFSET); |
| 521 | } |
| 522 | |
| 523 | static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) |
| 524 | { |
| 525 | writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, |
| 526 | dev->base + HSTIM_OFFSET); |
| 527 | |
| 528 | writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | |
| 529 | (dev->std_cfg->time_p << TIM_P_SHIFT) | |
| 530 | (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | |
| 531 | (dev->std_cfg->time_div << TIM_DIV_SHIFT), |
| 532 | dev->base + TIM_OFFSET); |
| 533 | |
| 534 | writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | |
| 535 | (dev->std_cfg->time_n << CLKEN_N_SHIFT) | |
| 536 | CLKEN_CLKEN_MASK, |
| 537 | dev->base + CLKEN_OFFSET); |
| 538 | } |
| 539 | |
| 540 | static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev) |
| 541 | { |
| 542 | writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) | |
| 543 | (dev->hs_cfg->time_p << TIM_P_SHIFT) | |
| 544 | (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) | |
| 545 | (dev->hs_cfg->time_div << TIM_DIV_SHIFT), |
| 546 | dev->base + TIM_OFFSET); |
| 547 | |
| 548 | writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) | |
| 549 | (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) | |
| 550 | (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT), |
| 551 | dev->base + HSTIM_OFFSET); |
| 552 | |
| 553 | writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK, |
| 554 | dev->base + HSTIM_OFFSET); |
| 555 | } |
| 556 | |
| 557 | static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev) |
| 558 | { |
| 559 | int rc; |
| 560 | |
| 561 | /* Send mastercode at standard speed */ |
| 562 | rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1); |
| 563 | if (rc < 0) { |
| 564 | pr_err("High speed handshake failed\n"); |
| 565 | return rc; |
| 566 | } |
| 567 | |
| 568 | /* Configure external clock to higher frequency */ |
| 569 | rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ); |
| 570 | if (rc) { |
| 571 | dev_err(dev->device, "%s: clk_set_rate returned %d\n", |
| 572 | __func__, rc); |
| 573 | return rc; |
| 574 | } |
| 575 | |
| 576 | /* Reconfigure internal dividers */ |
| 577 | bcm_kona_i2c_config_timing_hs(dev); |
| 578 | |
| 579 | /* Send a restart command */ |
| 580 | rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); |
| 581 | if (rc < 0) |
| 582 | dev_err(dev->device, "High speed restart command failed\n"); |
| 583 | |
| 584 | return rc; |
| 585 | } |
| 586 | |
| 587 | static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev) |
| 588 | { |
| 589 | int rc; |
| 590 | |
| 591 | /* Reconfigure internal dividers */ |
| 592 | bcm_kona_i2c_config_timing(dev); |
| 593 | |
| 594 | /* Configure external clock to lower frequency */ |
| 595 | rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); |
| 596 | if (rc) { |
| 597 | dev_err(dev->device, "%s: clk_set_rate returned %d\n", |
| 598 | __func__, rc); |
| 599 | } |
| 600 | |
| 601 | return rc; |
| 602 | } |
| 603 | |
| 604 | /* Master transfer function */ |
| 605 | static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter, |
| 606 | struct i2c_msg msgs[], int num) |
| 607 | { |
| 608 | struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter); |
| 609 | struct i2c_msg *pmsg; |
| 610 | int rc = 0; |
| 611 | int i; |
| 612 | |
| 613 | rc = clk_prepare_enable(dev->external_clk); |
| 614 | if (rc) { |
| 615 | dev_err(dev->device, "%s: peri clock enable failed. err %d\n", |
| 616 | __func__, rc); |
| 617 | return rc; |
| 618 | } |
| 619 | |
| 620 | /* Enable pad output */ |
| 621 | writel(0, dev->base + PADCTL_OFFSET); |
| 622 | |
| 623 | /* Enable internal clocks */ |
| 624 | bcm_kona_i2c_enable_clock(dev); |
| 625 | |
| 626 | /* Send start command */ |
| 627 | rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); |
| 628 | if (rc < 0) { |
| 629 | dev_err(dev->device, "Start command failed rc = %d\n", rc); |
| 630 | goto xfer_disable_pad; |
| 631 | } |
| 632 | |
| 633 | /* Switch to high speed if applicable */ |
| 634 | if (dev->hs_cfg) { |
| 635 | rc = bcm_kona_i2c_switch_to_hs(dev); |
| 636 | if (rc < 0) |
| 637 | goto xfer_send_stop; |
| 638 | } |
| 639 | |
| 640 | /* Loop through all messages */ |
| 641 | for (i = 0; i < num; i++) { |
| 642 | pmsg = &msgs[i]; |
| 643 | |
| 644 | /* Send restart for subsequent messages */ |
| 645 | if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { |
| 646 | rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); |
| 647 | if (rc < 0) { |
| 648 | dev_err(dev->device, |
| 649 | "restart cmd failed rc = %d\n", rc); |
| 650 | goto xfer_send_stop; |
| 651 | } |
| 652 | } |
| 653 | |
| 654 | /* Send slave address */ |
| 655 | if (!(pmsg->flags & I2C_M_NOSTART)) { |
| 656 | rc = bcm_kona_i2c_do_addr(dev, pmsg); |
| 657 | if (rc < 0) { |
| 658 | dev_err(dev->device, |
| 659 | "NAK from addr %2.2x msg#%d rc = %d\n", |
| 660 | pmsg->addr, i, rc); |
| 661 | goto xfer_send_stop; |
| 662 | } |
| 663 | } |
| 664 | |
| 665 | /* Perform data transfer */ |
| 666 | if (pmsg->flags & I2C_M_RD) { |
| 667 | rc = bcm_kona_i2c_read_fifo(dev, pmsg); |
| 668 | if (rc < 0) { |
| 669 | dev_err(dev->device, "read failure\n"); |
| 670 | goto xfer_send_stop; |
| 671 | } |
| 672 | } else { |
| 673 | rc = bcm_kona_i2c_write_fifo(dev, pmsg); |
| 674 | if (rc < 0) { |
| 675 | dev_err(dev->device, "write failure"); |
| 676 | goto xfer_send_stop; |
| 677 | } |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | rc = num; |
| 682 | |
| 683 | xfer_send_stop: |
| 684 | /* Send a STOP command */ |
| 685 | bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); |
| 686 | |
| 687 | /* Return from high speed if applicable */ |
| 688 | if (dev->hs_cfg) { |
| 689 | int hs_rc = bcm_kona_i2c_switch_to_std(dev); |
| 690 | |
| 691 | if (hs_rc) |
| 692 | rc = hs_rc; |
| 693 | } |
| 694 | |
| 695 | xfer_disable_pad: |
| 696 | /* Disable pad output */ |
| 697 | writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); |
| 698 | |
| 699 | /* Stop internal clock */ |
| 700 | bcm_kona_i2c_disable_clock(dev); |
| 701 | |
| 702 | clk_disable_unprepare(dev->external_clk); |
| 703 | |
| 704 | return rc; |
| 705 | } |
| 706 | |
| 707 | static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap) |
| 708 | { |
| 709 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | |
| 710 | I2C_FUNC_NOSTART; |
| 711 | } |
| 712 | |
| 713 | static const struct i2c_algorithm bcm_algo = { |
| 714 | .master_xfer = bcm_kona_i2c_xfer, |
| 715 | .functionality = bcm_kona_i2c_functionality, |
| 716 | }; |
| 717 | |
| 718 | static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev) |
| 719 | { |
| 720 | unsigned int bus_speed; |
| 721 | int ret = of_property_read_u32(dev->device->of_node, "clock-frequency", |
| 722 | &bus_speed); |
| 723 | if (ret < 0) { |
| 724 | dev_err(dev->device, "missing clock-frequency property\n"); |
| 725 | return -ENODEV; |
| 726 | } |
| 727 | |
| 728 | switch (bus_speed) { |
| 729 | case 100000: |
| 730 | dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; |
| 731 | break; |
| 732 | case 400000: |
| 733 | dev->std_cfg = &std_cfg_table[BCM_SPD_400K]; |
| 734 | break; |
| 735 | case 1000000: |
| 736 | dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ]; |
| 737 | break; |
| 738 | case 3400000: |
| 739 | /* Send mastercode at 100k */ |
| 740 | dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; |
| 741 | dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ]; |
| 742 | break; |
| 743 | default: |
| 744 | pr_err("%d hz bus speed not supported\n", bus_speed); |
| 745 | pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n"); |
| 746 | return -EINVAL; |
| 747 | } |
| 748 | |
| 749 | return 0; |
| 750 | } |
| 751 | |
| 752 | static int bcm_kona_i2c_probe(struct platform_device *pdev) |
| 753 | { |
| 754 | int rc = 0; |
| 755 | struct bcm_kona_i2c_dev *dev; |
| 756 | struct i2c_adapter *adap; |
| 757 | struct resource *iomem; |
| 758 | |
| 759 | /* Allocate memory for private data structure */ |
| 760 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
| 761 | if (!dev) |
| 762 | return -ENOMEM; |
| 763 | |
| 764 | platform_set_drvdata(pdev, dev); |
| 765 | dev->device = &pdev->dev; |
| 766 | init_completion(&dev->done); |
| 767 | |
| 768 | /* Map hardware registers */ |
| 769 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 770 | dev->base = devm_ioremap_resource(dev->device, iomem); |
| 771 | if (IS_ERR(dev->base)) |
| 772 | return -ENOMEM; |
| 773 | |
| 774 | /* Get and enable external clock */ |
| 775 | dev->external_clk = devm_clk_get(dev->device, NULL); |
| 776 | if (IS_ERR(dev->external_clk)) { |
| 777 | dev_err(dev->device, "couldn't get clock\n"); |
| 778 | return -ENODEV; |
| 779 | } |
| 780 | |
| 781 | rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); |
| 782 | if (rc) { |
| 783 | dev_err(dev->device, "%s: clk_set_rate returned %d\n", |
| 784 | __func__, rc); |
| 785 | return rc; |
| 786 | } |
| 787 | |
| 788 | rc = clk_prepare_enable(dev->external_clk); |
| 789 | if (rc) { |
| 790 | dev_err(dev->device, "couldn't enable clock\n"); |
| 791 | return rc; |
| 792 | } |
| 793 | |
| 794 | /* Parse bus speed */ |
| 795 | if (bcm_kona_i2c_assign_bus_speed(dev)) |
| 796 | goto probe_disable_clk; |
| 797 | |
| 798 | /* Enable internal clocks */ |
| 799 | bcm_kona_i2c_enable_clock(dev); |
| 800 | |
| 801 | /* Configure internal dividers */ |
| 802 | bcm_kona_i2c_config_timing(dev); |
| 803 | |
| 804 | /* Disable timeout */ |
| 805 | writel(0, dev->base + TOUT_OFFSET); |
| 806 | |
| 807 | /* Enable autosense */ |
| 808 | bcm_kona_i2c_enable_autosense(dev); |
| 809 | |
| 810 | /* Enable TX FIFO */ |
| 811 | writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, |
| 812 | dev->base + TXFCR_OFFSET); |
| 813 | |
| 814 | /* Mask all interrupts */ |
| 815 | writel(0, dev->base + IER_OFFSET); |
| 816 | |
| 817 | /* Clear all pending interrupts */ |
| 818 | writel(ISR_CMDBUSY_MASK | |
| 819 | ISR_READ_COMPLETE_MASK | |
| 820 | ISR_SES_DONE_MASK | |
| 821 | ISR_ERR_MASK | |
| 822 | ISR_TXFIFOEMPTY_MASK | |
| 823 | ISR_NOACK_MASK, |
| 824 | dev->base + ISR_OFFSET); |
| 825 | |
| 826 | /* Get the interrupt number */ |
| 827 | dev->irq = platform_get_irq(pdev, 0); |
| 828 | if (dev->irq < 0) { |
| 829 | dev_err(dev->device, "no irq resource\n"); |
| 830 | rc = -ENODEV; |
| 831 | goto probe_disable_clk; |
| 832 | } |
| 833 | |
| 834 | /* register the ISR handler */ |
| 835 | rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr, |
| 836 | IRQF_SHARED, pdev->name, dev); |
| 837 | if (rc) { |
| 838 | dev_err(dev->device, "failed to request irq %i\n", dev->irq); |
| 839 | goto probe_disable_clk; |
| 840 | } |
| 841 | |
| 842 | /* Enable the controller but leave it idle */ |
| 843 | bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); |
| 844 | |
| 845 | /* Disable pad output */ |
| 846 | writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); |
| 847 | |
| 848 | /* Disable internal clock */ |
| 849 | bcm_kona_i2c_disable_clock(dev); |
| 850 | |
| 851 | /* Disable external clock */ |
| 852 | clk_disable_unprepare(dev->external_clk); |
| 853 | |
| 854 | /* Add the i2c adapter */ |
| 855 | adap = &dev->adapter; |
| 856 | i2c_set_adapdata(adap, dev); |
| 857 | adap->owner = THIS_MODULE; |
| 858 | strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); |
| 859 | adap->algo = &bcm_algo; |
| 860 | adap->dev.parent = &pdev->dev; |
| 861 | adap->dev.of_node = pdev->dev.of_node; |
| 862 | |
| 863 | rc = i2c_add_adapter(adap); |
| 864 | if (rc) { |
| 865 | dev_err(dev->device, "failed to add adapter\n"); |
| 866 | return rc; |
| 867 | } |
| 868 | |
| 869 | dev_info(dev->device, "device registered successfully\n"); |
| 870 | |
| 871 | return 0; |
| 872 | |
| 873 | probe_disable_clk: |
| 874 | bcm_kona_i2c_disable_clock(dev); |
| 875 | clk_disable_unprepare(dev->external_clk); |
| 876 | |
| 877 | return rc; |
| 878 | } |
| 879 | |
| 880 | static int bcm_kona_i2c_remove(struct platform_device *pdev) |
| 881 | { |
| 882 | struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev); |
| 883 | |
| 884 | i2c_del_adapter(&dev->adapter); |
| 885 | |
| 886 | return 0; |
| 887 | } |
| 888 | |
| 889 | static const struct of_device_id bcm_kona_i2c_of_match[] = { |
| 890 | {.compatible = "brcm,kona-i2c",}, |
| 891 | {}, |
| 892 | }; |
| 893 | MODULE_DEVICE_TABLE(of, kona_i2c_of_match); |
| 894 | |
| 895 | static struct platform_driver bcm_kona_i2c_driver = { |
| 896 | .driver = { |
| 897 | .name = "bcm-kona-i2c", |
| 898 | .owner = THIS_MODULE, |
| 899 | .of_match_table = bcm_kona_i2c_of_match, |
| 900 | }, |
| 901 | .probe = bcm_kona_i2c_probe, |
| 902 | .remove = bcm_kona_i2c_remove, |
| 903 | }; |
| 904 | module_platform_driver(bcm_kona_i2c_driver); |
| 905 | |
| 906 | MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>"); |
| 907 | MODULE_DESCRIPTION("Broadcom Kona I2C Driver"); |
| 908 | MODULE_LICENSE("GPL v2"); |