SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * linux/arch/arm/mach-at91/clock.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 David Brownell |
| 5 | * Copyright (C) 2005 Ivan Kokshaysky |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/fs.h> |
| 17 | #include <linux/debugfs.h> |
| 18 | #include <linux/seq_file.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 26 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/at91_pmc.h> |
| 29 | #include <mach/cpu.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 30 | |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 31 | #include <asm/proc-fns.h> |
| 32 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 33 | #include "clock.h" |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 34 | #include "generic.h" |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 35 | |
Andrew Victor | 55c20c0 | 2006-06-20 19:31:39 +0100 | [diff] [blame] | 36 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 37 | /* |
| 38 | * There's a lot more which can be done with clocks, including cpufreq |
| 39 | * integration, slow clock mode support (for system suspend), letting |
| 40 | * PLLB be used at other rates (on boards that don't need USB), etc. |
| 41 | */ |
| 42 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 43 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
| 44 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) |
| 45 | #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 46 | #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 47 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 48 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 49 | /* |
| 50 | * Chips have some kind of clocks : group them by functionality |
| 51 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 9918cea | 2012-01-26 14:07:09 +0100 | [diff] [blame] | 52 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 53 | || cpu_is_at91sam9g45() \ |
| 54 | || cpu_is_at91sam9x5()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 55 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 56 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 57 | || cpu_is_at91sam9g45() \ |
| 58 | || cpu_is_at91sam9x5()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 59 | |
Nicolas Ferre | eab4170 | 2009-06-26 15:37:00 +0100 | [diff] [blame] | 60 | #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 61 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 62 | #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 63 | || cpu_is_at91sam9g45() \ |
| 64 | || cpu_is_at91sam9x5())) |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 65 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 66 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ |
| 67 | || cpu_is_at91sam9x5()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 68 | |
| 69 | /* USB host HS & FS */ |
| 70 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) |
| 71 | |
| 72 | /* USB device FS only */ |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 73 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 74 | || cpu_is_at91sam9g45() \ |
| 75 | || cpu_is_at91sam9x5())) |
| 76 | |
| 77 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ |
| 78 | || cpu_is_at91sam9x5()) |
| 79 | |
| 80 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ |
| 81 | || cpu_is_at91sam9x5()) |
| 82 | |
| 83 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 84 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 85 | static LIST_HEAD(clocks); |
| 86 | static DEFINE_SPINLOCK(clk_lock); |
| 87 | |
| 88 | static u32 at91_pllb_usb_init; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * Four primary clock sources: two crystal oscillators (32K, main), and |
| 92 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at |
| 93 | * 48 MHz (unless no USB function clocks are needed). The main clock and |
| 94 | * both PLLs are turned off to run in "slow clock mode" (system suspend). |
| 95 | */ |
| 96 | static struct clk clk32k = { |
| 97 | .name = "clk32k", |
| 98 | .rate_hz = AT91_SLOW_CLOCK, |
| 99 | .users = 1, /* always on */ |
| 100 | .id = 0, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 101 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 102 | }; |
| 103 | static struct clk main_clk = { |
| 104 | .name = "main", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 105 | .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 106 | .id = 1, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 107 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 108 | }; |
| 109 | static struct clk plla = { |
| 110 | .name = "plla", |
| 111 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 112 | .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 113 | .id = 2, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 114 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 115 | }; |
| 116 | |
| 117 | static void pllb_mode(struct clk *clk, int is_on) |
| 118 | { |
| 119 | u32 value; |
| 120 | |
| 121 | if (is_on) { |
| 122 | is_on = AT91_PMC_LOCKB; |
| 123 | value = at91_pllb_usb_init; |
| 124 | } else |
| 125 | value = 0; |
| 126 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 127 | // REVISIT: Add work-around for AT91RM9200 Errata #26 ? |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 128 | at91_sys_write(AT91_CKGR_PLLBR, value); |
| 129 | |
| 130 | do { |
| 131 | cpu_relax(); |
| 132 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); |
| 133 | } |
| 134 | |
| 135 | static struct clk pllb = { |
| 136 | .name = "pllb", |
| 137 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 138 | .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 139 | .mode = pllb_mode, |
| 140 | .id = 3, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 141 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | static void pmc_sys_mode(struct clk *clk, int is_on) |
| 145 | { |
| 146 | if (is_on) |
| 147 | at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); |
| 148 | else |
| 149 | at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); |
| 150 | } |
| 151 | |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 152 | static void pmc_uckr_mode(struct clk *clk, int is_on) |
| 153 | { |
| 154 | unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); |
| 155 | |
| 156 | if (is_on) { |
| 157 | is_on = AT91_PMC_LOCKU; |
| 158 | at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
| 159 | } else |
| 160 | at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); |
| 161 | |
| 162 | do { |
| 163 | cpu_relax(); |
| 164 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); |
| 165 | } |
| 166 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 167 | /* USB function clocks (PLLB must be 48 MHz) */ |
| 168 | static struct clk udpck = { |
| 169 | .name = "udpck", |
| 170 | .parent = &pllb, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 171 | .mode = pmc_sys_mode, |
| 172 | }; |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 173 | struct clk utmi_clk = { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 174 | .name = "utmi_clk", |
| 175 | .parent = &main_clk, |
| 176 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ |
| 177 | .mode = pmc_uckr_mode, |
| 178 | .type = CLK_TYPE_PLL, |
| 179 | }; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 180 | static struct clk uhpck = { |
| 181 | .name = "uhpck", |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 182 | /*.parent = ... we choose parent at runtime */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 183 | .mode = pmc_sys_mode, |
| 184 | }; |
| 185 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 186 | |
| 187 | /* |
| 188 | * The master clock is divided from the CPU clock (by 1-4). It's used for |
| 189 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more |
| 190 | * (e.g baud rate generation). It's sourced from one of the primary clocks. |
| 191 | */ |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 192 | struct clk mck = { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 193 | .name = "mck", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 194 | .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | static void pmc_periph_mode(struct clk *clk, int is_on) |
| 198 | { |
| 199 | if (is_on) |
| 200 | at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); |
| 201 | else |
| 202 | at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); |
| 203 | } |
| 204 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 205 | static struct clk __init *at91_css_to_clk(unsigned long css) |
| 206 | { |
| 207 | switch (css) { |
| 208 | case AT91_PMC_CSS_SLOW: |
| 209 | return &clk32k; |
| 210 | case AT91_PMC_CSS_MAIN: |
| 211 | return &main_clk; |
| 212 | case AT91_PMC_CSS_PLLA: |
| 213 | return &plla; |
| 214 | case AT91_PMC_CSS_PLLB: |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 215 | if (cpu_has_upll()) |
| 216 | /* CSS_PLLB == CSS_UPLL */ |
| 217 | return &utmi_clk; |
| 218 | else if (cpu_has_pllb()) |
| 219 | return &pllb; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 220 | break; |
| 221 | /* alternate PMC: can use master clock */ |
| 222 | case AT91_PMC_CSS_MASTER: |
| 223 | return &mck; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 224 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 225 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 226 | return NULL; |
| 227 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 228 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 229 | static int pmc_prescaler_divider(u32 reg) |
| 230 | { |
| 231 | if (cpu_has_alt_prescaler()) { |
| 232 | return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET); |
| 233 | } else { |
| 234 | return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET); |
| 235 | } |
| 236 | } |
| 237 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 238 | static void __clk_enable(struct clk *clk) |
| 239 | { |
| 240 | if (clk->parent) |
| 241 | __clk_enable(clk->parent); |
| 242 | if (clk->users++ == 0 && clk->mode) |
| 243 | clk->mode(clk, 1); |
| 244 | } |
| 245 | |
| 246 | int clk_enable(struct clk *clk) |
| 247 | { |
| 248 | unsigned long flags; |
| 249 | |
| 250 | spin_lock_irqsave(&clk_lock, flags); |
| 251 | __clk_enable(clk); |
| 252 | spin_unlock_irqrestore(&clk_lock, flags); |
| 253 | return 0; |
| 254 | } |
| 255 | EXPORT_SYMBOL(clk_enable); |
| 256 | |
| 257 | static void __clk_disable(struct clk *clk) |
| 258 | { |
| 259 | BUG_ON(clk->users == 0); |
| 260 | if (--clk->users == 0 && clk->mode) |
| 261 | clk->mode(clk, 0); |
| 262 | if (clk->parent) |
| 263 | __clk_disable(clk->parent); |
| 264 | } |
| 265 | |
| 266 | void clk_disable(struct clk *clk) |
| 267 | { |
| 268 | unsigned long flags; |
| 269 | |
| 270 | spin_lock_irqsave(&clk_lock, flags); |
| 271 | __clk_disable(clk); |
| 272 | spin_unlock_irqrestore(&clk_lock, flags); |
| 273 | } |
| 274 | EXPORT_SYMBOL(clk_disable); |
| 275 | |
| 276 | unsigned long clk_get_rate(struct clk *clk) |
| 277 | { |
| 278 | unsigned long flags; |
| 279 | unsigned long rate; |
| 280 | |
| 281 | spin_lock_irqsave(&clk_lock, flags); |
| 282 | for (;;) { |
| 283 | rate = clk->rate_hz; |
| 284 | if (rate || !clk->parent) |
| 285 | break; |
| 286 | clk = clk->parent; |
| 287 | } |
| 288 | spin_unlock_irqrestore(&clk_lock, flags); |
| 289 | return rate; |
| 290 | } |
| 291 | EXPORT_SYMBOL(clk_get_rate); |
| 292 | |
| 293 | /*------------------------------------------------------------------------*/ |
| 294 | |
| 295 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 296 | |
| 297 | /* |
| 298 | * For now, only the programmable clocks support reparenting (MCK could |
| 299 | * do this too, with care) or rate changing (the PLLs could do this too, |
| 300 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get |
| 301 | * a better rate match; we don't. |
| 302 | */ |
| 303 | |
| 304 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 305 | { |
| 306 | unsigned long flags; |
| 307 | unsigned prescale; |
| 308 | unsigned long actual; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 309 | unsigned long prev = ULONG_MAX; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 310 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 311 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 312 | return -EINVAL; |
| 313 | spin_lock_irqsave(&clk_lock, flags); |
| 314 | |
| 315 | actual = clk->parent->rate_hz; |
| 316 | for (prescale = 0; prescale < 7; prescale++) { |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 317 | if (actual > rate) |
| 318 | prev = actual; |
| 319 | |
| 320 | if (actual && actual <= rate) { |
| 321 | if ((prev - rate) < (rate - actual)) { |
| 322 | actual = prev; |
| 323 | prescale--; |
| 324 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 325 | break; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 326 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 327 | actual >>= 1; |
| 328 | } |
| 329 | |
| 330 | spin_unlock_irqrestore(&clk_lock, flags); |
| 331 | return (prescale < 7) ? actual : -ENOENT; |
| 332 | } |
| 333 | EXPORT_SYMBOL(clk_round_rate); |
| 334 | |
| 335 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 336 | { |
| 337 | unsigned long flags; |
| 338 | unsigned prescale; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 339 | unsigned long prescale_offset, css_mask; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 340 | unsigned long actual; |
| 341 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 342 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 343 | return -EINVAL; |
| 344 | if (clk->users) |
| 345 | return -EBUSY; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 346 | |
| 347 | if (cpu_has_alt_prescaler()) { |
| 348 | prescale_offset = PMC_ALT_PRES_OFFSET; |
| 349 | css_mask = AT91_PMC_ALT_PCKR_CSS; |
| 350 | } else { |
| 351 | prescale_offset = PMC_PRES_OFFSET; |
| 352 | css_mask = AT91_PMC_CSS; |
| 353 | } |
| 354 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 355 | spin_lock_irqsave(&clk_lock, flags); |
| 356 | |
| 357 | actual = clk->parent->rate_hz; |
| 358 | for (prescale = 0; prescale < 7; prescale++) { |
| 359 | if (actual && actual <= rate) { |
| 360 | u32 pckr; |
| 361 | |
| 362 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 363 | pckr &= css_mask; /* keep clock selection */ |
| 364 | pckr |= prescale << prescale_offset; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 365 | at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); |
| 366 | clk->rate_hz = actual; |
| 367 | break; |
| 368 | } |
| 369 | actual >>= 1; |
| 370 | } |
| 371 | |
| 372 | spin_unlock_irqrestore(&clk_lock, flags); |
| 373 | return (prescale < 7) ? actual : -ENOENT; |
| 374 | } |
| 375 | EXPORT_SYMBOL(clk_set_rate); |
| 376 | |
| 377 | struct clk *clk_get_parent(struct clk *clk) |
| 378 | { |
| 379 | return clk->parent; |
| 380 | } |
| 381 | EXPORT_SYMBOL(clk_get_parent); |
| 382 | |
| 383 | int clk_set_parent(struct clk *clk, struct clk *parent) |
| 384 | { |
| 385 | unsigned long flags; |
| 386 | |
| 387 | if (clk->users) |
| 388 | return -EBUSY; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 389 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 390 | return -EINVAL; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 391 | |
| 392 | if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB) |
| 393 | return -EINVAL; |
| 394 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 395 | spin_lock_irqsave(&clk_lock, flags); |
| 396 | |
| 397 | clk->rate_hz = parent->rate_hz; |
| 398 | clk->parent = parent; |
| 399 | at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); |
| 400 | |
| 401 | spin_unlock_irqrestore(&clk_lock, flags); |
| 402 | return 0; |
| 403 | } |
| 404 | EXPORT_SYMBOL(clk_set_parent); |
| 405 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 406 | /* establish PCK0..PCKN parentage and rate */ |
David Brownell | 72e7ae8 | 2008-02-06 22:03:42 +0100 | [diff] [blame] | 407 | static void __init init_programmable_clock(struct clk *clk) |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 408 | { |
| 409 | struct clk *parent; |
| 410 | u32 pckr; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 411 | unsigned int css_mask; |
| 412 | |
| 413 | if (cpu_has_alt_prescaler()) |
| 414 | css_mask = AT91_PMC_ALT_PCKR_CSS; |
| 415 | else |
| 416 | css_mask = AT91_PMC_CSS; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 417 | |
| 418 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 419 | parent = at91_css_to_clk(pckr & css_mask); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 420 | clk->parent = parent; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 421 | clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 422 | } |
| 423 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 424 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ |
| 425 | |
| 426 | /*------------------------------------------------------------------------*/ |
| 427 | |
| 428 | #ifdef CONFIG_DEBUG_FS |
| 429 | |
| 430 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 431 | { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 432 | u32 scsr, pcsr, uckr = 0, sr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 433 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 434 | |
Nicolas Ferre | 940192e | 2012-02-23 09:44:37 +0100 | [diff] [blame^] | 435 | scsr = at91_sys_read(AT91_PMC_SCSR); |
| 436 | pcsr = at91_sys_read(AT91_PMC_PCSR); |
| 437 | sr = at91_sys_read(AT91_PMC_SR); |
| 438 | seq_printf(s, "SCSR = %8x\n", scsr); |
| 439 | seq_printf(s, "PCSR = %8x\n", pcsr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 440 | seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); |
| 441 | seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); |
| 442 | seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 443 | if (cpu_has_pllb()) |
Nicolas Ferre | ba45ca4 | 2008-04-08 13:59:18 +0100 | [diff] [blame] | 444 | seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); |
Nicolas Ferre | 940192e | 2012-02-23 09:44:37 +0100 | [diff] [blame^] | 445 | if (cpu_has_utmi()) { |
| 446 | uckr = at91_sys_read(AT91_CKGR_UCKR); |
| 447 | seq_printf(s, "UCKR = %8x\n", uckr); |
| 448 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 449 | seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 450 | if (cpu_has_upll()) |
| 451 | seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); |
Nicolas Ferre | 940192e | 2012-02-23 09:44:37 +0100 | [diff] [blame^] | 452 | seq_printf(s, "SR = %8x\n", sr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 453 | |
| 454 | seq_printf(s, "\n"); |
| 455 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 456 | list_for_each_entry(clk, &clocks, node) { |
| 457 | char *state; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 458 | |
| 459 | if (clk->mode == pmc_sys_mode) |
| 460 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 461 | else if (clk->mode == pmc_periph_mode) |
| 462 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 463 | else if (clk->mode == pmc_uckr_mode) |
| 464 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 465 | else if (clk->pmc_mask) |
| 466 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 467 | else if (clk == &clk32k || clk == &main_clk) |
| 468 | state = "on"; |
| 469 | else |
| 470 | state = ""; |
| 471 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 472 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 473 | clk->name, clk->users, state, clk_get_rate(clk), |
| 474 | clk->parent ? clk->parent->name : ""); |
| 475 | } |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static int at91_clk_open(struct inode *inode, struct file *file) |
| 480 | { |
| 481 | return single_open(file, at91_clk_show, NULL); |
| 482 | } |
| 483 | |
Arjan van de Ven | 5dfe4c9 | 2007-02-12 00:55:31 -0800 | [diff] [blame] | 484 | static const struct file_operations at91_clk_operations = { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 485 | .open = at91_clk_open, |
| 486 | .read = seq_read, |
| 487 | .llseek = seq_lseek, |
| 488 | .release = single_release, |
| 489 | }; |
| 490 | |
| 491 | static int __init at91_clk_debugfs_init(void) |
| 492 | { |
| 493 | /* /sys/kernel/debug/at91_clk */ |
| 494 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | postcore_initcall(at91_clk_debugfs_init); |
| 499 | |
| 500 | #endif |
| 501 | |
| 502 | /*------------------------------------------------------------------------*/ |
| 503 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 504 | /* Register a new clock */ |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 505 | static void __init at91_clk_add(struct clk *clk) |
| 506 | { |
| 507 | list_add_tail(&clk->node, &clocks); |
| 508 | |
| 509 | clk->cl.con_id = clk->name; |
| 510 | clk->cl.clk = clk; |
| 511 | clkdev_add(&clk->cl); |
| 512 | } |
| 513 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 514 | int __init clk_register(struct clk *clk) |
| 515 | { |
| 516 | if (clk_is_peripheral(clk)) { |
Nicolas Ferre | 5afddee | 2010-09-09 19:58:23 +0200 | [diff] [blame] | 517 | if (!clk->parent) |
| 518 | clk->parent = &mck; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 519 | clk->mode = pmc_periph_mode; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 520 | } |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 521 | else if (clk_is_sys(clk)) { |
| 522 | clk->parent = &mck; |
| 523 | clk->mode = pmc_sys_mode; |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 524 | } |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 525 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 526 | else if (clk_is_programmable(clk)) { |
| 527 | clk->mode = pmc_sys_mode; |
| 528 | init_programmable_clock(clk); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 529 | } |
| 530 | #endif |
| 531 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 532 | at91_clk_add(clk); |
| 533 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 534 | return 0; |
| 535 | } |
| 536 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 537 | /*------------------------------------------------------------------------*/ |
| 538 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 539 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) |
| 540 | { |
| 541 | unsigned mul, div; |
| 542 | |
| 543 | div = reg & 0xff; |
| 544 | mul = (reg >> 16) & 0x7ff; |
| 545 | if (div && mul) { |
| 546 | freq /= div; |
| 547 | freq *= mul + 1; |
| 548 | } else |
| 549 | freq = 0; |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 550 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 551 | return freq; |
| 552 | } |
| 553 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 554 | static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) |
| 555 | { |
| 556 | if (pll == &pllb && (reg & AT91_PMC_USB96M)) |
| 557 | return freq / 2; |
| 558 | else |
| 559 | return freq; |
| 560 | } |
| 561 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 562 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) |
| 563 | { |
| 564 | unsigned i, div = 0, mul = 0, diff = 1 << 30; |
| 565 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; |
| 566 | |
| 567 | /* PLL output max 240 MHz (or 180 MHz per errata) */ |
| 568 | if (out_freq > 240000000) |
| 569 | goto fail; |
| 570 | |
| 571 | for (i = 1; i < 256; i++) { |
| 572 | int diff1; |
| 573 | unsigned input, mul1; |
| 574 | |
| 575 | /* |
| 576 | * PLL input between 1MHz and 32MHz per spec, but lower |
| 577 | * frequences seem necessary in some cases so allow 100K. |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 578 | * Warning: some newer products need 2MHz min. |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 579 | */ |
| 580 | input = main_freq / i; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 581 | if (cpu_is_at91sam9g20() && input < 2000000) |
| 582 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 583 | if (input < 100000) |
| 584 | continue; |
| 585 | if (input > 32000000) |
| 586 | continue; |
| 587 | |
| 588 | mul1 = out_freq / input; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 589 | if (cpu_is_at91sam9g20() && mul > 63) |
| 590 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 591 | if (mul1 > 2048) |
| 592 | continue; |
| 593 | if (mul1 < 2) |
| 594 | goto fail; |
| 595 | |
| 596 | diff1 = out_freq - input * mul1; |
| 597 | if (diff1 < 0) |
| 598 | diff1 = -diff1; |
| 599 | if (diff > diff1) { |
| 600 | diff = diff1; |
| 601 | div = i; |
| 602 | mul = mul1; |
| 603 | if (diff == 0) |
| 604 | break; |
| 605 | } |
| 606 | } |
| 607 | if (i == 256 && diff > (out_freq >> 5)) |
| 608 | goto fail; |
| 609 | return ret | ((mul - 1) << 16) | div; |
| 610 | fail: |
| 611 | return 0; |
| 612 | } |
| 613 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 614 | static struct clk *const standard_pmc_clocks[] __initdata = { |
| 615 | /* four primary clocks */ |
| 616 | &clk32k, |
| 617 | &main_clk, |
| 618 | &plla, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 619 | |
| 620 | /* MCK */ |
| 621 | &mck |
| 622 | }; |
| 623 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 624 | /* PLLB generated USB full speed clock init */ |
| 625 | static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) |
| 626 | { |
| 627 | /* |
| 628 | * USB clock init: choose 48 MHz PLLB value, |
| 629 | * disable 48MHz clock during usb peripheral suspend. |
| 630 | * |
| 631 | * REVISIT: assumes MCK doesn't derive from PLLB! |
| 632 | */ |
| 633 | uhpck.parent = &pllb; |
| 634 | |
| 635 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; |
| 636 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); |
| 637 | if (cpu_is_at91rm9200()) { |
| 638 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; |
| 639 | udpck.pmc_mask = AT91RM9200_PMC_UDP; |
| 640 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
Nicolas Ferre | eab4170 | 2009-06-26 15:37:00 +0100 | [diff] [blame] | 641 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || |
| 642 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || |
Jean-Christophe PLAGNIOL-VILLARD | 7a2207a | 2011-05-17 20:51:14 +0800 | [diff] [blame] | 643 | cpu_is_at91sam9g10()) { |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 644 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 645 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 646 | } |
| 647 | at91_sys_write(AT91_CKGR_PLLBR, 0); |
| 648 | |
| 649 | udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 650 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 651 | } |
| 652 | |
| 653 | /* UPLL generated USB full speed clock init */ |
| 654 | static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) |
| 655 | { |
| 656 | /* |
| 657 | * USB clock init: choose 480 MHz from UPLL, |
| 658 | */ |
| 659 | unsigned int usbr = AT91_PMC_USBS_UPLL; |
| 660 | |
| 661 | /* Setup divider by 10 to reach 48 MHz */ |
| 662 | usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; |
| 663 | |
| 664 | at91_sys_write(AT91_PMC_USB, usbr); |
| 665 | |
| 666 | /* Now set uhpck values */ |
| 667 | uhpck.parent = &utmi_clk; |
| 668 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
Ryan Mallon | 8251544 | 2010-06-02 12:55:36 +1200 | [diff] [blame] | 669 | uhpck.rate_hz = utmi_clk.rate_hz; |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 670 | uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); |
| 671 | } |
| 672 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 673 | int __init at91_clock_init(unsigned long main_clock) |
| 674 | { |
| 675 | unsigned tmp, freq, mckr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 676 | int i; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 677 | int pll_overclock = false; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 678 | |
| 679 | /* |
| 680 | * When the bootloader initialized the main oscillator correctly, |
| 681 | * there's no problem using the cycle counter. But if it didn't, |
| 682 | * or when using oscillator bypass mode, we must be told the speed |
| 683 | * of the main clock. |
| 684 | */ |
| 685 | if (!main_clock) { |
| 686 | do { |
| 687 | tmp = at91_sys_read(AT91_CKGR_MCFR); |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 688 | } while (!(tmp & AT91_PMC_MAINRDY)); |
| 689 | main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 690 | } |
| 691 | main_clk.rate_hz = main_clock; |
| 692 | |
| 693 | /* report if PLLA is more than mildly overclocked */ |
| 694 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 695 | if (cpu_has_300M_plla()) { |
| 696 | if (plla.rate_hz > 300000000) |
| 697 | pll_overclock = true; |
| 698 | } else if (cpu_has_800M_plla()) { |
| 699 | if (plla.rate_hz > 800000000) |
| 700 | pll_overclock = true; |
| 701 | } else { |
| 702 | if (plla.rate_hz > 209000000) |
| 703 | pll_overclock = true; |
| 704 | } |
| 705 | if (pll_overclock) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 706 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
| 707 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 708 | if (cpu_has_plladiv2()) { |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 709 | mckr = at91_sys_read(AT91_PMC_MCKR); |
| 710 | plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ |
| 711 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 712 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 713 | if (!cpu_has_pllb() && cpu_has_upll()) { |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 714 | /* setup UTMI clock as the fourth primary clock |
| 715 | * (instead of pllb) */ |
| 716 | utmi_clk.type |= CLK_TYPE_PRIMARY; |
| 717 | utmi_clk.id = 3; |
| 718 | } |
| 719 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 720 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 721 | /* |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 722 | * USB HS clock init |
| 723 | */ |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 724 | if (cpu_has_utmi()) { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 725 | /* |
| 726 | * multiplier is hard-wired to 40 |
| 727 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) |
| 728 | */ |
| 729 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 730 | |
| 731 | /* UTMI bias and PLL are managed at the same time */ |
| 732 | if (cpu_has_upll()) |
| 733 | utmi_clk.pmc_mask |= AT91_PMC_BIASEN; |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 734 | } |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 735 | |
| 736 | /* |
| 737 | * USB FS clock init |
| 738 | */ |
| 739 | if (cpu_has_pllb()) |
| 740 | at91_pllb_usbfs_clock_init(main_clock); |
| 741 | if (cpu_has_upll()) |
| 742 | /* assumes that we choose UPLL for USB and not PLLA */ |
| 743 | at91_upll_usbfs_clock_init(main_clock); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 744 | |
| 745 | /* |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 746 | * MCK and CPU derive from one of those primary clocks. |
| 747 | * For now, assume this parentage won't change. |
| 748 | */ |
| 749 | mckr = at91_sys_read(AT91_PMC_MCKR); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 750 | mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 751 | freq = mck.parent->rate_hz; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 752 | freq /= pmc_prescaler_divider(mckr); /* prescale */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 753 | if (cpu_is_at91rm9200()) { |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 754 | mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 755 | } else if (cpu_is_at91sam9g20()) { |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 756 | mck.rate_hz = (mckr & AT91_PMC_MDIV) ? |
| 757 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ |
| 758 | if (mckr & AT91_PMC_PDIV) |
| 759 | freq /= 2; /* processor clock division */ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 760 | } else if (cpu_has_mdiv3()) { |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 761 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? |
| 762 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 763 | } else { |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 764 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 765 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 766 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 767 | if (cpu_has_alt_prescaler()) { |
| 768 | /* Programmable clocks can use MCK */ |
| 769 | mck.type |= CLK_TYPE_PRIMARY; |
| 770 | mck.id = 4; |
| 771 | } |
| 772 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 773 | /* Register the PMC's standard clocks */ |
| 774 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 775 | at91_clk_add(standard_pmc_clocks[i]); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 776 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 777 | if (cpu_has_pllb()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 778 | at91_clk_add(&pllb); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 779 | |
| 780 | if (cpu_has_uhp()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 781 | at91_clk_add(&uhpck); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 782 | |
| 783 | if (cpu_has_udpfs()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 784 | at91_clk_add(&udpck); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 785 | |
| 786 | if (cpu_has_utmi()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 787 | at91_clk_add(&utmi_clk); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 788 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 789 | /* MCK and CPU clock are "always on" */ |
| 790 | clk_enable(&mck); |
| 791 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 792 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", |
| 793 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, |
| 794 | (unsigned) main_clock / 1000000, |
| 795 | ((unsigned) main_clock % 1000000) / 1000); |
| 796 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 797 | return 0; |
| 798 | } |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 799 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 800 | /* |
| 801 | * Several unused clocks may be active. Turn them off. |
| 802 | */ |
| 803 | static int __init at91_clock_reset(void) |
| 804 | { |
| 805 | unsigned long pcdr = 0; |
| 806 | unsigned long scdr = 0; |
| 807 | struct clk *clk; |
| 808 | |
| 809 | list_for_each_entry(clk, &clocks, node) { |
| 810 | if (clk->users > 0) |
| 811 | continue; |
| 812 | |
| 813 | if (clk->mode == pmc_periph_mode) |
| 814 | pcdr |= clk->pmc_mask; |
| 815 | |
| 816 | if (clk->mode == pmc_sys_mode) |
| 817 | scdr |= clk->pmc_mask; |
| 818 | |
| 819 | pr_debug("Clocks: disable unused %s\n", clk->name); |
| 820 | } |
| 821 | |
| 822 | at91_sys_write(AT91_PMC_PCDR, pcdr); |
| 823 | at91_sys_write(AT91_PMC_SCDR, scdr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 824 | |
| 825 | return 0; |
| 826 | } |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 827 | late_initcall(at91_clock_reset); |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 828 | |
| 829 | void at91sam9_idle(void) |
| 830 | { |
| 831 | at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); |
| 832 | cpu_do_idle(); |
| 833 | } |