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James Courtier-Dutton3969f612006-04-09 17:44:13 +01001/*
2 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
3 * Driver p17v chips
4 * Version: 0.01
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22/******************************************************************************/
23/* Audigy2Value Tina (P17V) pointer-offset register set,
24 * accessed through the PTR20 and DATA24 registers */
25/******************************************************************************/
26
27/* 00 - 07: Not used */
28#define P17V_PLAYBACK_FIFO_PTR 0x08 /* Current playback fifo pointer
29 * and number of sound samples in cache.
30 */
31/* 09 - 12: Not used */
32#define P17V_CAPTURE_FIFO_PTR 0x13 /* Current capture fifo pointer
33 * and number of sound samples in cache.
34 */
35/* 14 - 17: Not used */
36#define P17V_PB_CHN_SEL 0x18 /* P17v playback channel select */
37#define P17V_SE_SLOT_SEL_L 0x19 /* Sound Engine slot select low */
38#define P17V_SE_SLOT_SEL_H 0x1a /* Sound Engine slot select high */
39/* 1b - 1f: Not used */
40/* 20 - 2f: Not used */
41/* 30 - 3b: Not used */
42#define P17V_SPI 0x3c /* SPI interface register */
43#define P17V_I2C_ADDR 0x3d /* I2C Address */
44#define P17V_I2C_0 0x3e /* I2C Data */
45#define P17V_I2C_1 0x3f /* I2C Data */
James Courtier-Dutton184c1e22006-12-06 15:58:02 +000046/* I2C values */
47#define I2C_A_ADC_ADD_MASK 0x000000fe /*The address is a 7 bit address */
48#define I2C_A_ADC_RW_MASK 0x00000001 /*bit mask for R/W */
49#define I2C_A_ADC_TRANS_MASK 0x00000010 /*Bit mask for I2c address DAC value */
50#define I2C_A_ADC_ABORT_MASK 0x00000020 /*Bit mask for I2C transaction abort flag */
51#define I2C_A_ADC_LAST_MASK 0x00000040 /*Bit mask for Last word transaction */
52#define I2C_A_ADC_BYTE_MASK 0x00000080 /*Bit mask for Byte Mode */
53
54#define I2C_A_ADC_ADD 0x00000034 /*This is the Device address for ADC */
55#define I2C_A_ADC_READ 0x00000001 /*To perform a read operation */
56#define I2C_A_ADC_START 0x00000100 /*Start I2C transaction */
57#define I2C_A_ADC_ABORT 0x00000200 /*I2C transaction abort */
58#define I2C_A_ADC_LAST 0x00000400 /*I2C last transaction */
59#define I2C_A_ADC_BYTE 0x00000800 /*I2C one byte mode */
60
61#define I2C_D_ADC_REG_MASK 0xfe000000 /*ADC address register */
62#define I2C_D_ADC_DAT_MASK 0x01ff0000 /*ADC data register */
63
64#define ADC_TIMEOUT 0x00000007 /*ADC Timeout Clock Disable */
65#define ADC_IFC_CTRL 0x0000000b /*ADC Interface Control */
66#define ADC_MASTER 0x0000000c /*ADC Master Mode Control */
67#define ADC_POWER 0x0000000d /*ADC PowerDown Control */
68#define ADC_ATTEN_ADCL 0x0000000e /*ADC Attenuation ADCL */
69#define ADC_ATTEN_ADCR 0x0000000f /*ADC Attenuation ADCR */
70#define ADC_ALC_CTRL1 0x00000010 /*ADC ALC Control 1 */
71#define ADC_ALC_CTRL2 0x00000011 /*ADC ALC Control 2 */
72#define ADC_ALC_CTRL3 0x00000012 /*ADC ALC Control 3 */
73#define ADC_NOISE_CTRL 0x00000013 /*ADC Noise Gate Control */
74#define ADC_LIMIT_CTRL 0x00000014 /*ADC Limiter Control */
75#define ADC_MUX 0x00000015 /*ADC Mux offset */
76#if 0
77/* FIXME: Not tested yet. */
78#define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain
79#define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB
80#define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute
81#define ADC_MUTE 0x000000c0 //Value to mute ADC
82#define ADC_OSR 0x00000008 //Mask for ADC oversample rate select
83#define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock
84#define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter
85#define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window
86#endif
87
88#define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux
89#define ADC_MUX_0 0x00000001 //Value to select Unknown at ADC Mux (Not used)
90#define ADC_MUX_1 0x00000002 //Value to select Unknown at ADC Mux (Not used)
91#define ADC_MUX_2 0x00000004 //Value to select Mic at ADC Mux
92#define ADC_MUX_3 0x00000008 //Value to select Line-In at ADC Mux
James Courtier-Dutton3969f612006-04-09 17:44:13 +010093
94#define P17V_START_AUDIO 0x40 /* Start Audio bit */
95/* 41 - 47: Reserved */
96#define P17V_START_CAPTURE 0x48 /* Start Capture bit */
97#define P17V_CAPTURE_FIFO_BASE 0x49 /* Record FIFO base address */
98#define P17V_CAPTURE_FIFO_SIZE 0x4a /* Record FIFO buffer size */
99#define P17V_CAPTURE_FIFO_INDEX 0x4b /* Record FIFO capture index */
100#define P17V_CAPTURE_VOL_H 0x4c /* P17v capture volume control */
101#define P17V_CAPTURE_VOL_L 0x4d /* P17v capture volume control */
102/* 4e - 4f: Not used */
103/* 50 - 5f: Not used */
104#define P17V_SRCSel 0x60 /* SRC48 and SRCMulti sample rate select
105 * and output select
106 */
107#define P17V_MIXER_AC97_10K1_VOL_L 0x61 /* 10K to Mixer_AC97 input volume control */
108#define P17V_MIXER_AC97_10K1_VOL_H 0x62 /* 10K to Mixer_AC97 input volume control */
109#define P17V_MIXER_AC97_P17V_VOL_L 0x63 /* P17V to Mixer_AC97 input volume control */
110#define P17V_MIXER_AC97_P17V_VOL_H 0x64 /* P17V to Mixer_AC97 input volume control */
111#define P17V_MIXER_AC97_SRP_REC_VOL_L 0x65 /* SRP Record to Mixer_AC97 input volume control */
112#define P17V_MIXER_AC97_SRP_REC_VOL_H 0x66 /* SRP Record to Mixer_AC97 input volume control */
113/* 67 - 68: Reserved */
114#define P17V_MIXER_Spdif_10K1_VOL_L 0x69 /* 10K to Mixer_Spdif input volume control */
115#define P17V_MIXER_Spdif_10K1_VOL_H 0x6A /* 10K to Mixer_Spdif input volume control */
116#define P17V_MIXER_Spdif_P17V_VOL_L 0x6B /* P17V to Mixer_Spdif input volume control */
117#define P17V_MIXER_Spdif_P17V_VOL_H 0x6C /* P17V to Mixer_Spdif input volume control */
118#define P17V_MIXER_Spdif_SRP_REC_VOL_L 0x6D /* SRP Record to Mixer_Spdif input volume control */
119#define P17V_MIXER_Spdif_SRP_REC_VOL_H 0x6E /* SRP Record to Mixer_Spdif input volume control */
120/* 6f - 70: Reserved */
121#define P17V_MIXER_I2S_10K1_VOL_L 0x71 /* 10K to Mixer_I2S input volume control */
122#define P17V_MIXER_I2S_10K1_VOL_H 0x72 /* 10K to Mixer_I2S input volume control */
123#define P17V_MIXER_I2S_P17V_VOL_L 0x73 /* P17V to Mixer_I2S input volume control */
124#define P17V_MIXER_I2S_P17V_VOL_H 0x74 /* P17V to Mixer_I2S input volume control */
125#define P17V_MIXER_I2S_SRP_REC_VOL_L 0x75 /* SRP Record to Mixer_I2S input volume control */
126#define P17V_MIXER_I2S_SRP_REC_VOL_H 0x76 /* SRP Record to Mixer_I2S input volume control */
127/* 77 - 78: Reserved */
128#define P17V_MIXER_AC97_ENABLE 0x79 /* Mixer AC97 input audio enable */
129#define P17V_MIXER_SPDIF_ENABLE 0x7A /* Mixer SPDIF input audio enable */
130#define P17V_MIXER_I2S_ENABLE 0x7B /* Mixer I2S input audio enable */
131#define P17V_AUDIO_OUT_ENABLE 0x7C /* Audio out enable */
132#define P17V_MIXER_ATT 0x7D /* SRP Mixer Attenuation Select */
133#define P17V_SRP_RECORD_SRR 0x7E /* SRP Record channel source Select */
134#define P17V_SOFT_RESET_SRP_MIXER 0x7F /* SRP and mixer soft reset */
135
136#define P17V_AC97_OUT_MASTER_VOL_L 0x80 /* AC97 Output master volume control */
137#define P17V_AC97_OUT_MASTER_VOL_H 0x81 /* AC97 Output master volume control */
138#define P17V_SPDIF_OUT_MASTER_VOL_L 0x82 /* SPDIF Output master volume control */
139#define P17V_SPDIF_OUT_MASTER_VOL_H 0x83 /* SPDIF Output master volume control */
140#define P17V_I2S_OUT_MASTER_VOL_L 0x84 /* I2S Output master volume control */
141#define P17V_I2S_OUT_MASTER_VOL_H 0x85 /* I2S Output master volume control */
142/* 86 - 87: Not used */
143#define P17V_I2S_CHANNEL_SWAP_PHASE_INVERSE 0x88 /* I2S out mono channel swap
144 * and phase inverse */
145#define P17V_SPDIF_CHANNEL_SWAP_PHASE_INVERSE 0x89 /* SPDIF out mono channel swap
146 * and phase inverse */
147/* 8A: Not used */
148#define P17V_SRP_P17V_ESR 0x8B /* SRP_P17V estimated sample rate and rate lock */
149#define P17V_SRP_REC_ESR 0x8C /* SRP_REC estimated sample rate and rate lock */
150#define P17V_SRP_BYPASS 0x8D /* srps channel bypass and srps bypass */
151/* 8E - 92: Not used */
152#define P17V_I2S_SRC_SEL 0x93 /* I2SIN mode sel */
153
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