| Lennert Buytenhek | 19cfd5c | 2008-05-10 23:25:46 +0200 | [diff] [blame] | 1 | #ifndef __ARCH_ORION5X_MPP_H |
| 2 | #define __ARCH_ORION5X_MPP_H |
| 3 | |
| 4 | enum orion5x_mpp_type { |
| 5 | /* |
| 6 | * This MPP is unused. |
| 7 | */ |
| 8 | MPP_UNUSED, |
| 9 | |
| 10 | /* |
| 11 | * This MPP pin is used as a generic GPIO pin. Valid for |
| 12 | * MPPs 0-15 and device bus data pins 16-31. On 5182, also |
| 13 | * valid for MPPs 16-19. |
| 14 | */ |
| 15 | MPP_GPIO, |
| 16 | |
| 17 | /* |
| 18 | * This MPP is used as PCIe_RST_OUTn pin. Valid for |
| 19 | * MPP 0 only. |
| 20 | */ |
| 21 | MPP_PCIE_RST_OUTn, |
| 22 | |
| 23 | /* |
| 24 | * This MPP is used as PCI arbiter pin (REQn/GNTn). |
| 25 | * Valid for MPPs 0-7 only. |
| 26 | */ |
| 27 | MPP_PCI_ARB, |
| 28 | |
| 29 | /* |
| 30 | * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only. |
| 31 | */ |
| 32 | MPP_PCI_PMEn, |
| 33 | |
| 34 | /* |
| 35 | * This MPP is used as GigE half-duplex (COL, CRS) or GMII |
| 36 | * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for |
| 37 | * MPPs 8-19 only. |
| 38 | */ |
| 39 | MPP_GIGE, |
| 40 | |
| 41 | /* |
| 42 | * This MPP is used as NAND REn/WEn pin. Valid for MPPs |
| 43 | * 4-7 and 12-17 only, and only on the 5181l/5182/5281. |
| 44 | */ |
| 45 | MPP_NAND, |
| 46 | |
| 47 | /* |
| 48 | * This MPP is used as a PCI clock output pin. Valid for |
| 49 | * MPPs 6-7 only, and only on the 5181l. |
| 50 | */ |
| 51 | MPP_PCI_CLK, |
| 52 | |
| 53 | /* |
| 54 | * This MPP is used as a SATA presence/activity LED. |
| 55 | * Valid for MPPs 4-7 and 12-15 only, and only on the 5182. |
| 56 | */ |
| 57 | MPP_SATA_LED, |
| 58 | |
| 59 | /* |
| 60 | * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin. |
| 61 | * Valid for MPPs 16-19 only. |
| 62 | */ |
| 63 | MPP_UART, |
| 64 | }; |
| 65 | |
| 66 | struct orion5x_mpp_mode { |
| 67 | int mpp; |
| 68 | enum orion5x_mpp_type type; |
| 69 | }; |
| 70 | |
| 71 | void orion5x_mpp_conf(struct orion5x_mpp_mode *mode); |
| 72 | |
| 73 | |
| 74 | #endif |