Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 94d1dd87316fdb7a403a2750e13ec839fd2fadea / . / drivers / soc / mediatek / mtk-pmic-wrap.c
blob: db5be1eec54c8db3977ea810e13c5470f416aaa7 [file] [log] [blame]
Flora Fu1f022d82015-03-17 11:14:34 +0100[diff] [blame]1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/clk.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23
24#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
25#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
26#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
27#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
28#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
29#define PWRAP_MT8135_BRIDGE_INT_EN 0x38
30#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
31#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
32#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
33
34/* macro for wrapper status */
35#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
36#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
37#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
38#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
39#define PWRAP_STATE_INIT_DONE0 (1 << 21)
40
41/* macro for WACS FSM */
42#define PWRAP_WACS_FSM_IDLE 0x00
43#define PWRAP_WACS_FSM_REQ 0x02
44#define PWRAP_WACS_FSM_WFDLE 0x04
45#define PWRAP_WACS_FSM_WFVLDCLR 0x06
46#define PWRAP_WACS_INIT_DONE 0x01
47#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
48#define PWRAP_WACS_SYNC_BUSY 0x00
49
50/* macro for device wrapper default value */
51#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
52#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
53
54/* macro for manual command */
55#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
56#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
57#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
58#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
59#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
60#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
61#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
62
63/* macro for slave device wrapper registers */
64#define PWRAP_DEW_BASE 0xbc00
65#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
66#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
67#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
68#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
69#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
70#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
71#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
72#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
73#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
74#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
75#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
76#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
77#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
78#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
79#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
80#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
81#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
82#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
83#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
84#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
85#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
86#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
87#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
88#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
89#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
90
91enum pwrap_regs {
92 PWRAP_MUX_SEL,
93 PWRAP_WRAP_EN,
94 PWRAP_DIO_EN,
95 PWRAP_SIDLY,
96 PWRAP_CSHEXT_WRITE,
97 PWRAP_CSHEXT_READ,
98 PWRAP_CSLEXT_START,
99 PWRAP_CSLEXT_END,
100 PWRAP_STAUPD_PRD,
101 PWRAP_STAUPD_GRPEN,
102 PWRAP_STAUPD_MAN_TRIG,
103 PWRAP_STAUPD_STA,
104 PWRAP_WRAP_STA,
105 PWRAP_HARB_INIT,
106 PWRAP_HARB_HPRIO,
107 PWRAP_HIPRIO_ARB_EN,
108 PWRAP_HARB_STA0,
109 PWRAP_HARB_STA1,
110 PWRAP_MAN_EN,
111 PWRAP_MAN_CMD,
112 PWRAP_MAN_RDATA,
113 PWRAP_MAN_VLDCLR,
114 PWRAP_WACS0_EN,
115 PWRAP_INIT_DONE0,
116 PWRAP_WACS0_CMD,
117 PWRAP_WACS0_RDATA,
118 PWRAP_WACS0_VLDCLR,
119 PWRAP_WACS1_EN,
120 PWRAP_INIT_DONE1,
121 PWRAP_WACS1_CMD,
122 PWRAP_WACS1_RDATA,
123 PWRAP_WACS1_VLDCLR,
124 PWRAP_WACS2_EN,
125 PWRAP_INIT_DONE2,
126 PWRAP_WACS2_CMD,
127 PWRAP_WACS2_RDATA,
128 PWRAP_WACS2_VLDCLR,
129 PWRAP_INT_EN,
130 PWRAP_INT_FLG_RAW,
131 PWRAP_INT_FLG,
132 PWRAP_INT_CLR,
133 PWRAP_SIG_ADR,
134 PWRAP_SIG_MODE,
135 PWRAP_SIG_VALUE,
136 PWRAP_SIG_ERRVAL,
137 PWRAP_CRC_EN,
138 PWRAP_TIMER_EN,
139 PWRAP_TIMER_STA,
140 PWRAP_WDT_UNIT,
141 PWRAP_WDT_SRC_EN,
142 PWRAP_WDT_FLG,
143 PWRAP_DEBUG_INT_SEL,
144 PWRAP_CIPHER_KEY_SEL,
145 PWRAP_CIPHER_IV_SEL,
146 PWRAP_CIPHER_RDY,
147 PWRAP_CIPHER_MODE,
148 PWRAP_CIPHER_SWRST,
149 PWRAP_DCM_EN,
150 PWRAP_DCM_DBC_PRD,
151
152 /* MT8135 only regs */
153 PWRAP_CSHEXT,
154 PWRAP_EVENT_IN_EN,
155 PWRAP_EVENT_DST_EN,
156 PWRAP_RRARB_INIT,
157 PWRAP_RRARB_EN,
158 PWRAP_RRARB_STA0,
159 PWRAP_RRARB_STA1,
160 PWRAP_EVENT_STA,
161 PWRAP_EVENT_STACLR,
162 PWRAP_CIPHER_LOAD,
163 PWRAP_CIPHER_START,
164
165 /* MT8173 only regs */
166 PWRAP_RDDMY,
167 PWRAP_SI_CK_CON,
168 PWRAP_DVFS_ADR0,
169 PWRAP_DVFS_WDATA0,
170 PWRAP_DVFS_ADR1,
171 PWRAP_DVFS_WDATA1,
172 PWRAP_DVFS_ADR2,
173 PWRAP_DVFS_WDATA2,
174 PWRAP_DVFS_ADR3,
175 PWRAP_DVFS_WDATA3,
176 PWRAP_DVFS_ADR4,
177 PWRAP_DVFS_WDATA4,
178 PWRAP_DVFS_ADR5,
179 PWRAP_DVFS_WDATA5,
180 PWRAP_DVFS_ADR6,
181 PWRAP_DVFS_WDATA6,
182 PWRAP_DVFS_ADR7,
183 PWRAP_DVFS_WDATA7,
184 PWRAP_SPMINF_STA,
185 PWRAP_CIPHER_EN,
186};
187
188static int mt8173_regs[] = {
189 [PWRAP_MUX_SEL] = 0x0,
190 [PWRAP_WRAP_EN] = 0x4,
191 [PWRAP_DIO_EN] = 0x8,
192 [PWRAP_SIDLY] = 0xc,
193 [PWRAP_RDDMY] = 0x10,
194 [PWRAP_SI_CK_CON] = 0x14,
195 [PWRAP_CSHEXT_WRITE] = 0x18,
196 [PWRAP_CSHEXT_READ] = 0x1c,
197 [PWRAP_CSLEXT_START] = 0x20,
198 [PWRAP_CSLEXT_END] = 0x24,
199 [PWRAP_STAUPD_PRD] = 0x28,
200 [PWRAP_STAUPD_GRPEN] = 0x2c,
201 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
202 [PWRAP_STAUPD_STA] = 0x44,
203 [PWRAP_WRAP_STA] = 0x48,
204 [PWRAP_HARB_INIT] = 0x4c,
205 [PWRAP_HARB_HPRIO] = 0x50,
206 [PWRAP_HIPRIO_ARB_EN] = 0x54,
207 [PWRAP_HARB_STA0] = 0x58,
208 [PWRAP_HARB_STA1] = 0x5c,
209 [PWRAP_MAN_EN] = 0x60,
210 [PWRAP_MAN_CMD] = 0x64,
211 [PWRAP_MAN_RDATA] = 0x68,
212 [PWRAP_MAN_VLDCLR] = 0x6c,
213 [PWRAP_WACS0_EN] = 0x70,
214 [PWRAP_INIT_DONE0] = 0x74,
215 [PWRAP_WACS0_CMD] = 0x78,
216 [PWRAP_WACS0_RDATA] = 0x7c,
217 [PWRAP_WACS0_VLDCLR] = 0x80,
218 [PWRAP_WACS1_EN] = 0x84,
219 [PWRAP_INIT_DONE1] = 0x88,
220 [PWRAP_WACS1_CMD] = 0x8c,
221 [PWRAP_WACS1_RDATA] = 0x90,
222 [PWRAP_WACS1_VLDCLR] = 0x94,
223 [PWRAP_WACS2_EN] = 0x98,
224 [PWRAP_INIT_DONE2] = 0x9c,
225 [PWRAP_WACS2_CMD] = 0xa0,
226 [PWRAP_WACS2_RDATA] = 0xa4,
227 [PWRAP_WACS2_VLDCLR] = 0xa8,
228 [PWRAP_INT_EN] = 0xac,
229 [PWRAP_INT_FLG_RAW] = 0xb0,
230 [PWRAP_INT_FLG] = 0xb4,
231 [PWRAP_INT_CLR] = 0xb8,
232 [PWRAP_SIG_ADR] = 0xbc,
233 [PWRAP_SIG_MODE] = 0xc0,
234 [PWRAP_SIG_VALUE] = 0xc4,
235 [PWRAP_SIG_ERRVAL] = 0xc8,
236 [PWRAP_CRC_EN] = 0xcc,
237 [PWRAP_TIMER_EN] = 0xd0,
238 [PWRAP_TIMER_STA] = 0xd4,
239 [PWRAP_WDT_UNIT] = 0xd8,
240 [PWRAP_WDT_SRC_EN] = 0xdc,
241 [PWRAP_WDT_FLG] = 0xe0,
242 [PWRAP_DEBUG_INT_SEL] = 0xe4,
243 [PWRAP_DVFS_ADR0] = 0xe8,
244 [PWRAP_DVFS_WDATA0] = 0xec,
245 [PWRAP_DVFS_ADR1] = 0xf0,
246 [PWRAP_DVFS_WDATA1] = 0xf4,
247 [PWRAP_DVFS_ADR2] = 0xf8,
248 [PWRAP_DVFS_WDATA2] = 0xfc,
249 [PWRAP_DVFS_ADR3] = 0x100,
250 [PWRAP_DVFS_WDATA3] = 0x104,
251 [PWRAP_DVFS_ADR4] = 0x108,
252 [PWRAP_DVFS_WDATA4] = 0x10c,
253 [PWRAP_DVFS_ADR5] = 0x110,
254 [PWRAP_DVFS_WDATA5] = 0x114,
255 [PWRAP_DVFS_ADR6] = 0x118,
256 [PWRAP_DVFS_WDATA6] = 0x11c,
257 [PWRAP_DVFS_ADR7] = 0x120,
258 [PWRAP_DVFS_WDATA7] = 0x124,
259 [PWRAP_SPMINF_STA] = 0x128,
260 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
261 [PWRAP_CIPHER_IV_SEL] = 0x130,
262 [PWRAP_CIPHER_EN] = 0x134,
263 [PWRAP_CIPHER_RDY] = 0x138,
264 [PWRAP_CIPHER_MODE] = 0x13c,
265 [PWRAP_CIPHER_SWRST] = 0x140,
266 [PWRAP_DCM_EN] = 0x144,
267 [PWRAP_DCM_DBC_PRD] = 0x148,
268};
269
270static int mt8135_regs[] = {
271 [PWRAP_MUX_SEL] = 0x0,
272 [PWRAP_WRAP_EN] = 0x4,
273 [PWRAP_DIO_EN] = 0x8,
274 [PWRAP_SIDLY] = 0xc,
275 [PWRAP_CSHEXT] = 0x10,
276 [PWRAP_CSHEXT_WRITE] = 0x14,
277 [PWRAP_CSHEXT_READ] = 0x18,
278 [PWRAP_CSLEXT_START] = 0x1c,
279 [PWRAP_CSLEXT_END] = 0x20,
280 [PWRAP_STAUPD_PRD] = 0x24,
281 [PWRAP_STAUPD_GRPEN] = 0x28,
282 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
283 [PWRAP_STAUPD_STA] = 0x30,
284 [PWRAP_EVENT_IN_EN] = 0x34,
285 [PWRAP_EVENT_DST_EN] = 0x38,
286 [PWRAP_WRAP_STA] = 0x3c,
287 [PWRAP_RRARB_INIT] = 0x40,
288 [PWRAP_RRARB_EN] = 0x44,
289 [PWRAP_RRARB_STA0] = 0x48,
290 [PWRAP_RRARB_STA1] = 0x4c,
291 [PWRAP_HARB_INIT] = 0x50,
292 [PWRAP_HARB_HPRIO] = 0x54,
293 [PWRAP_HIPRIO_ARB_EN] = 0x58,
294 [PWRAP_HARB_STA0] = 0x5c,
295 [PWRAP_HARB_STA1] = 0x60,
296 [PWRAP_MAN_EN] = 0x64,
297 [PWRAP_MAN_CMD] = 0x68,
298 [PWRAP_MAN_RDATA] = 0x6c,
299 [PWRAP_MAN_VLDCLR] = 0x70,
300 [PWRAP_WACS0_EN] = 0x74,
301 [PWRAP_INIT_DONE0] = 0x78,
302 [PWRAP_WACS0_CMD] = 0x7c,
303 [PWRAP_WACS0_RDATA] = 0x80,
304 [PWRAP_WACS0_VLDCLR] = 0x84,
305 [PWRAP_WACS1_EN] = 0x88,
306 [PWRAP_INIT_DONE1] = 0x8c,
307 [PWRAP_WACS1_CMD] = 0x90,
308 [PWRAP_WACS1_RDATA] = 0x94,
309 [PWRAP_WACS1_VLDCLR] = 0x98,
310 [PWRAP_WACS2_EN] = 0x9c,
311 [PWRAP_INIT_DONE2] = 0xa0,
312 [PWRAP_WACS2_CMD] = 0xa4,
313 [PWRAP_WACS2_RDATA] = 0xa8,
314 [PWRAP_WACS2_VLDCLR] = 0xac,
315 [PWRAP_INT_EN] = 0xb0,
316 [PWRAP_INT_FLG_RAW] = 0xb4,
317 [PWRAP_INT_FLG] = 0xb8,
318 [PWRAP_INT_CLR] = 0xbc,
319 [PWRAP_SIG_ADR] = 0xc0,
320 [PWRAP_SIG_MODE] = 0xc4,
321 [PWRAP_SIG_VALUE] = 0xc8,
322 [PWRAP_SIG_ERRVAL] = 0xcc,
323 [PWRAP_CRC_EN] = 0xd0,
324 [PWRAP_EVENT_STA] = 0xd4,
325 [PWRAP_EVENT_STACLR] = 0xd8,
326 [PWRAP_TIMER_EN] = 0xdc,
327 [PWRAP_TIMER_STA] = 0xe0,
328 [PWRAP_WDT_UNIT] = 0xe4,
329 [PWRAP_WDT_SRC_EN] = 0xe8,
330 [PWRAP_WDT_FLG] = 0xec,
331 [PWRAP_DEBUG_INT_SEL] = 0xf0,
332 [PWRAP_CIPHER_KEY_SEL] = 0x134,
333 [PWRAP_CIPHER_IV_SEL] = 0x138,
334 [PWRAP_CIPHER_LOAD] = 0x13c,
335 [PWRAP_CIPHER_START] = 0x140,
336 [PWRAP_CIPHER_RDY] = 0x144,
337 [PWRAP_CIPHER_MODE] = 0x148,
338 [PWRAP_CIPHER_SWRST] = 0x14c,
339 [PWRAP_DCM_EN] = 0x15c,
340 [PWRAP_DCM_DBC_PRD] = 0x160,
341};
342
343enum pwrap_type {
344 PWRAP_MT8135,
345 PWRAP_MT8173,
346};
347
348struct pmic_wrapper_type {
349 int *regs;
350 enum pwrap_type type;
351 u32 arb_en_all;
352};
353
354static struct pmic_wrapper_type pwrap_mt8135 = {
355 .regs = mt8135_regs,
356 .type = PWRAP_MT8135,
357 .arb_en_all = 0x1ff,
358};
359
360static struct pmic_wrapper_type pwrap_mt8173 = {
361 .regs = mt8173_regs,
362 .type = PWRAP_MT8173,
363 .arb_en_all = 0x3f,
364};
365
366struct pmic_wrapper {
367 struct device *dev;
368 void __iomem *base;
369 struct regmap *regmap;
370 int *regs;
371 enum pwrap_type type;
372 u32 arb_en_all;
373 struct clk *clk_spi;
374 struct clk *clk_wrap;
375 struct reset_control *rstc;
376
377 struct reset_control *rstc_bridge;
378 void __iomem *bridge_base;
379};
380
381static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
382{
383 return wrp->type == PWRAP_MT8135;
384}
385
386static inline int pwrap_is_mt8173(struct pmic_wrapper *wrp)
387{
388 return wrp->type == PWRAP_MT8173;
389}
390
391static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
392{
393 return readl(wrp->base + wrp->regs[reg]);
394}
395
396static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
397{
398 writel(val, wrp->base + wrp->regs[reg]);
399}
400
401static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
402{
403 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
404
405 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
406}
407
408static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
409{
410 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
411
412 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
413}
414
415static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
416{
417 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
418}
419
420static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
421{
422 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
423
424 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
425 (val & PWRAP_STATE_SYNC_IDLE0);
426}
427
428static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
429 bool (*fp)(struct pmic_wrapper *))
430{
431 unsigned long timeout;
432
433 timeout = jiffies + usecs_to_jiffies(255);
434
435 do {
436 if (time_after(jiffies, timeout))
437 return fp(wrp) ? 0 : -ETIMEDOUT;
438 if (fp(wrp))
439 return 0;
440 } while (1);
441}
442
443static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
444{
445 int ret;
446 u32 val;
447
448 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
449 if (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR)
450 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
451
452 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
453 if (ret)
454 return ret;
455
456 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
457 PWRAP_WACS2_CMD);
458
459 return 0;
460}
461
462static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
463{
464 int ret;
465 u32 val;
466
467 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
468 if (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR)
469 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
470
471 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
472 if (ret)
473 return ret;
474
475 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
476
477 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
478 if (ret)
479 return ret;
480
481 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
482
483 return 0;
484}
485
486static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
487{
488 return pwrap_read(context, adr, rdata);
489}
490
491static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
492{
493 return pwrap_write(context, adr, wdata);
494}
495
496static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
497{
498 int ret, i;
499
500 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
501 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
502 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
503 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
504 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
505
506 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSL,
507 PWRAP_MAN_CMD);
508 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
509 PWRAP_MAN_CMD);
510 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSH,
511 PWRAP_MAN_CMD);
512
513 for (i = 0; i < 4; i++)
514 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
515 PWRAP_MAN_CMD);
516
517 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
518 if (ret) {
519 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
520 return ret;
521 }
522
523 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
524 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
525
526 return 0;
527}
528
529/*
530 * pwrap_init_sidly - configure serial input delay
531 *
532 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
533 * delay. Do a read test with all possible values and chose the best delay.
534 */
535static int pwrap_init_sidly(struct pmic_wrapper *wrp)
536{
537 u32 rdata;
538 u32 i;
539 u32 pass = 0;
540 signed char dly[16] = {
541 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
542 };
543
544 for (i = 0; i < 4; i++) {
545 pwrap_writel(wrp, i, PWRAP_SIDLY);
546 pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
547 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
548 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
549 pass |= 1 << i;
550 }
551 }
552
553 if (dly[pass] < 0) {
554 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
555 pass);
556 return -EIO;
557 }
558
559 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
560
561 return 0;
562}
563
564static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
565{
Flora Fu1f022d82015-03-17 11:14:34 +0100[diff] [blame]566 unsigned long rate_spi;
567 int ck_mhz;
568
569 rate_spi = clk_get_rate(wrp->clk_spi);
570
571 if (rate_spi > 26000000)
572 ck_mhz = 26;
573 else if (rate_spi > 18000000)
574 ck_mhz = 18;
575 else
576 ck_mhz = 0;
577
578 switch (ck_mhz) {
579 case 18:
580 if (pwrap_is_mt8135(wrp))
581 pwrap_writel(wrp, 0xc, PWRAP_CSHEXT);
582 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
583 pwrap_writel(wrp, 0xc, PWRAP_CSHEXT_READ);
584 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
585 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
586 break;
587 case 26:
588 if (pwrap_is_mt8135(wrp))
589 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
590 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
591 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
592 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
593 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
594 break;
595 case 0:
596 if (pwrap_is_mt8135(wrp))
597 pwrap_writel(wrp, 0xf, PWRAP_CSHEXT);
598 pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_WRITE);
599 pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_READ);
600 pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_START);
601 pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_END);
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 return 0;
608}
609
610static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
611{
612 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
613}
614
615static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
616{
617 u32 rdata;
618 int ret;
619
620 ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
621 if (ret)
622 return 0;
623
624 return rdata == 1;
625}
626
627static int pwrap_init_cipher(struct pmic_wrapper *wrp)
628{
629 int ret;
630 u32 rdata;
631
632 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
633 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
634 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
635 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
636
637 if (pwrap_is_mt8135(wrp)) {
638 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
639 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
640 } else {
641 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
642 }
643
644 /* Config cipher mode @PMIC */
645 pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
646 pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
647 pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
648 pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
649 pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
650 pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
651
652 /* wait for cipher data ready@AP */
653 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
654 if (ret) {
655 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
656 return ret;
657 }
658
659 /* wait for cipher data ready@PMIC */
660 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
661 if (ret) {
662 dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
663 return ret;
664 }
665
666 /* wait for cipher mode idle */
667 pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
668 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
669 if (ret) {
670 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
671 return ret;
672 }
673
674 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
675
676 /* Write Test */
677 if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
678 pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
679 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
680 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
681 return -EFAULT;
682 }
683
684 return 0;
685}
686
687static int pwrap_init(struct pmic_wrapper *wrp)
688{
689 int ret;
690 u32 rdata;
691
692 reset_control_reset(wrp->rstc);
693 if (wrp->rstc_bridge)
694 reset_control_reset(wrp->rstc_bridge);
695
696 if (pwrap_is_mt8173(wrp)) {
697 /* Enable DCM */
698 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
699 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
700 }
701
702 /* Reset SPI slave */
703 ret = pwrap_reset_spislave(wrp);
704 if (ret)
705 return ret;
706
707 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
708
709 pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
710
711 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
712
713 ret = pwrap_init_reg_clock(wrp);
714 if (ret)
715 return ret;
716
717 /* Setup serial input delay */
718 ret = pwrap_init_sidly(wrp);
719 if (ret)
720 return ret;
721
722 /* Enable dual IO mode */
723 pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
724
725 /* Check IDLE & INIT_DONE in advance */
726 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
727 if (ret) {
728 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
729 return ret;
730 }
731
732 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
733
734 /* Read Test */
735 pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
736 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
737 dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
738 PWRAP_DEW_READ_TEST_VAL, rdata);
739 return -EFAULT;
740 }
741
742 /* Enable encryption */
743 ret = pwrap_init_cipher(wrp);
744 if (ret)
745 return ret;
746
747 /* Signature checking - using CRC */
748 if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
749 return -EFAULT;
750
751 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
752 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
753 pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
754 pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
755
756 if (pwrap_is_mt8135(wrp))
757 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
758
759 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
760 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
761 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
762 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
763 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
764 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
765 pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);
766 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
767 pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
768
769 if (pwrap_is_mt8135(wrp)) {
770 /* enable pwrap events and pwrap bridge in AP side */
771 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
772 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
773 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
774 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
775 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
776 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
777 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
778 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
779 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
780
781 /* enable PMIC event out and sources */
782 if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
783 pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
784 dev_err(wrp->dev, "enable dewrap fail\n");
785 return -EFAULT;
786 }
787 } else {
788 /* PMIC_DEWRAP enables */
789 if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
790 pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
791 dev_err(wrp->dev, "enable dewrap fail\n");
792 return -EFAULT;
793 }
794 }
795
796 /* Setup the init done registers */
797 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
798 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
799 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
800
801 if (pwrap_is_mt8135(wrp)) {
802 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
803 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
804 }
805
806 return 0;
807}
808
809static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
810{
811 u32 rdata;
812 struct pmic_wrapper *wrp = dev_id;
813
814 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
815
816 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
817
818 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
819
820 return IRQ_HANDLED;
821}
822
823static const struct regmap_config pwrap_regmap_config = {
824 .reg_bits = 16,
825 .val_bits = 16,
826 .reg_stride = 2,
827 .reg_read = pwrap_regmap_read,
828 .reg_write = pwrap_regmap_write,
829 .max_register = 0xffff,
830};
831
832static struct of_device_id of_pwrap_match_tbl[] = {
833 {
834 .compatible = "mediatek,mt8135-pwrap",
835 .data = &pwrap_mt8135,
836 }, {
837 .compatible = "mediatek,mt8173-pwrap",
838 .data = &pwrap_mt8173,
839 }, {
840 /* sentinel */
841 }
842};
843MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
844
845static int pwrap_probe(struct platform_device *pdev)
846{
847 int ret, irq;
848 struct pmic_wrapper *wrp;
849 struct device_node *np = pdev->dev.of_node;
850 const struct of_device_id *of_id =
851 of_match_device(of_pwrap_match_tbl, &pdev->dev);
852 const struct pmic_wrapper_type *type;
853 struct resource *res;
854
855 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
856 if (!wrp)
857 return -ENOMEM;
858
859 platform_set_drvdata(pdev, wrp);
860
861 type = of_id->data;
862 wrp->regs = type->regs;
863 wrp->type = type->type;
864 wrp->arb_en_all = type->arb_en_all;
865 wrp->dev = &pdev->dev;
866
867 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
868 wrp->base = devm_ioremap_resource(wrp->dev, res);
869 if (IS_ERR(wrp->base))
870 return PTR_ERR(wrp->base);
871
872 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
873 if (IS_ERR(wrp->rstc)) {
874 ret = PTR_ERR(wrp->rstc);
875 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
876 return ret;
877 }
878
879 if (pwrap_is_mt8135(wrp)) {
880 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
881 "pwrap-bridge");
882 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
883 if (IS_ERR(wrp->bridge_base))
884 return PTR_ERR(wrp->bridge_base);
885
886 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
887 if (IS_ERR(wrp->rstc_bridge)) {
888 ret = PTR_ERR(wrp->rstc_bridge);
889 dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
890 return ret;
891 }
892 }
893
894 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
895 if (IS_ERR(wrp->clk_spi)) {
896 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
897 return PTR_ERR(wrp->clk_spi);
898 }
899
900 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
901 if (IS_ERR(wrp->clk_wrap)) {
902 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
903 return PTR_ERR(wrp->clk_wrap);
904 }
905
906 ret = clk_prepare_enable(wrp->clk_spi);
907 if (ret)
908 return ret;
909
910 ret = clk_prepare_enable(wrp->clk_wrap);
911 if (ret)
912 goto err_out1;
913
914 /* Enable internal dynamic clock */
915 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
916 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
917
918 /*
919 * The PMIC could already be initialized by the bootloader.
920 * Skip initialization here in this case.
921 */
922 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
923 ret = pwrap_init(wrp);
924 if (ret) {
925 dev_dbg(wrp->dev, "init failed with %d\n", ret);
926 goto err_out2;
927 }
928 }
929
930 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
931 dev_dbg(wrp->dev, "initialization isn't finished\n");
932 return -ENODEV;
933 }
934
935 irq = platform_get_irq(pdev, 0);
936 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
937 "mt-pmic-pwrap", wrp);
938 if (ret)
939 goto err_out2;
940
941 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
942 if (IS_ERR(wrp->regmap))
943 return PTR_ERR(wrp->regmap);
944
945 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
946 if (ret) {
947 dev_dbg(wrp->dev, "failed to create child devices at %s\n",
948 np->full_name);
949 goto err_out2;
950 }
951
952 return 0;
953
954err_out2:
955 clk_disable_unprepare(wrp->clk_wrap);
956err_out1:
957 clk_disable_unprepare(wrp->clk_spi);
958
959 return ret;
960}
961
962static struct platform_driver pwrap_drv = {
963 .driver = {
964 .name = "mt-pmic-pwrap",
965 .owner = THIS_MODULE,
966 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
967 },
968 .probe = pwrap_probe,
969};
970
971module_platform_driver(pwrap_drv);
972
973MODULE_AUTHOR("Flora Fu, MediaTek");
974MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
975MODULE_LICENSE("GPL v2");