Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Intel CE4100 platform specific setup code |
| 3 | * |
| 4 | * (C) Copyright 2010 Intel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; version 2 |
| 9 | * of the License. |
| 10 | */ |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/irq.h> |
| 14 | #include <linux/module.h> |
Dirk Brandewie | 5ec6960 | 2010-11-22 06:28:48 -0800 | [diff] [blame] | 15 | #include <linux/serial_reg.h> |
| 16 | #include <linux/serial_8250.h> |
Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 17 | |
Sebastian Andrzej Siewior | 0315017 | 2011-03-14 10:33:40 +0100 | [diff] [blame] | 18 | #include <asm/ce4100.h> |
Sebastian Andrzej Siewior | 1fa4163 | 2011-02-22 21:07:45 +0100 | [diff] [blame] | 19 | #include <asm/prom.h> |
Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 20 | #include <asm/setup.h> |
Sebastian Andrzej Siewior | 1fa4163 | 2011-02-22 21:07:45 +0100 | [diff] [blame] | 21 | #include <asm/i8259.h> |
Dirk Brandewie | 5ec6960 | 2010-11-22 06:28:48 -0800 | [diff] [blame] | 22 | #include <asm/io.h> |
Sebastian Andrzej Siewior | 1fa4163 | 2011-02-22 21:07:45 +0100 | [diff] [blame] | 23 | #include <asm/io_apic.h> |
Maxime Bizon | d795991 | 2012-10-29 14:40:19 +0100 | [diff] [blame] | 24 | #include <asm/emergency-restart.h> |
Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 25 | |
| 26 | static int ce4100_i8042_detect(void) |
| 27 | { |
| 28 | return 0; |
| 29 | } |
| 30 | |
Florian Fainelli | f49f4ab | 2012-10-29 14:40:18 +0100 | [diff] [blame] | 31 | /* |
| 32 | * The CE4100 platform has an internal 8051 Microcontroller which is |
| 33 | * responsible for signaling to the external Power Management Unit the |
| 34 | * intention to reset, reboot or power off the system. This 8051 device has |
| 35 | * its command register mapped at I/O port 0xcf9 and the value 0x4 is used |
| 36 | * to power off the system. |
| 37 | */ |
| 38 | static void ce4100_power_off(void) |
| 39 | { |
| 40 | outb(0x4, 0xcf9); |
| 41 | } |
| 42 | |
Dirk Brandewie | 5ec6960 | 2010-11-22 06:28:48 -0800 | [diff] [blame] | 43 | #ifdef CONFIG_SERIAL_8250 |
| 44 | |
Dirk Brandewie | 5ec6960 | 2010-11-22 06:28:48 -0800 | [diff] [blame] | 45 | static unsigned int mem_serial_in(struct uart_port *p, int offset) |
Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 46 | { |
Dirk Brandewie | 5ec6960 | 2010-11-22 06:28:48 -0800 | [diff] [blame] | 47 | offset = offset << p->regshift; |
| 48 | return readl(p->membase + offset); |
| 49 | } |
| 50 | |
| 51 | /* |
| 52 | * The UART Tx interrupts are not set under some conditions and therefore serial |
| 53 | * transmission hangs. This is a silicon issue and has not been root caused. The |
| 54 | * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT |
| 55 | * bit of LSR register in interrupt handler to see whether at least one of these |
| 56 | * two bits is set, if so then process the transmit request. If this workaround |
| 57 | * is not applied, then the serial transmission may hang. This workaround is for |
| 58 | * errata number 9 in Errata - B step. |
| 59 | */ |
| 60 | |
| 61 | static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset) |
| 62 | { |
| 63 | unsigned int ret, ier, lsr; |
| 64 | |
| 65 | if (offset == UART_IIR) { |
| 66 | offset = offset << p->regshift; |
| 67 | ret = readl(p->membase + offset); |
| 68 | if (ret & UART_IIR_NO_INT) { |
| 69 | /* see if the TX interrupt should have really set */ |
| 70 | ier = mem_serial_in(p, UART_IER); |
| 71 | /* see if the UART's XMIT interrupt is enabled */ |
| 72 | if (ier & UART_IER_THRI) { |
| 73 | lsr = mem_serial_in(p, UART_LSR); |
| 74 | /* now check to see if the UART should be |
| 75 | generating an interrupt (but isn't) */ |
| 76 | if (lsr & (UART_LSR_THRE | UART_LSR_TEMT)) |
| 77 | ret &= ~UART_IIR_NO_INT; |
| 78 | } |
| 79 | } |
| 80 | } else |
| 81 | ret = mem_serial_in(p, offset); |
| 82 | return ret; |
| 83 | } |
| 84 | |
| 85 | static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value) |
| 86 | { |
| 87 | offset = offset << p->regshift; |
| 88 | writel(value, p->membase + offset); |
| 89 | } |
| 90 | |
| 91 | static void ce4100_serial_fixup(int port, struct uart_port *up, |
| 92 | unsigned short *capabilites) |
| 93 | { |
| 94 | #ifdef CONFIG_EARLY_PRINTK |
| 95 | /* |
| 96 | * Over ride the legacy port configuration that comes from |
| 97 | * asm/serial.h. Using the ioport driver then switching to the |
| 98 | * PCI memmaped driver hangs the IOAPIC |
| 99 | */ |
| 100 | if (up->iotype != UPIO_MEM32) { |
| 101 | up->uartclk = 14745600; |
| 102 | up->mapbase = 0xdffe0200; |
| 103 | set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, |
| 104 | up->mapbase & PAGE_MASK); |
| 105 | up->membase = |
| 106 | (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE); |
| 107 | up->membase += up->mapbase & ~PAGE_MASK; |
| 108 | up->iotype = UPIO_MEM32; |
| 109 | up->regshift = 2; |
| 110 | } |
| 111 | #endif |
| 112 | up->iobase = 0; |
| 113 | up->serial_in = ce4100_mem_serial_in; |
| 114 | up->serial_out = ce4100_mem_serial_out; |
| 115 | |
| 116 | *capabilites |= (1 << 12); |
| 117 | } |
| 118 | |
| 119 | static __init void sdv_serial_fixup(void) |
| 120 | { |
| 121 | serial8250_set_isa_configurator(ce4100_serial_fixup); |
| 122 | } |
| 123 | |
| 124 | #else |
Zhang Rui | f2ee442 | 2011-11-10 13:21:10 +0000 | [diff] [blame] | 125 | static inline void sdv_serial_fixup(void) {}; |
Dirk Brandewie | 5ec6960 | 2010-11-22 06:28:48 -0800 | [diff] [blame] | 126 | #endif |
| 127 | |
| 128 | static void __init sdv_arch_setup(void) |
| 129 | { |
| 130 | sdv_serial_fixup(); |
Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 131 | } |
| 132 | |
Sebastian Andrzej Siewior | 1fa4163 | 2011-02-22 21:07:45 +0100 | [diff] [blame] | 133 | #ifdef CONFIG_X86_IO_APIC |
| 134 | static void __cpuinit sdv_pci_init(void) |
| 135 | { |
| 136 | x86_of_pci_init(); |
| 137 | /* We can't set this earlier, because we need to calibrate the timer */ |
| 138 | legacy_pic = &null_legacy_pic; |
| 139 | } |
| 140 | #endif |
| 141 | |
Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 142 | /* |
| 143 | * CE4100 specific x86_init function overrides and early setup |
| 144 | * calls. |
| 145 | */ |
| 146 | void __init x86_ce4100_early_setup(void) |
| 147 | { |
| 148 | x86_init.oem.arch_setup = sdv_arch_setup; |
| 149 | x86_platform.i8042_detect = ce4100_i8042_detect; |
| 150 | x86_init.resources.probe_roms = x86_init_noop; |
| 151 | x86_init.mpparse.get_smp_config = x86_init_uint_noop; |
Thomas Gleixner | a906fda | 2011-02-25 16:09:31 +0100 | [diff] [blame] | 152 | x86_init.mpparse.find_smp_config = x86_init_noop; |
Sebastian Andrzej Siewior | 0315017 | 2011-03-14 10:33:40 +0100 | [diff] [blame] | 153 | x86_init.pci.init = ce4100_pci_init; |
Sebastian Andrzej Siewior | 1fa4163 | 2011-02-22 21:07:45 +0100 | [diff] [blame] | 154 | |
Maxime Bizon | d795991 | 2012-10-29 14:40:19 +0100 | [diff] [blame] | 155 | /* |
| 156 | * By default, the reboot method is ACPI which is supported by the |
| 157 | * CE4100 bootloader CEFDK using FADT.ResetReg Address and ResetValue |
| 158 | * the bootloader will however issue a system power off instead of |
| 159 | * reboot. By using BOOT_KBD we ensure proper system reboot as |
| 160 | * expected. |
| 161 | */ |
| 162 | reboot_type = BOOT_KBD; |
| 163 | |
Sebastian Andrzej Siewior | 1fa4163 | 2011-02-22 21:07:45 +0100 | [diff] [blame] | 164 | #ifdef CONFIG_X86_IO_APIC |
| 165 | x86_init.pci.init_irq = sdv_pci_init; |
| 166 | x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck; |
| 167 | #endif |
Florian Fainelli | f49f4ab | 2012-10-29 14:40:18 +0100 | [diff] [blame] | 168 | |
| 169 | pm_power_off = ce4100_power_off; |
Thomas Gleixner | c751e17 | 2010-11-09 12:08:04 -0800 | [diff] [blame] | 170 | } |