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gerrit-public.fairphone.software / kernel / msm-4.9 / 9557656200d685a6e92fb09c8d26ef7d7ba27026 / . / include / linux / platform_data / davinci_asp.h
blob: f3d6e4f20962e6761811758f6b32f6f09a441a21 [file] [log] [blame]
Hebbar, Gururaja896f66b2012-08-27 18:56:41 +0530[diff] [blame]1/*
2 * TI DaVinci Audio Serial Port support
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __DAVINCI_ASP_H
17#define __DAVINCI_ASP_H
18
Matt Porterb8ec56d2012-10-17 16:08:03 +0200[diff] [blame]19#include <linux/genalloc.h>
20
Hebbar, Gururaja896f66b2012-08-27 18:56:41 +0530[diff] [blame]21struct snd_platform_data {
22 u32 tx_dma_offset;
23 u32 rx_dma_offset;
24 int asp_chan_q; /* event queue number for ASP channel */
25 int ram_chan_q; /* event queue number for RAM channel */
26 unsigned int codec_fmt;
27 /*
28 * Allowing this is more efficient and eliminates left and right swaps
29 * caused by underruns, but will swap the left and right channels
30 * when compared to previous behavior.
31 */
32 unsigned enable_channel_combine:1;
33 unsigned sram_size_playback;
34 unsigned sram_size_capture;
Matt Porterb8ec56d2012-10-17 16:08:03 +0200[diff] [blame]35 struct gen_pool *sram_pool;
Hebbar, Gururaja896f66b2012-08-27 18:56:41 +0530[diff] [blame]36
37 /*
38 * If McBSP peripheral gets the clock from an external pin,
39 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
40 * and MCBSP_CLKS.
41 * Depending on different hardware connections it is possible
42 * to use this setting to change the behaviour of McBSP
43 * driver.
44 */
45 int clk_input_pin;
46
47 /*
48 * This flag works when both clock and FS are outputs for the cpu
49 * and makes clock more accurate (FS is not symmetrical and the
50 * clock is very fast.
51 * The clock becoming faster is named
52 * i2s continuous serial clock (I2S_SCK) and it is an externally
53 * visible bit clock.
54 *
55 * first line : WordSelect
56 * second line : ContinuousSerialClock
57 * third line: SerialData
58 *
59 * SYMMETRICAL APPROACH:
60 * _______________________ LEFT
61 * _| RIGHT |______________________|
62 * _ _ _ _ _ _ _ _
63 * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
64 * _ _ _ _ _ _ _ _
65 * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
66 * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
67 *
68 * ACCURATE CLOCK APPROACH:
69 * ______________ LEFT
70 * _| RIGHT |_______________________________|
71 * _ _ _ _ _ _ _ _ _
72 * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
73 * _ _ _ _ dummy cycles
74 * _/ \_ ... _/ \_/ \_ ... _/ \__________________
75 * \_/ \_/ \_/ \_/
76 *
77 */
78 bool i2s_accurate_sck;
79
80 /* McASP specific fields */
81 int tdm_slots;
82 u8 op_mode;
83 u8 num_serializer;
84 u8 *serial_dir;
85 u8 version;
86 u8 txnumevt;
87 u8 rxnumevt;
88};
89
90enum {
91 MCASP_VERSION_1 = 0, /* DM646x */
92 MCASP_VERSION_2, /* DA8xx/OMAPL1x */
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530[diff] [blame]93 MCASP_VERSION_3, /* TI81xx/AM33xx */
Hebbar, Gururaja896f66b2012-08-27 18:56:41 +0530[diff] [blame]94};
95
96enum mcbsp_clk_input_pin {
97 MCBSP_CLKR = 0, /* as in DM365 */
98 MCBSP_CLKS,
99};
100
101#define INACTIVE_MODE 0
102#define TX_MODE 1
103#define RX_MODE 2
104
105#define DAVINCI_MCASP_IIS_MODE 0
106#define DAVINCI_MCASP_DIT_MODE 1
107
108#endif