Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * drivers/pci/setup-bus.c |
| 3 | * |
| 4 | * Extruded from code written by |
| 5 | * Dave Rusling (david.rusling@reo.mts.dec.com) |
| 6 | * David Mosberger (davidm@cs.arizona.edu) |
| 7 | * David Miller (davem@redhat.com) |
| 8 | * |
| 9 | * Support routines for initializing a PCI subsystem. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
| 14 | * PCI-PCI bridges cleanup, sorted resource allocation. |
| 15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
| 16 | * Converted to allocation in 3 passes, which gives |
| 17 | * tighter packing. Prefetchable range support. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/pci.h> |
| 24 | #include <linux/errno.h> |
| 25 | #include <linux/ioport.h> |
| 26 | #include <linux/cache.h> |
| 27 | #include <linux/slab.h> |
| 28 | |
| 29 | |
| 30 | #define DEBUG_CONFIG 1 |
| 31 | #if DEBUG_CONFIG |
| 32 | #define DBG(x...) printk(x) |
| 33 | #else |
| 34 | #define DBG(x...) |
| 35 | #endif |
| 36 | |
| 37 | #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1)) |
| 38 | |
| 39 | /* |
| 40 | * FIXME: IO should be max 256 bytes. However, since we may |
| 41 | * have a P2P bridge below a cardbus bridge, we need 4K. |
| 42 | */ |
Linus Torvalds | 4196c3a | 2005-10-23 16:31:16 -0700 | [diff] [blame] | 43 | #define CARDBUS_IO_SIZE (256) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #define CARDBUS_MEM_SIZE (32*1024*1024) |
| 45 | |
| 46 | static void __devinit |
| 47 | pbus_assign_resources_sorted(struct pci_bus *bus) |
| 48 | { |
| 49 | struct pci_dev *dev; |
| 50 | struct resource *res; |
| 51 | struct resource_list head, *list, *tmp; |
| 52 | int idx; |
| 53 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | head.next = NULL; |
| 55 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 56 | u16 class = dev->class >> 8; |
| 57 | |
Kimball Murray | c0da3ba | 2006-05-31 14:20:04 -0400 | [diff] [blame] | 58 | /* Don't touch classless devices or host bridges or ioapics. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | if (class == PCI_CLASS_NOT_DEFINED || |
Kimball Murray | c0da3ba | 2006-05-31 14:20:04 -0400 | [diff] [blame] | 60 | class == PCI_CLASS_BRIDGE_HOST || |
| 61 | class == PCI_CLASS_SYSTEM_PIC) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | continue; |
| 63 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | pdev_sort_resources(dev, &head); |
| 65 | } |
| 66 | |
| 67 | for (list = head.next; list;) { |
| 68 | res = list->res; |
| 69 | idx = res - &list->dev->resource[0]; |
Rajesh Shah | 542df5d | 2005-04-28 00:25:50 -0700 | [diff] [blame] | 70 | if (pci_assign_resource(list->dev, idx)) { |
| 71 | res->start = 0; |
Ivan Kokshaysky | 960b846 | 2005-07-07 03:07:56 +0400 | [diff] [blame] | 72 | res->end = 0; |
Rajesh Shah | 542df5d | 2005-04-28 00:25:50 -0700 | [diff] [blame] | 73 | res->flags = 0; |
| 74 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | tmp = list; |
| 76 | list = list->next; |
| 77 | kfree(tmp); |
| 78 | } |
| 79 | } |
| 80 | |
Dominik Brodowski | b3743fa | 2005-09-09 13:03:23 -0700 | [diff] [blame] | 81 | void pci_setup_cardbus(struct pci_bus *bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | { |
| 83 | struct pci_dev *bridge = bus->self; |
| 84 | struct pci_bus_region region; |
| 85 | |
| 86 | printk("PCI: Bus %d, cardbus bridge: %s\n", |
| 87 | bus->number, pci_name(bridge)); |
| 88 | |
| 89 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); |
| 90 | if (bus->resource[0]->flags & IORESOURCE_IO) { |
| 91 | /* |
| 92 | * The IO resource is allocated a range twice as large as it |
| 93 | * would normally need. This allows us to set both IO regs. |
| 94 | */ |
| 95 | printk(" IO window: %08lx-%08lx\n", |
| 96 | region.start, region.end); |
| 97 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
| 98 | region.start); |
| 99 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, |
| 100 | region.end); |
| 101 | } |
| 102 | |
| 103 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); |
| 104 | if (bus->resource[1]->flags & IORESOURCE_IO) { |
| 105 | printk(" IO window: %08lx-%08lx\n", |
| 106 | region.start, region.end); |
| 107 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
| 108 | region.start); |
| 109 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, |
| 110 | region.end); |
| 111 | } |
| 112 | |
| 113 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); |
| 114 | if (bus->resource[2]->flags & IORESOURCE_MEM) { |
| 115 | printk(" PREFETCH window: %08lx-%08lx\n", |
| 116 | region.start, region.end); |
| 117 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
| 118 | region.start); |
| 119 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, |
| 120 | region.end); |
| 121 | } |
| 122 | |
| 123 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); |
| 124 | if (bus->resource[3]->flags & IORESOURCE_MEM) { |
| 125 | printk(" MEM window: %08lx-%08lx\n", |
| 126 | region.start, region.end); |
| 127 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
| 128 | region.start); |
| 129 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, |
| 130 | region.end); |
| 131 | } |
| 132 | } |
Dominik Brodowski | b3743fa | 2005-09-09 13:03:23 -0700 | [diff] [blame] | 133 | EXPORT_SYMBOL(pci_setup_cardbus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | |
| 135 | /* Initialize bridges with base/limit values we have collected. |
| 136 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) |
| 137 | requires that if there is no I/O ports or memory behind the |
| 138 | bridge, corresponding range must be turned off by writing base |
| 139 | value greater than limit to the bridge's base/limit registers. |
| 140 | |
| 141 | Note: care must be taken when updating I/O base/limit registers |
| 142 | of bridges which support 32-bit I/O. This update requires two |
| 143 | config space writes, so it's quite possible that an I/O window of |
| 144 | the bridge will have some undesirable address (e.g. 0) after the |
| 145 | first write. Ditto 64-bit prefetchable MMIO. */ |
| 146 | static void __devinit |
| 147 | pci_setup_bridge(struct pci_bus *bus) |
| 148 | { |
| 149 | struct pci_dev *bridge = bus->self; |
| 150 | struct pci_bus_region region; |
| 151 | u32 l, io_upper16; |
| 152 | |
| 153 | DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); |
| 154 | |
| 155 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
| 156 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); |
| 157 | if (bus->resource[0]->flags & IORESOURCE_IO) { |
| 158 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
| 159 | l &= 0xffff0000; |
| 160 | l |= (region.start >> 8) & 0x00f0; |
| 161 | l |= region.end & 0xf000; |
| 162 | /* Set up upper 16 bits of I/O base/limit. */ |
| 163 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); |
| 164 | DBG(KERN_INFO " IO window: %04lx-%04lx\n", |
| 165 | region.start, region.end); |
| 166 | } |
| 167 | else { |
| 168 | /* Clear upper 16 bits of I/O base/limit. */ |
| 169 | io_upper16 = 0; |
| 170 | l = 0x00f0; |
| 171 | DBG(KERN_INFO " IO window: disabled.\n"); |
| 172 | } |
| 173 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ |
| 174 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); |
| 175 | /* Update lower 16 bits of I/O base/limit. */ |
| 176 | pci_write_config_dword(bridge, PCI_IO_BASE, l); |
| 177 | /* Update upper 16 bits of I/O base/limit. */ |
| 178 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); |
| 179 | |
| 180 | /* Set up the top and bottom of the PCI Memory segment |
| 181 | for this bus. */ |
| 182 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); |
| 183 | if (bus->resource[1]->flags & IORESOURCE_MEM) { |
| 184 | l = (region.start >> 16) & 0xfff0; |
| 185 | l |= region.end & 0xfff00000; |
| 186 | DBG(KERN_INFO " MEM window: %08lx-%08lx\n", |
| 187 | region.start, region.end); |
| 188 | } |
| 189 | else { |
| 190 | l = 0x0000fff0; |
| 191 | DBG(KERN_INFO " MEM window: disabled.\n"); |
| 192 | } |
| 193 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); |
| 194 | |
| 195 | /* Clear out the upper 32 bits of PREF limit. |
| 196 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily |
| 197 | disables PREF range, which is ok. */ |
| 198 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); |
| 199 | |
| 200 | /* Set up PREF base/limit. */ |
| 201 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); |
| 202 | if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { |
| 203 | l = (region.start >> 16) & 0xfff0; |
| 204 | l |= region.end & 0xfff00000; |
| 205 | DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n", |
| 206 | region.start, region.end); |
| 207 | } |
| 208 | else { |
| 209 | l = 0x0000fff0; |
| 210 | DBG(KERN_INFO " PREFETCH window: disabled.\n"); |
| 211 | } |
| 212 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); |
| 213 | |
| 214 | /* Clear out the upper 32 bits of PREF base. */ |
| 215 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0); |
| 216 | |
| 217 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); |
| 218 | } |
| 219 | |
| 220 | /* Check whether the bridge supports optional I/O and |
| 221 | prefetchable memory ranges. If not, the respective |
| 222 | base/limit registers must be read-only and read as 0. */ |
| 223 | static void __devinit |
| 224 | pci_bridge_check_ranges(struct pci_bus *bus) |
| 225 | { |
| 226 | u16 io; |
| 227 | u32 pmem; |
| 228 | struct pci_dev *bridge = bus->self; |
| 229 | struct resource *b_res; |
| 230 | |
| 231 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
| 232 | b_res[1].flags |= IORESOURCE_MEM; |
| 233 | |
| 234 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
| 235 | if (!io) { |
| 236 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); |
| 237 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
| 238 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
| 239 | } |
| 240 | if (io) |
| 241 | b_res[0].flags |= IORESOURCE_IO; |
| 242 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
| 243 | disconnect boundary by one PCI data phase. |
| 244 | Workaround: do not use prefetching on this device. */ |
| 245 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) |
| 246 | return; |
| 247 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
| 248 | if (!pmem) { |
| 249 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, |
| 250 | 0xfff0fff0); |
| 251 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
| 252 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); |
| 253 | } |
| 254 | if (pmem) |
| 255 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 256 | } |
| 257 | |
| 258 | /* Helper function for sizing routines: find first available |
| 259 | bus resource of a given type. Note: we intentionally skip |
| 260 | the bus resources which have already been assigned (that is, |
| 261 | have non-NULL parent resource). */ |
| 262 | static struct resource * __devinit |
| 263 | find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
| 264 | { |
| 265 | int i; |
| 266 | struct resource *r; |
| 267 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
| 268 | IORESOURCE_PREFETCH; |
| 269 | |
| 270 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { |
| 271 | r = bus->resource[i]; |
Ivan Kokshaysky | 299de03 | 2005-06-15 18:59:27 +0400 | [diff] [blame] | 272 | if (r == &ioport_resource || r == &iomem_resource) |
| 273 | continue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | if (r && (r->flags & type_mask) == type && !r->parent) |
| 275 | return r; |
| 276 | } |
| 277 | return NULL; |
| 278 | } |
| 279 | |
| 280 | /* Sizing the IO windows of the PCI-PCI bridge is trivial, |
| 281 | since these windows have 4K granularity and the IO ranges |
| 282 | of non-bridge PCI devices are limited to 256 bytes. |
| 283 | We must be careful with the ISA aliasing though. */ |
| 284 | static void __devinit |
| 285 | pbus_size_io(struct pci_bus *bus) |
| 286 | { |
| 287 | struct pci_dev *dev; |
| 288 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); |
| 289 | unsigned long size = 0, size1 = 0; |
| 290 | |
| 291 | if (!b_res) |
| 292 | return; |
| 293 | |
| 294 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 295 | int i; |
| 296 | |
| 297 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 298 | struct resource *r = &dev->resource[i]; |
| 299 | unsigned long r_size; |
| 300 | |
| 301 | if (r->parent || !(r->flags & IORESOURCE_IO)) |
| 302 | continue; |
| 303 | r_size = r->end - r->start + 1; |
| 304 | |
| 305 | if (r_size < 0x400) |
| 306 | /* Might be re-aligned for ISA */ |
| 307 | size += r_size; |
| 308 | else |
| 309 | size1 += r_size; |
| 310 | } |
| 311 | } |
| 312 | /* To be fixed in 2.5: we should have sort of HAVE_ISA |
| 313 | flag in the struct pci_bus. */ |
| 314 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) |
| 315 | size = (size & 0xff) + ((size & ~0xffUL) << 2); |
| 316 | #endif |
| 317 | size = ROUND_UP(size + size1, 4096); |
| 318 | if (!size) { |
| 319 | b_res->flags = 0; |
| 320 | return; |
| 321 | } |
| 322 | /* Alignment of the IO window is always 4K */ |
| 323 | b_res->start = 4096; |
| 324 | b_res->end = b_res->start + size - 1; |
| 325 | } |
| 326 | |
| 327 | /* Calculate the size of the bus and minimal alignment which |
| 328 | guarantees that all child resources fit in this size. */ |
| 329 | static int __devinit |
| 330 | pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) |
| 331 | { |
| 332 | struct pci_dev *dev; |
| 333 | unsigned long min_align, align, size; |
| 334 | unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */ |
| 335 | int order, max_order; |
| 336 | struct resource *b_res = find_free_bus_resource(bus, type); |
| 337 | |
| 338 | if (!b_res) |
| 339 | return 0; |
| 340 | |
| 341 | memset(aligns, 0, sizeof(aligns)); |
| 342 | max_order = 0; |
| 343 | size = 0; |
| 344 | |
| 345 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 346 | int i; |
| 347 | |
| 348 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 349 | struct resource *r = &dev->resource[i]; |
| 350 | unsigned long r_size; |
| 351 | |
| 352 | if (r->parent || (r->flags & mask) != type) |
| 353 | continue; |
| 354 | r_size = r->end - r->start + 1; |
| 355 | /* For bridges size != alignment */ |
| 356 | align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; |
| 357 | order = __ffs(align) - 20; |
| 358 | if (order > 11) { |
| 359 | printk(KERN_WARNING "PCI: region %s/%d " |
| 360 | "too large: %lx-%lx\n", |
| 361 | pci_name(dev), i, r->start, r->end); |
| 362 | r->flags = 0; |
| 363 | continue; |
| 364 | } |
| 365 | size += r_size; |
| 366 | if (order < 0) |
| 367 | order = 0; |
| 368 | /* Exclude ranges with size > align from |
| 369 | calculation of the alignment. */ |
| 370 | if (r_size == align) |
| 371 | aligns[order] += align; |
| 372 | if (order > max_order) |
| 373 | max_order = order; |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | align = 0; |
| 378 | min_align = 0; |
| 379 | for (order = 0; order <= max_order; order++) { |
| 380 | unsigned long align1 = 1UL << (order + 20); |
| 381 | |
| 382 | if (!align) |
| 383 | min_align = align1; |
| 384 | else if (ROUND_UP(align + min_align, min_align) < align1) |
| 385 | min_align = align1 >> 1; |
| 386 | align += aligns[order]; |
| 387 | } |
| 388 | size = ROUND_UP(size, min_align); |
| 389 | if (!size) { |
| 390 | b_res->flags = 0; |
| 391 | return 1; |
| 392 | } |
| 393 | b_res->start = min_align; |
| 394 | b_res->end = size + min_align - 1; |
| 395 | return 1; |
| 396 | } |
| 397 | |
| 398 | static void __devinit |
| 399 | pci_bus_size_cardbus(struct pci_bus *bus) |
| 400 | { |
| 401 | struct pci_dev *bridge = bus->self; |
| 402 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
| 403 | u16 ctrl; |
| 404 | |
| 405 | /* |
| 406 | * Reserve some resources for CardBus. We reserve |
| 407 | * a fixed amount of bus space for CardBus bridges. |
| 408 | */ |
| 409 | b_res[0].start = CARDBUS_IO_SIZE; |
| 410 | b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1; |
| 411 | b_res[0].flags |= IORESOURCE_IO; |
| 412 | |
| 413 | b_res[1].start = CARDBUS_IO_SIZE; |
| 414 | b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1; |
| 415 | b_res[1].flags |= IORESOURCE_IO; |
| 416 | |
| 417 | /* |
| 418 | * Check whether prefetchable memory is supported |
| 419 | * by this bridge. |
| 420 | */ |
| 421 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
| 422 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { |
| 423 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
| 424 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); |
| 425 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
| 426 | } |
| 427 | |
| 428 | /* |
| 429 | * If we have prefetchable memory support, allocate |
| 430 | * two regions. Otherwise, allocate one region of |
| 431 | * twice the size. |
| 432 | */ |
| 433 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { |
| 434 | b_res[2].start = CARDBUS_MEM_SIZE; |
| 435 | b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1; |
| 436 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 437 | |
| 438 | b_res[3].start = CARDBUS_MEM_SIZE; |
| 439 | b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1; |
| 440 | b_res[3].flags |= IORESOURCE_MEM; |
| 441 | } else { |
| 442 | b_res[3].start = CARDBUS_MEM_SIZE * 2; |
| 443 | b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1; |
| 444 | b_res[3].flags |= IORESOURCE_MEM; |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | void __devinit |
| 449 | pci_bus_size_bridges(struct pci_bus *bus) |
| 450 | { |
| 451 | struct pci_dev *dev; |
| 452 | unsigned long mask, prefmask; |
| 453 | |
| 454 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 455 | struct pci_bus *b = dev->subordinate; |
| 456 | if (!b) |
| 457 | continue; |
| 458 | |
| 459 | switch (dev->class >> 8) { |
| 460 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 461 | pci_bus_size_cardbus(b); |
| 462 | break; |
| 463 | |
| 464 | case PCI_CLASS_BRIDGE_PCI: |
| 465 | default: |
| 466 | pci_bus_size_bridges(b); |
| 467 | break; |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | /* The root bus? */ |
| 472 | if (!bus->self) |
| 473 | return; |
| 474 | |
| 475 | switch (bus->self->class >> 8) { |
| 476 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 477 | /* don't size cardbuses yet. */ |
| 478 | break; |
| 479 | |
| 480 | case PCI_CLASS_BRIDGE_PCI: |
| 481 | pci_bridge_check_ranges(bus); |
| 482 | default: |
| 483 | pbus_size_io(bus); |
| 484 | /* If the bridge supports prefetchable range, size it |
| 485 | separately. If it doesn't, or its prefetchable window |
| 486 | has already been allocated by arch code, try |
| 487 | non-prefetchable range for both types of PCI memory |
| 488 | resources. */ |
| 489 | mask = IORESOURCE_MEM; |
| 490 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 491 | if (pbus_size_mem(bus, prefmask, prefmask)) |
| 492 | mask = prefmask; /* Success, size non-prefetch only. */ |
| 493 | pbus_size_mem(bus, mask, IORESOURCE_MEM); |
| 494 | break; |
| 495 | } |
| 496 | } |
| 497 | EXPORT_SYMBOL(pci_bus_size_bridges); |
| 498 | |
| 499 | void __devinit |
| 500 | pci_bus_assign_resources(struct pci_bus *bus) |
| 501 | { |
| 502 | struct pci_bus *b; |
| 503 | struct pci_dev *dev; |
| 504 | |
| 505 | pbus_assign_resources_sorted(bus); |
| 506 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 508 | b = dev->subordinate; |
| 509 | if (!b) |
| 510 | continue; |
| 511 | |
| 512 | pci_bus_assign_resources(b); |
| 513 | |
| 514 | switch (dev->class >> 8) { |
| 515 | case PCI_CLASS_BRIDGE_PCI: |
| 516 | pci_setup_bridge(b); |
| 517 | break; |
| 518 | |
| 519 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 520 | pci_setup_cardbus(b); |
| 521 | break; |
| 522 | |
| 523 | default: |
| 524 | printk(KERN_INFO "PCI: not setting up bridge %s " |
| 525 | "for bus %d\n", pci_name(dev), b->number); |
| 526 | break; |
| 527 | } |
| 528 | } |
| 529 | } |
| 530 | EXPORT_SYMBOL(pci_bus_assign_resources); |
| 531 | |
| 532 | void __init |
| 533 | pci_assign_unassigned_resources(void) |
| 534 | { |
| 535 | struct pci_bus *bus; |
| 536 | |
| 537 | /* Depth first, calculate sizes and alignments of all |
| 538 | subordinate buses. */ |
| 539 | list_for_each_entry(bus, &pci_root_buses, node) { |
| 540 | pci_bus_size_bridges(bus); |
| 541 | } |
| 542 | /* Depth last, allocate resources and update the hardware. */ |
| 543 | list_for_each_entry(bus, &pci_root_buses, node) { |
| 544 | pci_bus_assign_resources(bus); |
| 545 | pci_enable_bridges(bus); |
| 546 | } |
| 547 | } |