| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf533/cdefBF532.h |
| 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: |
| 7 | * Description: |
| 8 | * |
| 9 | * Rev: |
| 10 | * |
| 11 | * Modified: |
| 12 | * |
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License as published by |
| 17 | * the Free Software Foundation; either version 2, or (at your option) |
| 18 | * any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; see the file COPYING. |
| 27 | * If not, write to the Free Software Foundation, |
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 29 | */ |
| 30 | |
| 31 | #ifndef _CDEF_BF532_H |
| 32 | #define _CDEF_BF532_H |
| Mike Frysinger | 36a1548 | 2007-07-25 12:01:19 +0800 | [diff] [blame] | 33 | |
| 34 | #include <asm/blackfin.h> |
| 35 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 36 | /*include all Core registers and bit definitions*/ |
| 37 | #include "defBF532.h" |
| 38 | |
| 39 | /*include core specific register pointer definitions*/ |
| 40 | #include <asm/mach-common/cdef_LPBlackfin.h> |
| 41 | |
| 42 | #include <asm/system.h> |
| 43 | |
| 44 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ |
| 45 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 46 | #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) |
| 47 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 48 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) |
| 49 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| 50 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) |
| 51 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 52 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 53 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) |
| 54 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 55 | /* Writing to VR_CTL initiates a PLL relock sequence. */ |
| 56 | static __inline__ void bfin_write_VR_CTL(unsigned int val) |
| 57 | { |
| 58 | unsigned long flags, iwr; |
| 59 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 60 | /* Enable the PLL Wakeup bit in SIC IWR */ |
| 61 | iwr = bfin_read32(SIC_IWR); |
| 62 | /* Only allow PPL Wakeup) */ |
| 63 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); |
| Michael Hennerich | d1b945f | 2007-05-21 18:09:16 +0800 | [diff] [blame] | 64 | |
| 65 | bfin_write16(VR_CTL, val); |
| Mike Frysinger | d5148ff | 2007-07-25 11:57:42 +0800 | [diff] [blame] | 66 | SSYNC(); |
| Michael Hennerich | d1b945f | 2007-05-21 18:09:16 +0800 | [diff] [blame] | 67 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 68 | local_irq_save(flags); |
| 69 | asm("IDLE;"); |
| 70 | local_irq_restore(flags); |
| 71 | bfin_write32(SIC_IWR, iwr); |
| 72 | } |
| 73 | |
| 74 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 75 | #define bfin_read_SWRST() bfin_read16(SWRST) |
| 76 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) |
| 77 | #define bfin_read_SYSCR() bfin_read16(SYSCR) |
| 78 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 79 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
| 80 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) |
| 81 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
| 82 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) |
| 83 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) |
| 84 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) |
| 85 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) |
| 86 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) |
| 87 | #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) |
| 88 | #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) |
| 89 | #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) |
| 90 | #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val) |
| 91 | #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) |
| 92 | #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val) |
| 93 | |
| 94 | /* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ |
| 95 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) |
| 96 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val) |
| 97 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) |
| 98 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val) |
| 99 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) |
| 100 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val) |
| 101 | |
| 102 | /* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ |
| 103 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) |
| 104 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val) |
| 105 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) |
| 106 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val) |
| 107 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) |
| 108 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val) |
| 109 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) |
| 110 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val) |
| 111 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) |
| 112 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val) |
| 113 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) |
| 114 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val) |
| 115 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) |
| 116 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) |
| 117 | |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 118 | /* DMA Traffic controls */ |
| 119 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) |
| 120 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) |
| 121 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) |
| 122 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) |
| 123 | |
| 124 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
| 125 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) |
| 126 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) |
| 127 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) |
| 128 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) |
| 129 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 130 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ |
| 131 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) |
| 132 | #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 133 | #define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) |
| 134 | #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val) |
| 135 | #define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) |
| 136 | #define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val) |
| 137 | #define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) |
| 138 | #define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val) |
| 139 | #define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) |
| 140 | #define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val) |
| 141 | #define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) |
| 142 | #define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val) |
| 143 | #define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) |
| 144 | #define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val) |
| 145 | #define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) |
| 146 | #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val) |
| 147 | #define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) |
| 148 | #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val) |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 149 | #define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) |
| 150 | #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val) |
| 151 | #define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) |
| 152 | #define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val) |
| 153 | #define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) |
| 154 | #define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val) |
| 155 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) |
| 156 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) |
| 157 | |
| Michael Hennerich | 4b3f058 | 2007-09-12 14:50:28 +0800 | [diff] [blame] | 158 | |
| 159 | #if ANOMALY_05000311 |
| 160 | #define BFIN_WRITE_FIO_FLAG(name) \ |
| 161 | static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\ |
| 162 | {\ |
| 163 | unsigned long flags;\ |
| 164 | local_irq_save(flags);\ |
| 165 | bfin_write16(FIO_FLAG_ ## name,val);\ |
| 166 | bfin_read_CHIPID();\ |
| 167 | local_irq_restore(flags);\ |
| 168 | } |
| 169 | BFIN_WRITE_FIO_FLAG(D) |
| 170 | BFIN_WRITE_FIO_FLAG(C) |
| 171 | BFIN_WRITE_FIO_FLAG(S) |
| 172 | BFIN_WRITE_FIO_FLAG(T) |
| 173 | |
| 174 | #define BFIN_READ_FIO_FLAG(name) \ |
| 175 | static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\ |
| 176 | {\ |
| 177 | unsigned long flags;\ |
| 178 | unsigned short ret;\ |
| 179 | local_irq_save(flags);\ |
| 180 | ret = bfin_read16(FIO_FLAG_ ## name);\ |
| 181 | bfin_read_CHIPID();\ |
| 182 | local_irq_restore(flags);\ |
| 183 | return ret;\ |
| 184 | } |
| 185 | BFIN_READ_FIO_FLAG(D) |
| 186 | BFIN_READ_FIO_FLAG(C) |
| 187 | BFIN_READ_FIO_FLAG(S) |
| 188 | BFIN_READ_FIO_FLAG(T) |
| 189 | |
| 190 | #else |
| 191 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val) |
| 192 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val) |
| 193 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val) |
| 194 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val) |
| 195 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) |
| 196 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) |
| 197 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) |
| 198 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) |
| 199 | #endif |
| 200 | |
| 201 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 202 | /* DMA Controller */ |
| 203 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
| 204 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) |
| 205 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) |
| 206 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val) |
| 207 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) |
| 208 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val) |
| 209 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) |
| 210 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val) |
| 211 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) |
| 212 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val) |
| 213 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) |
| 214 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val) |
| 215 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) |
| 216 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val) |
| 217 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) |
| 218 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val) |
| 219 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) |
| 220 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val) |
| 221 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) |
| 222 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val) |
| 223 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) |
| 224 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val) |
| 225 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) |
| 226 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val) |
| 227 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) |
| 228 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val) |
| 229 | |
| 230 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) |
| 231 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val) |
| 232 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) |
| 233 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val) |
| 234 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) |
| 235 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val) |
| 236 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) |
| 237 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val) |
| 238 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) |
| 239 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val) |
| 240 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) |
| 241 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val) |
| 242 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) |
| 243 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val) |
| 244 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) |
| 245 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val) |
| 246 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) |
| 247 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val) |
| 248 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) |
| 249 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val) |
| 250 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) |
| 251 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val) |
| 252 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) |
| 253 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val) |
| 254 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) |
| 255 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val) |
| 256 | |
| 257 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) |
| 258 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val) |
| 259 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) |
| 260 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val) |
| 261 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) |
| 262 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val) |
| 263 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) |
| 264 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val) |
| 265 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) |
| 266 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val) |
| 267 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) |
| 268 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val) |
| 269 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) |
| 270 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val) |
| 271 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) |
| 272 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val) |
| 273 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) |
| 274 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val) |
| 275 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) |
| 276 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val) |
| 277 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) |
| 278 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val) |
| 279 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) |
| 280 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val) |
| 281 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) |
| 282 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val) |
| 283 | |
| 284 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) |
| 285 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val) |
| 286 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) |
| 287 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val) |
| 288 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) |
| 289 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val) |
| 290 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) |
| 291 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val) |
| 292 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) |
| 293 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val) |
| 294 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) |
| 295 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val) |
| 296 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) |
| 297 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val) |
| 298 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) |
| 299 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val) |
| 300 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) |
| 301 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val) |
| 302 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) |
| 303 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val) |
| 304 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) |
| 305 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val) |
| 306 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) |
| 307 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val) |
| 308 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) |
| 309 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val) |
| 310 | |
| 311 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) |
| 312 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val) |
| 313 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) |
| 314 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val) |
| 315 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) |
| 316 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val) |
| 317 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) |
| 318 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val) |
| 319 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) |
| 320 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val) |
| 321 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) |
| 322 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val) |
| 323 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) |
| 324 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val) |
| 325 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) |
| 326 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val) |
| 327 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) |
| 328 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val) |
| 329 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) |
| 330 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val) |
| 331 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) |
| 332 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val) |
| 333 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) |
| 334 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val) |
| 335 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) |
| 336 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val) |
| 337 | |
| 338 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) |
| 339 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val) |
| 340 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) |
| 341 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val) |
| 342 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) |
| 343 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val) |
| 344 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) |
| 345 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val) |
| 346 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) |
| 347 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val) |
| 348 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) |
| 349 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val) |
| 350 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) |
| 351 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val) |
| 352 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) |
| 353 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val) |
| 354 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) |
| 355 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val) |
| 356 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) |
| 357 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val) |
| 358 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) |
| 359 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val) |
| 360 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) |
| 361 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val) |
| 362 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) |
| 363 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val) |
| 364 | |
| 365 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) |
| 366 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val) |
| 367 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) |
| 368 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val) |
| 369 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) |
| 370 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val) |
| 371 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) |
| 372 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val) |
| 373 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) |
| 374 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val) |
| 375 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) |
| 376 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val) |
| 377 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) |
| 378 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val) |
| 379 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) |
| 380 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val) |
| 381 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) |
| 382 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val) |
| 383 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) |
| 384 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val) |
| 385 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) |
| 386 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val) |
| 387 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) |
| 388 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val) |
| 389 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) |
| 390 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val) |
| 391 | |
| 392 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) |
| 393 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val) |
| 394 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) |
| 395 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val) |
| 396 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) |
| 397 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val) |
| 398 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) |
| 399 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val) |
| 400 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) |
| 401 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val) |
| 402 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) |
| 403 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val) |
| 404 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) |
| 405 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val) |
| 406 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) |
| 407 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val) |
| 408 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) |
| 409 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val) |
| 410 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) |
| 411 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val) |
| 412 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) |
| 413 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val) |
| 414 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) |
| 415 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val) |
| 416 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) |
| 417 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val) |
| 418 | |
| 419 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) |
| 420 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) |
| 421 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) |
| 422 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) |
| 423 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) |
| 424 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) |
| 425 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) |
| 426 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) |
| 427 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) |
| 428 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) |
| 429 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) |
| 430 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) |
| 431 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) |
| 432 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) |
| 433 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) |
| 434 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) |
| 435 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) |
| 436 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) |
| 437 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) |
| 438 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) |
| 439 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) |
| 440 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) |
| 441 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) |
| 442 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) |
| 443 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) |
| 444 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) |
| 445 | |
| 446 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) |
| 447 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) |
| 448 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) |
| 449 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) |
| 450 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) |
| 451 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) |
| 452 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) |
| 453 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) |
| 454 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) |
| 455 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) |
| 456 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) |
| 457 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) |
| 458 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) |
| 459 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) |
| 460 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) |
| 461 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) |
| 462 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) |
| 463 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) |
| 464 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) |
| 465 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) |
| 466 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) |
| 467 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) |
| 468 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) |
| 469 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) |
| 470 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) |
| 471 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) |
| 472 | |
| 473 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) |
| 474 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) |
| 475 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) |
| 476 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) |
| 477 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) |
| 478 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) |
| 479 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) |
| 480 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) |
| 481 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) |
| 482 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) |
| 483 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) |
| 484 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) |
| 485 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) |
| 486 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) |
| 487 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) |
| 488 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) |
| 489 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) |
| 490 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) |
| 491 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) |
| 492 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) |
| 493 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) |
| 494 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) |
| 495 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) |
| 496 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) |
| 497 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) |
| 498 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) |
| 499 | |
| 500 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) |
| 501 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) |
| 502 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) |
| 503 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) |
| 504 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) |
| 505 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) |
| 506 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) |
| 507 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) |
| 508 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) |
| 509 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) |
| 510 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) |
| 511 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) |
| 512 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) |
| 513 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) |
| 514 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) |
| 515 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) |
| 516 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) |
| 517 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) |
| 518 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) |
| 519 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) |
| 520 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) |
| 521 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) |
| 522 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) |
| 523 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) |
| 524 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) |
| 525 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) |
| 526 | |
| 527 | /* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ |
| 528 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) |
| 529 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) |
| 530 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) |
| 531 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) |
| 532 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) |
| 533 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) |
| 534 | |
| 535 | /* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ |
| 536 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) |
| 537 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) |
| 538 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) |
| 539 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) |
| 540 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) |
| 541 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) |
| 542 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) |
| 543 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val) |
| 544 | |
| 545 | /* UART Controller */ |
| 546 | #define bfin_read_UART_THR() bfin_read16(UART_THR) |
| 547 | #define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) |
| 548 | #define bfin_read_UART_RBR() bfin_read16(UART_RBR) |
| 549 | #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) |
| 550 | #define bfin_read_UART_DLL() bfin_read16(UART_DLL) |
| 551 | #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) |
| 552 | #define bfin_read_UART_IER() bfin_read16(UART_IER) |
| 553 | #define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) |
| 554 | #define bfin_read_UART_DLH() bfin_read16(UART_DLH) |
| 555 | #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) |
| 556 | #define bfin_read_UART_IIR() bfin_read16(UART_IIR) |
| 557 | #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) |
| 558 | #define bfin_read_UART_LCR() bfin_read16(UART_LCR) |
| 559 | #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) |
| 560 | #define bfin_read_UART_MCR() bfin_read16(UART_MCR) |
| 561 | #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) |
| 562 | #define bfin_read_UART_LSR() bfin_read16(UART_LSR) |
| 563 | #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) |
| 564 | /* |
| 565 | #define UART_MSR |
| 566 | */ |
| 567 | #define bfin_read_UART_SCR() bfin_read16(UART_SCR) |
| 568 | #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) |
| 569 | #define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) |
| 570 | #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) |
| 571 | |
| 572 | /* SPI Controller */ |
| 573 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) |
| 574 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) |
| 575 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) |
| 576 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) |
| 577 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) |
| 578 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) |
| 579 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) |
| 580 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) |
| 581 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) |
| 582 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) |
| 583 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) |
| 584 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) |
| 585 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) |
| 586 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) |
| 587 | |
| 588 | /* TIMER 0, 1, 2 Registers */ |
| 589 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) |
| 590 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) |
| 591 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) |
| 592 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) |
| 593 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) |
| 594 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) |
| 595 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) |
| 596 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) |
| 597 | |
| 598 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) |
| 599 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) |
| 600 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) |
| 601 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) |
| 602 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) |
| 603 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) |
| 604 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) |
| 605 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) |
| 606 | |
| 607 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) |
| 608 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) |
| 609 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) |
| 610 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) |
| 611 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) |
| 612 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) |
| 613 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) |
| 614 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) |
| 615 | |
| 616 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) |
| 617 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val) |
| 618 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) |
| 619 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val) |
| 620 | #define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) |
| 621 | #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val) |
| 622 | |
| 623 | /* SPORT0 Controller */ |
| 624 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) |
| 625 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) |
| 626 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) |
| 627 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) |
| 628 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) |
| 629 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) |
| 630 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) |
| 631 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) |
| 632 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) |
| 633 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) |
| 634 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) |
| 635 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) |
| 636 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) |
| 637 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) |
| 638 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) |
| 639 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) |
| 640 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) |
| 641 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) |
| 642 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) |
| 643 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) |
| 644 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) |
| 645 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) |
| 646 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) |
| 647 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) |
| 648 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) |
| 649 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) |
| 650 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) |
| 651 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) |
| 652 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) |
| 653 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) |
| 654 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) |
| 655 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) |
| 656 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) |
| 657 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) |
| 658 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) |
| 659 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) |
| 660 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) |
| 661 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) |
| 662 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) |
| 663 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) |
| 664 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) |
| 665 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) |
| 666 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) |
| 667 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) |
| 668 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) |
| 669 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) |
| 670 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) |
| 671 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) |
| 672 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) |
| 673 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) |
| 674 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) |
| 675 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) |
| 676 | |
| 677 | /* SPORT1 Controller */ |
| 678 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) |
| 679 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) |
| 680 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) |
| 681 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) |
| 682 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) |
| 683 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) |
| 684 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) |
| 685 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) |
| 686 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) |
| 687 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) |
| 688 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) |
| 689 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) |
| 690 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) |
| 691 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) |
| 692 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) |
| 693 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) |
| 694 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) |
| 695 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) |
| 696 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) |
| 697 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) |
| 698 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) |
| 699 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) |
| 700 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) |
| 701 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) |
| 702 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) |
| 703 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) |
| 704 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) |
| 705 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) |
| 706 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) |
| 707 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) |
| 708 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) |
| 709 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) |
| 710 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) |
| 711 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) |
| 712 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) |
| 713 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) |
| 714 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) |
| 715 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) |
| 716 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) |
| 717 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) |
| 718 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) |
| 719 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) |
| 720 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) |
| 721 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) |
| 722 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) |
| 723 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) |
| 724 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) |
| 725 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) |
| 726 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) |
| 727 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) |
| 728 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) |
| 729 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) |
| 730 | |
| 731 | /* Parallel Peripheral Interface (PPI) */ |
| 732 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) |
| 733 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val) |
| 734 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) |
| 735 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val) |
| 736 | #define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() |
| 737 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) |
| 738 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val) |
| 739 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) |
| 740 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val) |
| 741 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
| 742 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) |
| 743 | |
| 744 | #endif /* _CDEF_BF532_H */ |