blob: ccf8af7717d3fc69c9cd5d57b8aafbb641520e52 [file] [log] [blame]
Florian Fainelli967dd822016-06-09 18:23:53 -07001/*
2 * B53 register definitions
3 *
4 * Copyright (C) 2004 Broadcom Corporation
5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#ifndef __B53_REGS_H
21#define __B53_REGS_H
22
23/* Management Port (SMP) Page offsets */
24#define B53_CTRL_PAGE 0x00 /* Control */
25#define B53_STAT_PAGE 0x01 /* Status */
26#define B53_MGMT_PAGE 0x02 /* Management Mode */
27#define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */
28#define B53_ARLCTRL_PAGE 0x04 /* ARL Control */
29#define B53_ARLIO_PAGE 0x05 /* ARL Access */
30#define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */
31#define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */
32
33/* PHY Registers */
34#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */
35#define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */
36#define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */
37
38/* MIB registers */
39#define B53_MIB_PAGE(i) (0x20 + (i))
40
41/* Quality of Service (QoS) Registers */
42#define B53_QOS_PAGE 0x30
43
44/* Port VLAN Page */
45#define B53_PVLAN_PAGE 0x31
46
47/* VLAN Registers */
48#define B53_VLAN_PAGE 0x34
49
50/* Jumbo Frame Registers */
51#define B53_JUMBO_PAGE 0x40
52
53/* CFP Configuration Registers Page */
54#define B53_CFP_PAGE 0xa1
55
56/*************************************************************************
57 * Control Page registers
58 *************************************************************************/
59
60/* Port Control Register (8 bit) */
61#define B53_PORT_CTRL(i) (0x00 + (i))
62#define PORT_CTRL_RX_DISABLE BIT(0)
63#define PORT_CTRL_TX_DISABLE BIT(1)
64#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
65#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
66#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
67#define PORT_CTRL_STP_STATE_S 5
68#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S)
69
70/* SMP Control Register (8 bit) */
71#define B53_SMP_CTRL 0x0a
72
73/* Switch Mode Control Register (8 bit) */
74#define B53_SWITCH_MODE 0x0b
75#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
76#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
77
78/* IMP Port state override register (8 bit) */
79#define B53_PORT_OVERRIDE_CTRL 0x0e
80#define PORT_OVERRIDE_LINK BIT(0)
81#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
82#define PORT_OVERRIDE_SPEED_S 2
83#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
84#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
85#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
86#define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */
87#define PORT_OVERRIDE_RX_FLOW BIT(4)
88#define PORT_OVERRIDE_TX_FLOW BIT(5)
89#define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */
90#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
91
92/* Power-down mode control */
93#define B53_PD_MODE_CTRL_25 0x0f
94
95/* IP Multicast control (8 bit) */
96#define B53_IP_MULTICAST_CTRL 0x21
97#define B53_IPMC_FWD_EN BIT(1)
98#define B53_UC_FWD_EN BIT(6)
99#define B53_MC_FWD_EN BIT(7)
100
101/* (16 bit) */
102#define B53_UC_FLOOD_MASK 0x32
103#define B53_MC_FLOOD_MASK 0x34
104#define B53_IPMC_FLOOD_MASK 0x36
105
106/*
107 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
108 *
109 * For port 8 still use B53_PORT_OVERRIDE_CTRL
110 * Please note that not all ports are available on every hardware, e.g. BCM5301X
111 * don't include overriding port 6, BCM63xx also have some limitations.
112 */
113#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i))
114#define GMII_PO_LINK BIT(0)
115#define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
116#define GMII_PO_SPEED_S 2
117#define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S)
118#define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S)
119#define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S)
120#define GMII_PO_RX_FLOW BIT(4)
121#define GMII_PO_TX_FLOW BIT(5)
122#define GMII_PO_EN BIT(6) /* Use the register contents */
123#define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */
124
125#define B53_RGMII_CTRL_IMP 0x60
126#define RGMII_CTRL_ENABLE_GMII BIT(7)
127#define RGMII_CTRL_TIMING_SEL BIT(2)
128#define RGMII_CTRL_DLL_RXC BIT(1)
129#define RGMII_CTRL_DLL_TXC BIT(0)
130
131#define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i))
132
133/* Software reset register (8 bit) */
134#define B53_SOFTRESET 0x79
135#define SW_RST BIT(7)
136#define EN_SW_RST BIT(4)
137
138/* Fast Aging Control register (8 bit) */
139#define B53_FAST_AGE_CTRL 0x88
140#define FAST_AGE_STATIC BIT(0)
141#define FAST_AGE_DYNAMIC BIT(1)
142#define FAST_AGE_PORT BIT(2)
143#define FAST_AGE_VLAN BIT(3)
144#define FAST_AGE_STP BIT(4)
145#define FAST_AGE_MC BIT(5)
146#define FAST_AGE_DONE BIT(7)
147
148/*************************************************************************
149 * Status Page registers
150 *************************************************************************/
151
152/* Link Status Summary Register (16bit) */
153#define B53_LINK_STAT 0x00
154
155/* Link Status Change Register (16 bit) */
156#define B53_LINK_STAT_CHANGE 0x02
157
158/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
159#define B53_SPEED_STAT 0x04
160#define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1)
161#define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3)
162#define SPEED_STAT_10M 0
163#define SPEED_STAT_100M 1
164#define SPEED_STAT_1000M 2
165
166/* Duplex Status Summary (16 bit) */
167#define B53_DUPLEX_STAT_FE 0x06
168#define B53_DUPLEX_STAT_GE 0x08
169#define B53_DUPLEX_STAT_63XX 0x0c
170
171/* Revision ID register for BCM5325 */
172#define B53_REV_ID_25 0x50
173
174/* Strap Value (48 bit) */
175#define B53_STRAP_VALUE 0x70
176#define SV_GMII_CTRL_115 BIT(27)
177
178/*************************************************************************
179 * Management Mode Page Registers
180 *************************************************************************/
181
182/* Global Management Config Register (8 bit) */
183#define B53_GLOBAL_CONFIG 0x00
184#define GC_RESET_MIB 0x01
185#define GC_RX_BPDU_EN 0x02
186#define GC_MIB_AC_HDR_EN 0x10
187#define GC_MIB_AC_EN 0x20
188#define GC_FRM_MGMT_PORT_M 0xC0
189#define GC_FRM_MGMT_PORT_04 0x00
190#define GC_FRM_MGMT_PORT_MII 0x80
191
192/* Broadcom Header control register (8 bit) */
193#define B53_BRCM_HDR 0x03
194#define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */
195#define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */
196
197/* Device ID register (8 or 32 bit) */
198#define B53_DEVICE_ID 0x30
199
200/* Revision ID register (8 bit) */
201#define B53_REV_ID 0x40
202
203/*************************************************************************
204 * ARL Access Page Registers
205 *************************************************************************/
206
207/* VLAN Table Access Register (8 bit) */
208#define B53_VT_ACCESS 0x80
209#define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */
210#define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */
211#define VTA_CMD_WRITE 0
212#define VTA_CMD_READ 1
213#define VTA_CMD_CLEAR 2
214#define VTA_START_CMD BIT(7)
215
216/* VLAN Table Index Register (16 bit) */
217#define B53_VT_INDEX 0x81
218#define B53_VT_INDEX_9798 0x61
219#define B53_VT_INDEX_63XX 0x62
220
221/* VLAN Table Entry Register (32 bit) */
222#define B53_VT_ENTRY 0x83
223#define B53_VT_ENTRY_9798 0x63
224#define B53_VT_ENTRY_63XX 0x64
225#define VTE_MEMBERS 0x1ff
226#define VTE_UNTAG_S 9
227#define VTE_UNTAG (0x1ff << 9)
228
229/*************************************************************************
230 * Port VLAN Registers
231 *************************************************************************/
232
233/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
234#define B53_PVLAN_PORT_MASK(i) ((i) * 2)
235
236/*************************************************************************
237 * 802.1Q Page Registers
238 *************************************************************************/
239
240/* Global QoS Control (8 bit) */
241#define B53_QOS_GLOBAL_CTL 0x00
242
243/* Enable 802.1Q for individual Ports (16 bit) */
244#define B53_802_1P_EN 0x04
245
246/*************************************************************************
247 * VLAN Page Registers
248 *************************************************************************/
249
250/* VLAN Control 0 (8 bit) */
251#define B53_VLAN_CTRL0 0x00
252#define VC0_8021PF_CTRL_MASK 0x3
253#define VC0_8021PF_CTRL_NONE 0x0
254#define VC0_8021PF_CTRL_CHANGE_PRI 0x1
255#define VC0_8021PF_CTRL_CHANGE_VID 0x2
256#define VC0_8021PF_CTRL_CHANGE_BOTH 0x3
257#define VC0_8021QF_CTRL_MASK 0xc
258#define VC0_8021QF_CTRL_CHANGE_PRI 0x1
259#define VC0_8021QF_CTRL_CHANGE_VID 0x2
260#define VC0_8021QF_CTRL_CHANGE_BOTH 0x3
261#define VC0_RESERVED_1 BIT(1)
262#define VC0_DROP_VID_MISS BIT(4)
263#define VC0_VID_HASH_VID BIT(5)
264#define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */
265#define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */
266
267/* VLAN Control 1 (8 bit) */
268#define B53_VLAN_CTRL1 0x01
269#define VC1_RX_MCST_TAG_EN BIT(1)
270#define VC1_RX_MCST_FWD_EN BIT(2)
271#define VC1_RX_MCST_UNTAG_EN BIT(3)
272
273/* VLAN Control 2 (8 bit) */
274#define B53_VLAN_CTRL2 0x02
275
276/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
277#define B53_VLAN_CTRL3 0x03
278#define B53_VLAN_CTRL3_63XX 0x04
279#define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */
280#define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */
281
282/* VLAN Control 4 (8 bit) */
283#define B53_VLAN_CTRL4 0x05
284#define B53_VLAN_CTRL4_25 0x04
285#define B53_VLAN_CTRL4_63XX 0x06
286#define VC4_ING_VID_CHECK_S 6
287#define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S)
288#define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */
289#define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */
290#define VC4_NO_ING_VID_CHK 2 /* do not check */
291#define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */
292
293/* VLAN Control 5 (8 bit) */
294#define B53_VLAN_CTRL5 0x06
295#define B53_VLAN_CTRL5_25 0x05
296#define B53_VLAN_CTRL5_63XX 0x07
297#define VC5_VID_FFF_EN BIT(2)
298#define VC5_DROP_VTABLE_MISS BIT(3)
299
300/* VLAN Control 6 (8 bit) */
301#define B53_VLAN_CTRL6 0x07
302#define B53_VLAN_CTRL6_63XX 0x08
303
304/* VLAN Table Access Register (16 bit) */
305#define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */
306#define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */
307#define VTA_VID_LOW_MASK_25 0xf
308#define VTA_VID_LOW_MASK_65 0xff
309#define VTA_VID_HIGH_S_25 4
310#define VTA_VID_HIGH_S_65 8
311#define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E)
312#define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65)
313#define VTA_RW_STATE BIT(12)
314#define VTA_RW_STATE_RD 0
315#define VTA_RW_STATE_WR BIT(12)
316#define VTA_RW_OP_EN BIT(13)
317
318/* VLAN Read/Write Registers for (16/32 bit) */
319#define B53_VLAN_WRITE_25 0x08
320#define B53_VLAN_WRITE_65 0x0a
321#define B53_VLAN_READ 0x0c
322#define VA_MEMBER_MASK 0x3f
323#define VA_UNTAG_S_25 6
324#define VA_UNTAG_MASK_25 0x3f
325#define VA_UNTAG_S_65 7
326#define VA_UNTAG_MASK_65 0x1f
327#define VA_VID_HIGH_S 12
328#define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S)
329#define VA_VALID_25 BIT(20)
330#define VA_VALID_25_R4 BIT(24)
331#define VA_VALID_65 BIT(14)
332
333/* VLAN Port Default Tag (16 bit) */
334#define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i))
335
336/*************************************************************************
337 * Jumbo Frame Page Registers
338 *************************************************************************/
339
340/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
341#define B53_JUMBO_PORT_MASK 0x01
342#define B53_JUMBO_PORT_MASK_63XX 0x04
343#define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */
344
345/* Good Frame Max Size without 802.1Q TAG (16 bit) */
346#define B53_JUMBO_MAX_SIZE 0x05
347#define B53_JUMBO_MAX_SIZE_63XX 0x08
348#define JMS_MIN_SIZE 1518
349#define JMS_MAX_SIZE 9724
350
351/*************************************************************************
352 * CFP Configuration Page Registers
353 *************************************************************************/
354
355/* CFP Control Register with ports map (8 bit) */
356#define B53_CFP_CTRL 0x00
357
358#endif /* !__B53_REGS_H */