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Magnus Damm72f4d572010-12-14 16:57:11 +09001/*
2 * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Takashi Yoshii
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/smp.h>
23#include <linux/spinlock.h>
24#include <linux/io.h>
Marc Zyngiera62580e2011-09-08 13:15:22 +010025#include <linux/delay.h>
Magnus Damm72f4d572010-12-14 16:57:11 +090026#include <mach/common.h>
Will Deaconeb504392012-01-20 12:01:12 +010027#include <asm/smp_plat.h>
Marc Zyngiera62580e2011-09-08 13:15:22 +010028#include <mach/sh73a0.h>
Magnus Damm72f4d572010-12-14 16:57:11 +090029#include <asm/smp_scu.h>
30#include <asm/smp_twd.h>
31#include <asm/hardware/gic.h>
32
Rob Herringa2a47ca2012-03-09 17:16:40 -060033#define WUPCR IOMEM(0xe6151010)
34#define SRESCR IOMEM(0xe6151018)
35#define PSTR IOMEM(0xe6151040)
36#define SBAR IOMEM(0xe6180020)
37#define APARMBAREA IOMEM(0xe6f10020)
Magnus Damm72f4d572010-12-14 16:57:11 +090038
39static void __iomem *scu_base_addr(void)
40{
41 return (void __iomem *)0xf0000000;
42}
43
44static DEFINE_SPINLOCK(scu_lock);
45static unsigned long tmp;
46
Kuninori Morimotod6720002012-05-10 00:26:58 -070047#ifdef CONFIG_HAVE_ARM_TWD
Marc Zyngier4200b162012-01-10 19:44:19 +000048static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
Kuninori Morimotod6720002012-05-10 00:26:58 -070049void __init sh73a0_register_twd(void)
50{
51 twd_local_timer_register(&twd_local_timer);
52}
53#endif
Marc Zyngier4200b162012-01-10 19:44:19 +000054
Magnus Damm72f4d572010-12-14 16:57:11 +090055static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
56{
57 void __iomem *scu_base = scu_base_addr();
58
59 spin_lock(&scu_lock);
60 tmp = __raw_readl(scu_base + 8);
61 tmp &= ~clr;
62 tmp |= set;
63 spin_unlock(&scu_lock);
64
65 /* disable cache coherency after releasing the lock */
66 __raw_writel(tmp, scu_base + 8);
67}
68
Marc Zyngiera62580e2011-09-08 13:15:22 +010069static unsigned int __init sh73a0_get_core_count(void)
Magnus Damm72f4d572010-12-14 16:57:11 +090070{
71 void __iomem *scu_base = scu_base_addr();
72
73 return scu_get_core_count(scu_base);
74}
75
Marc Zyngiera62580e2011-09-08 13:15:22 +010076static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
Magnus Damm72f4d572010-12-14 16:57:11 +090077{
Paul Mundtc0312b32011-01-07 12:02:11 +090078 gic_secondary_init(0);
Magnus Damm72f4d572010-12-14 16:57:11 +090079}
80
Marc Zyngiera62580e2011-09-08 13:15:22 +010081static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
Magnus Damm72f4d572010-12-14 16:57:11 +090082{
Will Deaconf80ca522011-08-09 12:13:53 +010083 cpu = cpu_logical_map(cpu);
84
Magnus Damm72f4d572010-12-14 16:57:11 +090085 /* enable cache coherency */
86 modify_scu_cpu_psr(0, 3 << (cpu * 8));
87
Linus Torvalds820d41c2012-03-29 18:02:10 -070088 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
Rob Herringa2a47ca2012-03-09 17:16:40 -060089 __raw_writel(1 << cpu, WUPCR); /* wake up */
Magnus Damm72f4d572010-12-14 16:57:11 +090090 else
Rob Herringa2a47ca2012-03-09 17:16:40 -060091 __raw_writel(1 << cpu, SRESCR); /* reset */
Magnus Damm72f4d572010-12-14 16:57:11 +090092
93 return 0;
94}
95
Marc Zyngiera62580e2011-09-08 13:15:22 +010096static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
Magnus Damm72f4d572010-12-14 16:57:11 +090097{
Will Deaconf80ca522011-08-09 12:13:53 +010098 int cpu = cpu_logical_map(0);
99
Magnus Damm72f4d572010-12-14 16:57:11 +0900100 scu_enable(scu_base_addr());
101
102 /* Map the reset vector (in headsmp.S) */
Rob Herringa2a47ca2012-03-09 17:16:40 -0600103 __raw_writel(0, APARMBAREA); /* 4k */
104 __raw_writel(__pa(shmobile_secondary_vector), SBAR);
Magnus Damm72f4d572010-12-14 16:57:11 +0900105
106 /* enable cache coherency on CPU0 */
Will Deaconf80ca522011-08-09 12:13:53 +0100107 modify_scu_cpu_psr(0, 3 << (cpu * 8));
Magnus Damm72f4d572010-12-14 16:57:11 +0900108}
Marc Zyngiera62580e2011-09-08 13:15:22 +0100109
110static void __init sh73a0_smp_init_cpus(void)
111{
112 unsigned int ncores = sh73a0_get_core_count();
113
114 shmobile_smp_init_cpus(ncores);
115}
116
117static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
118{
119 int k;
120
121 /* this function is running on another CPU than the offline target,
122 * here we need wait for shutdown code in platform_cpu_die() to
123 * finish before asking SoC-specific code to power off the CPU core.
124 */
125 for (k = 0; k < 1000; k++) {
126 if (shmobile_cpu_is_dead(cpu))
127 return 1;
128
129 mdelay(1);
130 }
131
132 return 0;
133}
134
135
136struct smp_operations sh73a0_smp_ops __initdata = {
137 .smp_init_cpus = sh73a0_smp_init_cpus,
138 .smp_prepare_cpus = sh73a0_smp_prepare_cpus,
139 .smp_secondary_init = sh73a0_secondary_init,
140 .smp_boot_secondary = sh73a0_boot_secondary,
141#ifdef CONFIG_HOTPLUG_CPU
142 .cpu_kill = sh73a0_cpu_kill,
143 .cpu_die = shmobile_cpu_die,
144 .cpu_disable = shmobile_cpu_disable,
145#endif
146};