blob: a6e3c98b95ed436c7470f1ae58d17ba9bec446f5 [file] [log] [blame]
Matthias Bruggerf682a212014-05-13 01:06:13 +02001/*
2 * Device Tree support for Mediatek SoCs
3 *
4 * Copyright (c) 2014 MundoReader S.L.
5 * Author: Matthias Brugger <matthias.bgg@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <linux/init.h>
18#include <asm/mach/arch.h>
Matthias Brugger9821e542015-10-02 23:19:37 +080019#include <linux/of.h>
20#include <linux/clk-provider.h>
21#include <linux/clocksource.h>
22
23
24#define GPT6_CON_MT65xx 0x10008060
25#define GPT_ENABLE 0x31
26
27static void __init mediatek_timer_init(void)
28{
29 void __iomem *gpt_base;
30
31 if (of_machine_is_compatible("mediatek,mt6589") ||
John Crispin601bac72016-04-07 20:18:35 +020032 of_machine_is_compatible("mediatek,mt7623") ||
Matthias Brugger9821e542015-10-02 23:19:37 +080033 of_machine_is_compatible("mediatek,mt8135") ||
34 of_machine_is_compatible("mediatek,mt8127")) {
35 /* turn on GPT6 which ungates arch timer clocks */
36 gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
37
38 /* enable clock and set to free-run */
39 writel(GPT_ENABLE, gpt_base);
40 iounmap(gpt_base);
41 }
42
43 of_clk_init(NULL);
Linus Torvalds56e04642015-11-10 14:56:23 -080044 clocksource_probe();
Matthias Brugger9821e542015-10-02 23:19:37 +080045};
Matthias Bruggerf682a212014-05-13 01:06:13 +020046
47static const char * const mediatek_board_dt_compat[] = {
Erin Lo74d25722015-10-20 14:34:31 +080048 "mediatek,mt2701",
Matthias Bruggerf682a212014-05-13 01:06:13 +020049 "mediatek,mt6589",
Howard Chen45421722014-11-14 13:14:52 +080050 "mediatek,mt6592",
John Crispin31ac0d62016-01-05 17:24:27 +010051 "mediatek,mt7623",
Joe.C1ccd6532014-11-11 15:53:41 +080052 "mediatek,mt8127",
Joe.C0c3fb202014-11-11 15:53:43 +080053 "mediatek,mt8135",
Matthias Bruggerf682a212014-05-13 01:06:13 +020054 NULL,
55};
56
57DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
58 .dt_compat = mediatek_board_dt_compat,
Matthias Brugger9821e542015-10-02 23:19:37 +080059 .init_time = mediatek_timer_init,
Matthias Bruggerf682a212014-05-13 01:06:13 +020060MACHINE_END