Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 ARM Limited |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 9 | #include <linux/cpu.h> |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 10 | #include <linux/init.h> |
| 11 | #include <linux/list.h> |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 12 | #include <linux/perf_event.h> |
| 13 | #include <linux/sched.h> |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 14 | #include <linux/slab.h> |
| 15 | #include <linux/sysctl.h> |
| 16 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 17 | #include <asm/alternative.h> |
| 18 | #include <asm/cpufeature.h> |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 19 | #include <asm/insn.h> |
| 20 | #include <asm/opcodes.h> |
James Morse | 870828e | 2015-07-21 13:23:27 +0100 | [diff] [blame] | 21 | #include <asm/sysreg.h> |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 22 | #include <asm/system_misc.h> |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 23 | #include <asm/traps.h> |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 24 | #include <asm/uaccess.h> |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 25 | #include <asm/cpufeature.h> |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 26 | |
Punit Agrawal | d784e29 | 2014-11-18 11:41:27 +0000 | [diff] [blame] | 27 | #define CREATE_TRACE_POINTS |
| 28 | #include "trace-events-emulation.h" |
| 29 | |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 30 | /* |
| 31 | * The runtime support for deprecated instruction support can be in one of |
| 32 | * following three states - |
| 33 | * |
| 34 | * 0 = undef |
| 35 | * 1 = emulate (software emulation) |
| 36 | * 2 = hw (supported in hardware) |
| 37 | */ |
| 38 | enum insn_emulation_mode { |
| 39 | INSN_UNDEF, |
| 40 | INSN_EMULATE, |
| 41 | INSN_HW, |
| 42 | }; |
| 43 | |
| 44 | enum legacy_insn_status { |
| 45 | INSN_DEPRECATED, |
| 46 | INSN_OBSOLETE, |
| 47 | }; |
| 48 | |
| 49 | struct insn_emulation_ops { |
| 50 | const char *name; |
| 51 | enum legacy_insn_status status; |
| 52 | struct undef_hook *hooks; |
| 53 | int (*set_hw_mode)(bool enable); |
| 54 | }; |
| 55 | |
| 56 | struct insn_emulation { |
| 57 | struct list_head node; |
| 58 | struct insn_emulation_ops *ops; |
| 59 | int current_mode; |
| 60 | int min; |
| 61 | int max; |
| 62 | }; |
| 63 | |
| 64 | static LIST_HEAD(insn_emulation); |
Jisheng Zhang | a7c61a3 | 2015-11-20 17:59:10 +0800 | [diff] [blame] | 65 | static int nr_insn_emulated __initdata; |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 66 | static DEFINE_RAW_SPINLOCK(insn_emulation_lock); |
| 67 | |
| 68 | static void register_emulation_hooks(struct insn_emulation_ops *ops) |
| 69 | { |
| 70 | struct undef_hook *hook; |
| 71 | |
| 72 | BUG_ON(!ops->hooks); |
| 73 | |
| 74 | for (hook = ops->hooks; hook->instr_mask; hook++) |
| 75 | register_undef_hook(hook); |
| 76 | |
| 77 | pr_notice("Registered %s emulation handler\n", ops->name); |
| 78 | } |
| 79 | |
| 80 | static void remove_emulation_hooks(struct insn_emulation_ops *ops) |
| 81 | { |
| 82 | struct undef_hook *hook; |
| 83 | |
| 84 | BUG_ON(!ops->hooks); |
| 85 | |
| 86 | for (hook = ops->hooks; hook->instr_mask; hook++) |
| 87 | unregister_undef_hook(hook); |
| 88 | |
| 89 | pr_notice("Removed %s emulation handler\n", ops->name); |
| 90 | } |
| 91 | |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 92 | static void enable_insn_hw_mode(void *data) |
| 93 | { |
| 94 | struct insn_emulation *insn = (struct insn_emulation *)data; |
| 95 | if (insn->ops->set_hw_mode) |
| 96 | insn->ops->set_hw_mode(true); |
| 97 | } |
| 98 | |
| 99 | static void disable_insn_hw_mode(void *data) |
| 100 | { |
| 101 | struct insn_emulation *insn = (struct insn_emulation *)data; |
| 102 | if (insn->ops->set_hw_mode) |
| 103 | insn->ops->set_hw_mode(false); |
| 104 | } |
| 105 | |
| 106 | /* Run set_hw_mode(mode) on all active CPUs */ |
| 107 | static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable) |
| 108 | { |
| 109 | if (!insn->ops->set_hw_mode) |
| 110 | return -EINVAL; |
| 111 | if (enable) |
| 112 | on_each_cpu(enable_insn_hw_mode, (void *)insn, true); |
| 113 | else |
| 114 | on_each_cpu(disable_insn_hw_mode, (void *)insn, true); |
| 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | /* |
| 119 | * Run set_hw_mode for all insns on a starting CPU. |
| 120 | * Returns: |
| 121 | * 0 - If all the hooks ran successfully. |
| 122 | * -EINVAL - At least one hook is not supported by the CPU. |
| 123 | */ |
Sebastian Andrzej Siewior | 27c01a8 | 2016-07-13 17:16:56 +0000 | [diff] [blame] | 124 | static int run_all_insn_set_hw_mode(unsigned int cpu) |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 125 | { |
| 126 | int rc = 0; |
| 127 | unsigned long flags; |
| 128 | struct insn_emulation *insn; |
| 129 | |
| 130 | raw_spin_lock_irqsave(&insn_emulation_lock, flags); |
| 131 | list_for_each_entry(insn, &insn_emulation, node) { |
| 132 | bool enable = (insn->current_mode == INSN_HW); |
| 133 | if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) { |
Sebastian Andrzej Siewior | 27c01a8 | 2016-07-13 17:16:56 +0000 | [diff] [blame] | 134 | pr_warn("CPU[%u] cannot support the emulation of %s", |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 135 | cpu, insn->ops->name); |
| 136 | rc = -EINVAL; |
| 137 | } |
| 138 | } |
| 139 | raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); |
| 140 | return rc; |
| 141 | } |
| 142 | |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 143 | static int update_insn_emulation_mode(struct insn_emulation *insn, |
| 144 | enum insn_emulation_mode prev) |
| 145 | { |
| 146 | int ret = 0; |
| 147 | |
| 148 | switch (prev) { |
| 149 | case INSN_UNDEF: /* Nothing to be done */ |
| 150 | break; |
| 151 | case INSN_EMULATE: |
| 152 | remove_emulation_hooks(insn->ops); |
| 153 | break; |
| 154 | case INSN_HW: |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 155 | if (!run_all_cpu_set_hw_mode(insn, false)) |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 156 | pr_notice("Disabled %s support\n", insn->ops->name); |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 157 | break; |
| 158 | } |
| 159 | |
| 160 | switch (insn->current_mode) { |
| 161 | case INSN_UNDEF: |
| 162 | break; |
| 163 | case INSN_EMULATE: |
| 164 | register_emulation_hooks(insn->ops); |
| 165 | break; |
| 166 | case INSN_HW: |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 167 | ret = run_all_cpu_set_hw_mode(insn, true); |
| 168 | if (!ret) |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 169 | pr_notice("Enabled %s support\n", insn->ops->name); |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 170 | break; |
| 171 | } |
| 172 | |
| 173 | return ret; |
| 174 | } |
| 175 | |
Jisheng Zhang | a7c61a3 | 2015-11-20 17:59:10 +0800 | [diff] [blame] | 176 | static void __init register_insn_emulation(struct insn_emulation_ops *ops) |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 177 | { |
| 178 | unsigned long flags; |
| 179 | struct insn_emulation *insn; |
| 180 | |
| 181 | insn = kzalloc(sizeof(*insn), GFP_KERNEL); |
| 182 | insn->ops = ops; |
| 183 | insn->min = INSN_UNDEF; |
| 184 | |
| 185 | switch (ops->status) { |
| 186 | case INSN_DEPRECATED: |
| 187 | insn->current_mode = INSN_EMULATE; |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 188 | /* Disable the HW mode if it was turned on at early boot time */ |
| 189 | run_all_cpu_set_hw_mode(insn, false); |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 190 | insn->max = INSN_HW; |
| 191 | break; |
| 192 | case INSN_OBSOLETE: |
| 193 | insn->current_mode = INSN_UNDEF; |
| 194 | insn->max = INSN_EMULATE; |
| 195 | break; |
| 196 | } |
| 197 | |
| 198 | raw_spin_lock_irqsave(&insn_emulation_lock, flags); |
| 199 | list_add(&insn->node, &insn_emulation); |
| 200 | nr_insn_emulated++; |
| 201 | raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); |
| 202 | |
| 203 | /* Register any handlers if required */ |
| 204 | update_insn_emulation_mode(insn, INSN_UNDEF); |
| 205 | } |
| 206 | |
| 207 | static int emulation_proc_handler(struct ctl_table *table, int write, |
| 208 | void __user *buffer, size_t *lenp, |
| 209 | loff_t *ppos) |
| 210 | { |
| 211 | int ret = 0; |
| 212 | struct insn_emulation *insn = (struct insn_emulation *) table->data; |
| 213 | enum insn_emulation_mode prev_mode = insn->current_mode; |
| 214 | |
| 215 | table->data = &insn->current_mode; |
| 216 | ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); |
| 217 | |
| 218 | if (ret || !write || prev_mode == insn->current_mode) |
| 219 | goto ret; |
| 220 | |
| 221 | ret = update_insn_emulation_mode(insn, prev_mode); |
Will Deacon | 9096339 | 2014-11-25 10:05:35 +0000 | [diff] [blame] | 222 | if (ret) { |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 223 | /* Mode change failed, revert to previous mode. */ |
| 224 | insn->current_mode = prev_mode; |
| 225 | update_insn_emulation_mode(insn, INSN_UNDEF); |
| 226 | } |
| 227 | ret: |
| 228 | table->data = insn; |
| 229 | return ret; |
| 230 | } |
| 231 | |
| 232 | static struct ctl_table ctl_abi[] = { |
| 233 | { |
| 234 | .procname = "abi", |
| 235 | .mode = 0555, |
| 236 | }, |
| 237 | { } |
| 238 | }; |
| 239 | |
Jisheng Zhang | a7c61a3 | 2015-11-20 17:59:10 +0800 | [diff] [blame] | 240 | static void __init register_insn_emulation_sysctl(struct ctl_table *table) |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 241 | { |
| 242 | unsigned long flags; |
| 243 | int i = 0; |
| 244 | struct insn_emulation *insn; |
| 245 | struct ctl_table *insns_sysctl, *sysctl; |
| 246 | |
| 247 | insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1), |
| 248 | GFP_KERNEL); |
| 249 | |
| 250 | raw_spin_lock_irqsave(&insn_emulation_lock, flags); |
| 251 | list_for_each_entry(insn, &insn_emulation, node) { |
| 252 | sysctl = &insns_sysctl[i]; |
| 253 | |
| 254 | sysctl->mode = 0644; |
| 255 | sysctl->maxlen = sizeof(int); |
| 256 | |
| 257 | sysctl->procname = insn->ops->name; |
| 258 | sysctl->data = insn; |
| 259 | sysctl->extra1 = &insn->min; |
| 260 | sysctl->extra2 = &insn->max; |
| 261 | sysctl->proc_handler = emulation_proc_handler; |
| 262 | i++; |
| 263 | } |
| 264 | raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); |
| 265 | |
| 266 | table->child = insns_sysctl; |
| 267 | register_sysctl_table(table); |
| 268 | } |
| 269 | |
| 270 | /* |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 271 | * Implement emulation of the SWP/SWPB instructions using load-exclusive and |
| 272 | * store-exclusive. |
| 273 | * |
| 274 | * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>] |
| 275 | * Where: Rt = destination |
| 276 | * Rt2 = source |
| 277 | * Rn = address |
| 278 | */ |
| 279 | |
| 280 | /* |
| 281 | * Error-checking SWP macros implemented using ldxr{b}/stxr{b} |
| 282 | */ |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 283 | |
| 284 | /* Arbitrary constant to ensure forward-progress of the LL/SC loop */ |
| 285 | #define __SWP_LL_SC_LOOPS 4 |
| 286 | |
| 287 | #define __user_swpX_asm(data, addr, res, temp, temp2, B) \ |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 288 | __asm__ __volatile__( \ |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 289 | " mov %w3, %w7\n" \ |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 290 | ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ |
| 291 | CONFIG_ARM64_PAN) \ |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 292 | "0: ldxr"B" %w2, [%4]\n" \ |
| 293 | "1: stxr"B" %w0, %w1, [%4]\n" \ |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 294 | " cbz %w0, 2f\n" \ |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 295 | " sub %w3, %w3, #1\n" \ |
| 296 | " cbnz %w3, 0b\n" \ |
| 297 | " mov %w0, %w5\n" \ |
Will Deacon | 589cb22 | 2015-10-15 13:55:53 +0100 | [diff] [blame] | 298 | " b 3f\n" \ |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 299 | "2:\n" \ |
Will Deacon | 589cb22 | 2015-10-15 13:55:53 +0100 | [diff] [blame] | 300 | " mov %w1, %w2\n" \ |
| 301 | "3:\n" \ |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 302 | " .pushsection .fixup,\"ax\"\n" \ |
| 303 | " .align 2\n" \ |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 304 | "4: mov %w0, %w6\n" \ |
Will Deacon | 589cb22 | 2015-10-15 13:55:53 +0100 | [diff] [blame] | 305 | " b 3b\n" \ |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 306 | " .popsection" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 307 | _ASM_EXTABLE(0b, 4b) \ |
| 308 | _ASM_EXTABLE(1b, 4b) \ |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 309 | ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ |
| 310 | CONFIG_ARM64_PAN) \ |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 311 | : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \ |
Mark Rutland | 4775fbc | 2017-05-03 16:09:36 +0100 | [diff] [blame] | 312 | : "r" ((unsigned long)addr), "i" (-EAGAIN), \ |
| 313 | "i" (-EFAULT), \ |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 314 | "i" (__SWP_LL_SC_LOOPS) \ |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 315 | : "memory") |
| 316 | |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 317 | #define __user_swp_asm(data, addr, res, temp, temp2) \ |
| 318 | __user_swpX_asm(data, addr, res, temp, temp2, "") |
| 319 | #define __user_swpb_asm(data, addr, res, temp, temp2) \ |
| 320 | __user_swpX_asm(data, addr, res, temp, temp2, "b") |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 321 | |
| 322 | /* |
| 323 | * Bit 22 of the instruction encoding distinguishes between |
| 324 | * the SWP and SWPB variants (bit set means SWPB). |
| 325 | */ |
| 326 | #define TYPE_SWPB (1 << 22) |
| 327 | |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 328 | static int emulate_swpX(unsigned int address, unsigned int *data, |
| 329 | unsigned int type) |
| 330 | { |
| 331 | unsigned int res = 0; |
| 332 | |
| 333 | if ((type != TYPE_SWPB) && (address & 0x3)) { |
| 334 | /* SWP to unaligned address not permitted */ |
| 335 | pr_debug("SWP instruction on unaligned pointer!\n"); |
| 336 | return -EFAULT; |
| 337 | } |
| 338 | |
| 339 | while (1) { |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 340 | unsigned long temp, temp2; |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 341 | |
| 342 | if (type == TYPE_SWPB) |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 343 | __user_swpb_asm(*data, address, res, temp, temp2); |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 344 | else |
Will Deacon | 1c5b51d | 2016-07-04 16:59:43 +0100 | [diff] [blame] | 345 | __user_swp_asm(*data, address, res, temp, temp2); |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 346 | |
| 347 | if (likely(res != -EAGAIN) || signal_pending(current)) |
| 348 | break; |
| 349 | |
| 350 | cond_resched(); |
| 351 | } |
| 352 | |
| 353 | return res; |
| 354 | } |
| 355 | |
David A. Long | 2af3ec0 | 2016-07-08 12:35:47 -0400 | [diff] [blame] | 356 | #define ARM_OPCODE_CONDITION_UNCOND 0xf |
| 357 | |
| 358 | static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr) |
| 359 | { |
| 360 | u32 cc_bits = opcode >> 28; |
| 361 | |
| 362 | if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) { |
| 363 | if ((*aarch32_opcode_cond_checks[cc_bits])(psr)) |
| 364 | return ARM_OPCODE_CONDTEST_PASS; |
| 365 | else |
| 366 | return ARM_OPCODE_CONDTEST_FAIL; |
| 367 | } |
| 368 | return ARM_OPCODE_CONDTEST_UNCOND; |
| 369 | } |
| 370 | |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 371 | /* |
| 372 | * swp_handler logs the id of calling process, dissects the instruction, sanity |
| 373 | * checks the memory location, calls emulate_swpX for the actual operation and |
| 374 | * deals with fixup/error handling before returning |
| 375 | */ |
| 376 | static int swp_handler(struct pt_regs *regs, u32 instr) |
| 377 | { |
| 378 | u32 destreg, data, type, address = 0; |
| 379 | int rn, rt2, res = 0; |
| 380 | |
| 381 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); |
| 382 | |
| 383 | type = instr & TYPE_SWPB; |
| 384 | |
David A. Long | 2af3ec0 | 2016-07-08 12:35:47 -0400 | [diff] [blame] | 385 | switch (aarch32_check_condition(instr, regs->pstate)) { |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 386 | case ARM_OPCODE_CONDTEST_PASS: |
| 387 | break; |
| 388 | case ARM_OPCODE_CONDTEST_FAIL: |
| 389 | /* Condition failed - return to next instruction */ |
| 390 | goto ret; |
| 391 | case ARM_OPCODE_CONDTEST_UNCOND: |
| 392 | /* If unconditional encoding - not a SWP, undef */ |
| 393 | return -EFAULT; |
| 394 | default: |
| 395 | return -EINVAL; |
| 396 | } |
| 397 | |
| 398 | rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET); |
| 399 | rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET); |
| 400 | |
| 401 | address = (u32)regs->user_regs.regs[rn]; |
| 402 | data = (u32)regs->user_regs.regs[rt2]; |
| 403 | destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET); |
| 404 | |
| 405 | pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n", |
| 406 | rn, address, destreg, |
| 407 | aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data); |
| 408 | |
| 409 | /* Check access in reasonable access range for both SWP and SWPB */ |
| 410 | if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) { |
| 411 | pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n", |
| 412 | address); |
| 413 | goto fault; |
| 414 | } |
| 415 | |
| 416 | res = emulate_swpX(address, &data, type); |
| 417 | if (res == -EFAULT) |
| 418 | goto fault; |
| 419 | else if (res == 0) |
| 420 | regs->user_regs.regs[destreg] = data; |
| 421 | |
| 422 | ret: |
Punit Agrawal | d784e29 | 2014-11-18 11:41:27 +0000 | [diff] [blame] | 423 | if (type == TYPE_SWPB) |
| 424 | trace_instruction_emulation("swpb", regs->pc); |
| 425 | else |
| 426 | trace_instruction_emulation("swp", regs->pc); |
| 427 | |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 428 | pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n", |
| 429 | current->comm, (unsigned long)current->pid, regs->pc); |
| 430 | |
| 431 | regs->pc += 4; |
| 432 | return 0; |
| 433 | |
| 434 | fault: |
Andre Przywara | 390bf17 | 2016-06-28 18:07:31 +0100 | [diff] [blame] | 435 | pr_debug("SWP{B} emulation: access caused memory abort!\n"); |
| 436 | arm64_notify_segfault(regs, address); |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | /* |
| 442 | * Only emulate SWP/SWPB executed in ARM state/User mode. |
| 443 | * The kernel must be SWP free and SWP{B} does not exist in Thumb. |
| 444 | */ |
| 445 | static struct undef_hook swp_hooks[] = { |
| 446 | { |
| 447 | .instr_mask = 0x0fb00ff0, |
| 448 | .instr_val = 0x01000090, |
| 449 | .pstate_mask = COMPAT_PSR_MODE_MASK, |
| 450 | .pstate_val = COMPAT_PSR_MODE_USR, |
| 451 | .fn = swp_handler |
| 452 | }, |
| 453 | { } |
| 454 | }; |
| 455 | |
| 456 | static struct insn_emulation_ops swp_ops = { |
| 457 | .name = "swp", |
| 458 | .status = INSN_OBSOLETE, |
| 459 | .hooks = swp_hooks, |
| 460 | .set_hw_mode = NULL, |
| 461 | }; |
| 462 | |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 463 | static int cp15barrier_handler(struct pt_regs *regs, u32 instr) |
| 464 | { |
| 465 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); |
| 466 | |
David A. Long | 2af3ec0 | 2016-07-08 12:35:47 -0400 | [diff] [blame] | 467 | switch (aarch32_check_condition(instr, regs->pstate)) { |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 468 | case ARM_OPCODE_CONDTEST_PASS: |
| 469 | break; |
| 470 | case ARM_OPCODE_CONDTEST_FAIL: |
| 471 | /* Condition failed - return to next instruction */ |
| 472 | goto ret; |
| 473 | case ARM_OPCODE_CONDTEST_UNCOND: |
| 474 | /* If unconditional encoding - not a barrier instruction */ |
| 475 | return -EFAULT; |
| 476 | default: |
| 477 | return -EINVAL; |
| 478 | } |
| 479 | |
| 480 | switch (aarch32_insn_mcr_extract_crm(instr)) { |
| 481 | case 10: |
| 482 | /* |
| 483 | * dmb - mcr p15, 0, Rt, c7, c10, 5 |
| 484 | * dsb - mcr p15, 0, Rt, c7, c10, 4 |
| 485 | */ |
Punit Agrawal | d784e29 | 2014-11-18 11:41:27 +0000 | [diff] [blame] | 486 | if (aarch32_insn_mcr_extract_opc2(instr) == 5) { |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 487 | dmb(sy); |
Punit Agrawal | d784e29 | 2014-11-18 11:41:27 +0000 | [diff] [blame] | 488 | trace_instruction_emulation( |
| 489 | "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc); |
| 490 | } else { |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 491 | dsb(sy); |
Punit Agrawal | d784e29 | 2014-11-18 11:41:27 +0000 | [diff] [blame] | 492 | trace_instruction_emulation( |
| 493 | "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc); |
| 494 | } |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 495 | break; |
| 496 | case 5: |
| 497 | /* |
| 498 | * isb - mcr p15, 0, Rt, c7, c5, 4 |
| 499 | * |
| 500 | * Taking an exception or returning from one acts as an |
| 501 | * instruction barrier. So no explicit barrier needed here. |
| 502 | */ |
Punit Agrawal | d784e29 | 2014-11-18 11:41:27 +0000 | [diff] [blame] | 503 | trace_instruction_emulation( |
| 504 | "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc); |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 505 | break; |
| 506 | } |
| 507 | |
| 508 | ret: |
| 509 | pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n", |
| 510 | current->comm, (unsigned long)current->pid, regs->pc); |
| 511 | |
| 512 | regs->pc += 4; |
| 513 | return 0; |
| 514 | } |
| 515 | |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 516 | static int cp15_barrier_set_hw_mode(bool enable) |
| 517 | { |
Suzuki K. Poulose | 736d474 | 2015-01-21 12:43:10 +0000 | [diff] [blame] | 518 | if (enable) |
| 519 | config_sctlr_el1(0, SCTLR_EL1_CP15BEN); |
| 520 | else |
| 521 | config_sctlr_el1(SCTLR_EL1_CP15BEN, 0); |
| 522 | return 0; |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 523 | } |
| 524 | |
| 525 | static struct undef_hook cp15_barrier_hooks[] = { |
| 526 | { |
| 527 | .instr_mask = 0x0fff0fdf, |
| 528 | .instr_val = 0x0e070f9a, |
| 529 | .pstate_mask = COMPAT_PSR_MODE_MASK, |
| 530 | .pstate_val = COMPAT_PSR_MODE_USR, |
| 531 | .fn = cp15barrier_handler, |
| 532 | }, |
| 533 | { |
| 534 | .instr_mask = 0x0fff0fff, |
| 535 | .instr_val = 0x0e070f95, |
| 536 | .pstate_mask = COMPAT_PSR_MODE_MASK, |
| 537 | .pstate_val = COMPAT_PSR_MODE_USR, |
| 538 | .fn = cp15barrier_handler, |
| 539 | }, |
| 540 | { } |
| 541 | }; |
| 542 | |
| 543 | static struct insn_emulation_ops cp15_barrier_ops = { |
| 544 | .name = "cp15_barrier", |
| 545 | .status = INSN_DEPRECATED, |
| 546 | .hooks = cp15_barrier_hooks, |
| 547 | .set_hw_mode = cp15_barrier_set_hw_mode, |
| 548 | }; |
| 549 | |
Suzuki K. Poulose | 2d888f4 | 2015-01-21 12:43:11 +0000 | [diff] [blame] | 550 | static int setend_set_hw_mode(bool enable) |
| 551 | { |
| 552 | if (!cpu_supports_mixed_endian_el0()) |
| 553 | return -EINVAL; |
| 554 | |
| 555 | if (enable) |
| 556 | config_sctlr_el1(SCTLR_EL1_SED, 0); |
| 557 | else |
| 558 | config_sctlr_el1(0, SCTLR_EL1_SED); |
| 559 | return 0; |
| 560 | } |
| 561 | |
| 562 | static int compat_setend_handler(struct pt_regs *regs, u32 big_endian) |
| 563 | { |
| 564 | char *insn; |
| 565 | |
| 566 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); |
| 567 | |
| 568 | if (big_endian) { |
| 569 | insn = "setend be"; |
| 570 | regs->pstate |= COMPAT_PSR_E_BIT; |
| 571 | } else { |
| 572 | insn = "setend le"; |
| 573 | regs->pstate &= ~COMPAT_PSR_E_BIT; |
| 574 | } |
| 575 | |
| 576 | trace_instruction_emulation(insn, regs->pc); |
| 577 | pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n", |
| 578 | current->comm, (unsigned long)current->pid, regs->pc); |
| 579 | |
| 580 | return 0; |
| 581 | } |
| 582 | |
| 583 | static int a32_setend_handler(struct pt_regs *regs, u32 instr) |
| 584 | { |
| 585 | int rc = compat_setend_handler(regs, (instr >> 9) & 1); |
| 586 | regs->pc += 4; |
| 587 | return rc; |
| 588 | } |
| 589 | |
| 590 | static int t16_setend_handler(struct pt_regs *regs, u32 instr) |
| 591 | { |
| 592 | int rc = compat_setend_handler(regs, (instr >> 3) & 1); |
| 593 | regs->pc += 2; |
| 594 | return rc; |
| 595 | } |
| 596 | |
| 597 | static struct undef_hook setend_hooks[] = { |
| 598 | { |
| 599 | .instr_mask = 0xfffffdff, |
| 600 | .instr_val = 0xf1010000, |
| 601 | .pstate_mask = COMPAT_PSR_MODE_MASK, |
| 602 | .pstate_val = COMPAT_PSR_MODE_USR, |
| 603 | .fn = a32_setend_handler, |
| 604 | }, |
| 605 | { |
| 606 | /* Thumb mode */ |
| 607 | .instr_mask = 0x0000fff7, |
| 608 | .instr_val = 0x0000b650, |
| 609 | .pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK), |
| 610 | .pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR), |
| 611 | .fn = t16_setend_handler, |
| 612 | }, |
| 613 | {} |
| 614 | }; |
| 615 | |
| 616 | static struct insn_emulation_ops setend_ops = { |
| 617 | .name = "setend", |
| 618 | .status = INSN_DEPRECATED, |
| 619 | .hooks = setend_hooks, |
| 620 | .set_hw_mode = setend_set_hw_mode, |
| 621 | }; |
| 622 | |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 623 | /* |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 624 | * Invoked as late_initcall, since not needed before init spawned. |
| 625 | */ |
| 626 | static int __init armv8_deprecated_init(void) |
| 627 | { |
Punit Agrawal | bd35a4a | 2014-11-18 11:41:25 +0000 | [diff] [blame] | 628 | if (IS_ENABLED(CONFIG_SWP_EMULATION)) |
| 629 | register_insn_emulation(&swp_ops); |
| 630 | |
Punit Agrawal | c852f32 | 2014-11-18 11:41:26 +0000 | [diff] [blame] | 631 | if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION)) |
| 632 | register_insn_emulation(&cp15_barrier_ops); |
| 633 | |
Suzuki K. Poulose | 2d888f4 | 2015-01-21 12:43:11 +0000 | [diff] [blame] | 634 | if (IS_ENABLED(CONFIG_SETEND_EMULATION)) { |
| 635 | if(system_supports_mixed_endian_el0()) |
| 636 | register_insn_emulation(&setend_ops); |
| 637 | else |
| 638 | pr_info("setend instruction emulation is not supported on the system"); |
| 639 | } |
| 640 | |
Sebastian Andrzej Siewior | 27c01a8 | 2016-07-13 17:16:56 +0000 | [diff] [blame] | 641 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING, |
| 642 | "AP_ARM64_ISNDEP_STARTING", |
| 643 | run_all_insn_set_hw_mode, NULL); |
Punit Agrawal | 587064b | 2014-11-18 11:41:24 +0000 | [diff] [blame] | 644 | register_insn_emulation_sysctl(ctl_abi); |
| 645 | |
| 646 | return 0; |
| 647 | } |
| 648 | |
| 649 | late_initcall(armv8_deprecated_init); |