Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include "drmP.h" |
| 26 | |
| 27 | #include "nouveau_drv.h" |
| 28 | #include "nouveau_dma.h" |
| 29 | #include "nouveau_ramht.h" |
Ben Skeggs | ef8389a | 2011-02-01 10:07:32 +1000 | [diff] [blame] | 30 | #include "nv50_display.h" |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 31 | |
| 32 | static void |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 33 | nv50_evo_channel_del(struct nouveau_channel **pevo) |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 34 | { |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 35 | struct nouveau_channel *evo = *pevo; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 36 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 37 | if (!evo) |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 38 | return; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 39 | *pevo = NULL; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 40 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 41 | nouveau_gpuobj_channel_takedown(evo); |
| 42 | nouveau_bo_unmap(evo->pushbuf_bo); |
| 43 | nouveau_bo_ref(NULL, &evo->pushbuf_bo); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 44 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 45 | if (evo->user) |
| 46 | iounmap(evo->user); |
| 47 | |
| 48 | kfree(evo); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 49 | } |
| 50 | |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 51 | void |
| 52 | nv50_evo_dmaobj_init(struct nouveau_gpuobj *obj, u32 memtype, u64 base, u64 size) |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 53 | { |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 54 | struct drm_nouveau_private *dev_priv = obj->dev->dev_private; |
| 55 | u32 flags5; |
| 56 | |
| 57 | if (dev_priv->chipset < 0xc0) { |
| 58 | /* not supported on 0x50, specified in format mthd */ |
| 59 | if (dev_priv->chipset == 0x50) |
| 60 | memtype = 0; |
| 61 | flags5 = 0x00010000; |
| 62 | } else { |
| 63 | if (memtype & 0x80000000) |
| 64 | flags5 = 0x00000000; /* large pages */ |
| 65 | else |
| 66 | flags5 = 0x00020000; |
| 67 | } |
| 68 | |
| 69 | nv50_gpuobj_dma_init(obj, 0, 0x3d, base, size, NV_MEM_TARGET_VRAM, |
| 70 | NV_MEM_ACCESS_RW, (memtype >> 8) & 0xff, 0); |
| 71 | nv_wo32(obj, 0x14, flags5); |
| 72 | dev_priv->engine.instmem.flush(obj->dev); |
| 73 | } |
| 74 | |
| 75 | int |
| 76 | nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype, |
| 77 | u64 base, u64 size, struct nouveau_gpuobj **pobj) |
| 78 | { |
Ben Skeggs | ef8389a | 2011-02-01 10:07:32 +1000 | [diff] [blame] | 79 | struct nv50_display *disp = nv50_display(evo->dev); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 80 | struct nouveau_gpuobj *obj = NULL; |
| 81 | int ret; |
| 82 | |
Ben Skeggs | 59c0f57 | 2011-02-01 10:24:41 +1000 | [diff] [blame] | 83 | ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 84 | if (ret) |
| 85 | return ret; |
| 86 | obj->engine = NVOBJ_ENGINE_DISPLAY; |
| 87 | |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 88 | nv50_evo_dmaobj_init(obj, memtype, base, size); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 89 | |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 90 | ret = nouveau_ramht_insert(evo, handle, obj); |
| 91 | if (ret) |
| 92 | goto out; |
| 93 | |
| 94 | if (pobj) |
| 95 | nouveau_gpuobj_ref(obj, pobj); |
| 96 | out: |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 97 | nouveau_gpuobj_ref(NULL, &obj); |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 98 | return ret; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | static int |
Ben Skeggs | 30d8181 | 2011-02-01 10:39:45 +1000 | [diff] [blame] | 102 | nv50_evo_channel_new(struct drm_device *dev, int chid, |
| 103 | struct nouveau_channel **pevo) |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 104 | { |
Ben Skeggs | ef8389a | 2011-02-01 10:07:32 +1000 | [diff] [blame] | 105 | struct nv50_display *disp = nv50_display(dev); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 106 | struct nouveau_channel *evo; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 107 | int ret; |
| 108 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 109 | evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL); |
| 110 | if (!evo) |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 111 | return -ENOMEM; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 112 | *pevo = evo; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 113 | |
Ben Skeggs | 30d8181 | 2011-02-01 10:39:45 +1000 | [diff] [blame] | 114 | evo->id = chid; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 115 | evo->dev = dev; |
| 116 | evo->user_get = 4; |
| 117 | evo->user_put = 0; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 118 | |
| 119 | ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0, |
Ben Skeggs | d550c41 | 2011-02-16 08:41:56 +1000 | [diff] [blame] | 120 | &evo->pushbuf_bo); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 121 | if (ret == 0) |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 122 | ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 123 | if (ret) { |
| 124 | NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 125 | nv50_evo_channel_del(pevo); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 126 | return ret; |
| 127 | } |
| 128 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 129 | ret = nouveau_bo_map(evo->pushbuf_bo); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 130 | if (ret) { |
| 131 | NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 132 | nv50_evo_channel_del(pevo); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 133 | return ret; |
| 134 | } |
| 135 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 136 | evo->user = ioremap(pci_resource_start(dev->pdev, 0) + |
| 137 | NV50_PDISPLAY_USER(evo->id), PAGE_SIZE); |
| 138 | if (!evo->user) { |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 139 | NV_ERROR(dev, "Error mapping EVO control regs.\n"); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 140 | nv50_evo_channel_del(pevo); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 141 | return -ENOMEM; |
| 142 | } |
| 143 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 144 | /* bind primary evo channel's ramht to the channel */ |
Ben Skeggs | 59c0f57 | 2011-02-01 10:24:41 +1000 | [diff] [blame] | 145 | if (disp->master && evo != disp->master) |
| 146 | nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 147 | |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | static int |
| 152 | nv50_evo_channel_init(struct nouveau_channel *evo) |
| 153 | { |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 154 | struct drm_device *dev = evo->dev; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 155 | int id = evo->id, ret, i; |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 156 | u64 pushbuf = evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 157 | u32 tmp; |
| 158 | |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 159 | tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)); |
| 160 | if ((tmp & 0x009f0000) == 0x00020000) |
| 161 | nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 162 | |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 163 | tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)); |
| 164 | if ((tmp & 0x003f0000) == 0x00030000) |
| 165 | nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 166 | |
| 167 | /* initialise fifo */ |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 168 | nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 | |
| 169 | NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM | |
| 170 | NV50_PDISPLAY_EVO_DMA_CB_VALID); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 171 | nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000); |
| 172 | nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id); |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 173 | nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA, |
| 174 | NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED); |
| 175 | |
| 176 | nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000); |
| 177 | nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 | |
| 178 | NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 179 | if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) { |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 180 | NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id, |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 181 | nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 182 | return -EBUSY; |
| 183 | } |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 184 | |
| 185 | /* enable error reporting on the channel */ |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 186 | nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 187 | |
| 188 | evo->dma.max = (4096/4) - 2; |
David Dillow | 59197c0 | 2011-03-21 21:41:47 +1000 | [diff] [blame] | 189 | evo->dma.max &= ~7; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 190 | evo->dma.put = 0; |
| 191 | evo->dma.cur = evo->dma.put; |
| 192 | evo->dma.free = evo->dma.max - evo->dma.cur; |
| 193 | |
| 194 | ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS); |
| 195 | if (ret) |
| 196 | return ret; |
| 197 | |
| 198 | for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) |
| 199 | OUT_RING(evo, 0); |
| 200 | |
| 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | static void |
| 205 | nv50_evo_channel_fini(struct nouveau_channel *evo) |
| 206 | { |
| 207 | struct drm_device *dev = evo->dev; |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 208 | int id = evo->id; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 209 | |
Ben Skeggs | 43ce028 | 2010-10-19 18:01:41 +1000 | [diff] [blame] | 210 | nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000); |
| 211 | nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000); |
| 212 | nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id)); |
| 213 | nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000); |
| 214 | if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) { |
| 215 | NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id, |
| 216 | nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 217 | } |
| 218 | } |
| 219 | |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 220 | static void |
| 221 | nv50_evo_destroy(struct drm_device *dev) |
| 222 | { |
| 223 | struct nv50_display *disp = nv50_display(dev); |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 224 | int i; |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 225 | |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 226 | for (i = 0; i < 2; i++) { |
| 227 | if (disp->crtc[i].sem.bo) { |
| 228 | nouveau_bo_unmap(disp->crtc[i].sem.bo); |
| 229 | nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo); |
| 230 | } |
| 231 | nv50_evo_channel_del(&disp->crtc[i].sync); |
| 232 | } |
Ben Skeggs | 60f60bf | 2011-02-03 15:46:14 +1000 | [diff] [blame] | 233 | nouveau_gpuobj_ref(NULL, &disp->ntfy); |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 234 | nv50_evo_channel_del(&disp->master); |
| 235 | } |
| 236 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 237 | static int |
| 238 | nv50_evo_create(struct drm_device *dev) |
| 239 | { |
| 240 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | ef8389a | 2011-02-01 10:07:32 +1000 | [diff] [blame] | 241 | struct nv50_display *disp = nv50_display(dev); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 242 | struct nouveau_gpuobj *ramht = NULL; |
| 243 | struct nouveau_channel *evo; |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 244 | int ret, i, j; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 245 | |
| 246 | /* create primary evo channel, the one we use for modesetting |
| 247 | * purporses |
| 248 | */ |
Ben Skeggs | 30d8181 | 2011-02-01 10:39:45 +1000 | [diff] [blame] | 249 | ret = nv50_evo_channel_new(dev, 0, &disp->master); |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 250 | if (ret) |
| 251 | return ret; |
Ben Skeggs | 59c0f57 | 2011-02-01 10:24:41 +1000 | [diff] [blame] | 252 | evo = disp->master; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 253 | |
| 254 | /* setup object management on it, any other evo channel will |
| 255 | * use this also as there's no per-channel support on the |
| 256 | * hardware |
| 257 | */ |
Ben Skeggs | 8888cb1 | 2010-10-20 15:35:28 +1000 | [diff] [blame] | 258 | ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536, |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 259 | NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin); |
| 260 | if (ret) { |
| 261 | NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret); |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 262 | goto err; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | ret = drm_mm_init(&evo->ramin_heap, 0, 32768); |
| 266 | if (ret) { |
| 267 | NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret); |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 268 | goto err; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht); |
| 272 | if (ret) { |
| 273 | NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret); |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 274 | goto err; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | ret = nouveau_ramht_new(dev, ramht, &evo->ramht); |
| 278 | nouveau_gpuobj_ref(NULL, &ramht); |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 279 | if (ret) |
| 280 | goto err; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 281 | |
Ben Skeggs | 60f60bf | 2011-02-03 15:46:14 +1000 | [diff] [blame] | 282 | /* not sure exactly what this is.. |
| 283 | * |
| 284 | * the first dword of the structure is used by nvidia to wait on |
| 285 | * full completion of an EVO "update" command. |
| 286 | * |
| 287 | * method 0x8c on the master evo channel will fill a lot more of |
| 288 | * this structure with some undefined info |
| 289 | */ |
| 290 | ret = nouveau_gpuobj_new(dev, disp->master, 0x1000, 0, |
| 291 | NVOBJ_FLAG_ZERO_ALLOC, &disp->ntfy); |
| 292 | if (ret) |
| 293 | goto err; |
| 294 | |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 295 | ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000, |
| 296 | disp->ntfy->vinst, disp->ntfy->size, NULL); |
Ben Skeggs | 60f60bf | 2011-02-03 15:46:14 +1000 | [diff] [blame] | 297 | if (ret) |
| 298 | goto err; |
| 299 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 300 | /* create some default objects for the scanout memtypes we support */ |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 301 | ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000, |
| 302 | 0, dev_priv->vram_size, NULL); |
| 303 | if (ret) |
| 304 | goto err; |
Ben Skeggs | 6d86951 | 2010-12-08 11:19:30 +1000 | [diff] [blame] | 305 | |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 306 | ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000, |
| 307 | 0, dev_priv->vram_size, NULL); |
| 308 | if (ret) |
| 309 | goto err; |
Ben Skeggs | 6d86951 | 2010-12-08 11:19:30 +1000 | [diff] [blame] | 310 | |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 311 | ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 | |
| 312 | (dev_priv->chipset < 0xc0 ? 0x7a00 : 0xfe00), |
| 313 | 0, dev_priv->vram_size, NULL); |
| 314 | if (ret) |
| 315 | goto err; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 316 | |
Ben Skeggs | 292deb7 | 2011-02-07 13:08:16 +1000 | [diff] [blame] | 317 | ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 | |
| 318 | (dev_priv->chipset < 0xc0 ? 0x7000 : 0xfe00), |
| 319 | 0, dev_priv->vram_size, NULL); |
| 320 | if (ret) |
| 321 | goto err; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 322 | |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 323 | /* create "display sync" channels and other structures we need |
| 324 | * to implement page flipping |
| 325 | */ |
| 326 | for (i = 0; i < 2; i++) { |
| 327 | struct nv50_display_crtc *dispc = &disp->crtc[i]; |
| 328 | u64 offset; |
| 329 | |
| 330 | ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync); |
| 331 | if (ret) |
| 332 | goto err; |
| 333 | |
| 334 | ret = nouveau_bo_new(dev, NULL, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
Ben Skeggs | d550c41 | 2011-02-16 08:41:56 +1000 | [diff] [blame] | 335 | 0, 0x0000, &dispc->sem.bo); |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 336 | if (!ret) { |
| 337 | offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT; |
| 338 | |
| 339 | ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM); |
| 340 | if (!ret) |
| 341 | ret = nouveau_bo_map(dispc->sem.bo); |
| 342 | if (ret) |
| 343 | nouveau_bo_ref(NULL, &dispc->sem.bo); |
| 344 | } |
| 345 | |
| 346 | if (ret) |
| 347 | goto err; |
| 348 | |
| 349 | ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000, |
| 350 | offset, 4096, NULL); |
| 351 | if (ret) |
| 352 | goto err; |
| 353 | |
| 354 | ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000, |
| 355 | 0, dev_priv->vram_size, NULL); |
| 356 | if (ret) |
| 357 | goto err; |
| 358 | |
| 359 | ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 | |
| 360 | (dev_priv->chipset < 0xc0 ? |
| 361 | 0x7a00 : 0xfe00), |
| 362 | 0, dev_priv->vram_size, NULL); |
| 363 | if (ret) |
| 364 | goto err; |
| 365 | |
| 366 | ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 | |
| 367 | (dev_priv->chipset < 0xc0 ? |
| 368 | 0x7000 : 0xfe00), |
| 369 | 0, dev_priv->vram_size, NULL); |
| 370 | if (ret) |
| 371 | goto err; |
| 372 | |
| 373 | for (j = 0; j < 4096; j += 4) |
| 374 | nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000); |
| 375 | dispc->sem.offset = 0; |
| 376 | } |
| 377 | |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 378 | return 0; |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 379 | |
| 380 | err: |
| 381 | nv50_evo_destroy(dev); |
| 382 | return ret; |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 383 | } |
| 384 | |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 385 | int |
| 386 | nv50_evo_init(struct drm_device *dev) |
| 387 | { |
Ben Skeggs | ef8389a | 2011-02-01 10:07:32 +1000 | [diff] [blame] | 388 | struct nv50_display *disp = nv50_display(dev); |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 389 | int ret, i; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 390 | |
Ben Skeggs | 59c0f57 | 2011-02-01 10:24:41 +1000 | [diff] [blame] | 391 | if (!disp->master) { |
Ben Skeggs | 1e96268 | 2010-10-19 14:18:06 +1000 | [diff] [blame] | 392 | ret = nv50_evo_create(dev); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 393 | if (ret) |
| 394 | return ret; |
| 395 | } |
| 396 | |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 397 | ret = nv50_evo_channel_init(disp->master); |
| 398 | if (ret) |
| 399 | return ret; |
| 400 | |
| 401 | for (i = 0; i < 2; i++) { |
| 402 | ret = nv50_evo_channel_init(disp->crtc[i].sync); |
| 403 | if (ret) |
| 404 | return ret; |
| 405 | } |
| 406 | |
| 407 | return 0; |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | void |
| 411 | nv50_evo_fini(struct drm_device *dev) |
| 412 | { |
Ben Skeggs | ef8389a | 2011-02-01 10:07:32 +1000 | [diff] [blame] | 413 | struct nv50_display *disp = nv50_display(dev); |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 414 | int i; |
| 415 | |
| 416 | for (i = 0; i < 2; i++) { |
| 417 | if (disp->crtc[i].sync) |
| 418 | nv50_evo_channel_fini(disp->crtc[i].sync); |
| 419 | } |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 420 | |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 421 | if (disp->master) |
Ben Skeggs | 59c0f57 | 2011-02-01 10:24:41 +1000 | [diff] [blame] | 422 | nv50_evo_channel_fini(disp->master); |
Ben Skeggs | cdccc70 | 2011-02-07 13:29:23 +1000 | [diff] [blame] | 423 | |
Ben Skeggs | 33f409d | 2011-02-01 10:59:07 +1000 | [diff] [blame] | 424 | nv50_evo_destroy(dev); |
Ben Skeggs | b7bc613 | 2010-10-19 13:05:51 +1000 | [diff] [blame] | 425 | } |