blob: ff0f5ba14b2cfb60223a19455772fddca719951b [file] [log] [blame]
Michael Buesche4d6b792007-09-18 15:39:42 -04001/*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28*/
29
30#include "b43.h"
31#include "dma.h"
32#include "main.h"
33#include "debugfs.h"
34#include "xmit.h"
35
36#include <linux/dma-mapping.h>
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
Michael Buesch280d0e12007-12-26 18:26:17 +010040#include <linux/etherdevice.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090041#include <linux/slab.h>
Michael Buesch57df40d2008-03-07 15:50:02 +010042#include <asm/div64.h>
Michael Buesch280d0e12007-12-26 18:26:17 +010043
Michael Buesche4d6b792007-09-18 15:39:42 -040044
Michael Bueschbdceeb22009-02-19 23:45:43 +010045/* Required number of TX DMA slots per TX frame.
46 * This currently is 2, because we put the header and the ieee80211 frame
47 * into separate slots. */
48#define TX_SLOTS_PER_FRAME 2
49
50
Michael Buesche4d6b792007-09-18 15:39:42 -040051/* 32bit DMA ops. */
52static
53struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
54 int slot,
55 struct b43_dmadesc_meta **meta)
56{
57 struct b43_dmadesc32 *desc;
58
59 *meta = &(ring->meta[slot]);
60 desc = ring->descbase;
61 desc = &(desc[slot]);
62
63 return (struct b43_dmadesc_generic *)desc;
64}
65
66static void op32_fill_descriptor(struct b43_dmaring *ring,
67 struct b43_dmadesc_generic *desc,
68 dma_addr_t dmaaddr, u16 bufsize,
69 int start, int end, int irq)
70{
71 struct b43_dmadesc32 *descbase = ring->descbase;
72 int slot;
73 u32 ctl;
74 u32 addr;
75 u32 addrext;
76
77 slot = (int)(&(desc->dma32) - descbase);
78 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
79
80 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
81 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
82 >> SSB_DMA_TRANSLATION_SHIFT;
83 addr |= ssb_dma_translation(ring->dev->dev);
Michael Buesch8eccb532009-02-19 23:39:26 +010084 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
Michael Buesche4d6b792007-09-18 15:39:42 -040085 if (slot == ring->nr_slots - 1)
86 ctl |= B43_DMA32_DCTL_DTABLEEND;
87 if (start)
88 ctl |= B43_DMA32_DCTL_FRAMESTART;
89 if (end)
90 ctl |= B43_DMA32_DCTL_FRAMEEND;
91 if (irq)
92 ctl |= B43_DMA32_DCTL_IRQ;
93 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
94 & B43_DMA32_DCTL_ADDREXT_MASK;
95
96 desc->dma32.control = cpu_to_le32(ctl);
97 desc->dma32.address = cpu_to_le32(addr);
98}
99
100static void op32_poke_tx(struct b43_dmaring *ring, int slot)
101{
102 b43_dma_write(ring, B43_DMA32_TXINDEX,
103 (u32) (slot * sizeof(struct b43_dmadesc32)));
104}
105
106static void op32_tx_suspend(struct b43_dmaring *ring)
107{
108 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
109 | B43_DMA32_TXSUSPEND);
110}
111
112static void op32_tx_resume(struct b43_dmaring *ring)
113{
114 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
115 & ~B43_DMA32_TXSUSPEND);
116}
117
118static int op32_get_current_rxslot(struct b43_dmaring *ring)
119{
120 u32 val;
121
122 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
123 val &= B43_DMA32_RXDPTR;
124
125 return (val / sizeof(struct b43_dmadesc32));
126}
127
128static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
129{
130 b43_dma_write(ring, B43_DMA32_RXINDEX,
131 (u32) (slot * sizeof(struct b43_dmadesc32)));
132}
133
134static const struct b43_dma_ops dma32_ops = {
135 .idx2desc = op32_idx2desc,
136 .fill_descriptor = op32_fill_descriptor,
137 .poke_tx = op32_poke_tx,
138 .tx_suspend = op32_tx_suspend,
139 .tx_resume = op32_tx_resume,
140 .get_current_rxslot = op32_get_current_rxslot,
141 .set_current_rxslot = op32_set_current_rxslot,
142};
143
144/* 64bit DMA ops. */
145static
146struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
147 int slot,
148 struct b43_dmadesc_meta **meta)
149{
150 struct b43_dmadesc64 *desc;
151
152 *meta = &(ring->meta[slot]);
153 desc = ring->descbase;
154 desc = &(desc[slot]);
155
156 return (struct b43_dmadesc_generic *)desc;
157}
158
159static void op64_fill_descriptor(struct b43_dmaring *ring,
160 struct b43_dmadesc_generic *desc,
161 dma_addr_t dmaaddr, u16 bufsize,
162 int start, int end, int irq)
163{
164 struct b43_dmadesc64 *descbase = ring->descbase;
165 int slot;
166 u32 ctl0 = 0, ctl1 = 0;
167 u32 addrlo, addrhi;
168 u32 addrext;
169
170 slot = (int)(&(desc->dma64) - descbase);
171 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
174 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT;
Larry Finger013978b2007-11-26 10:29:47 -0600177 addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
Michael Buesche4d6b792007-09-18 15:39:42 -0400178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
180 if (start)
181 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
182 if (end)
183 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
184 if (irq)
185 ctl0 |= B43_DMA64_DCTL0_IRQ;
Michael Buesch8eccb532009-02-19 23:39:26 +0100186 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
Michael Buesche4d6b792007-09-18 15:39:42 -0400187 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
188 & B43_DMA64_DCTL1_ADDREXT_MASK;
189
190 desc->dma64.control0 = cpu_to_le32(ctl0);
191 desc->dma64.control1 = cpu_to_le32(ctl1);
192 desc->dma64.address_low = cpu_to_le32(addrlo);
193 desc->dma64.address_high = cpu_to_le32(addrhi);
194}
195
196static void op64_poke_tx(struct b43_dmaring *ring, int slot)
197{
198 b43_dma_write(ring, B43_DMA64_TXINDEX,
199 (u32) (slot * sizeof(struct b43_dmadesc64)));
200}
201
202static void op64_tx_suspend(struct b43_dmaring *ring)
203{
204 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
205 | B43_DMA64_TXSUSPEND);
206}
207
208static void op64_tx_resume(struct b43_dmaring *ring)
209{
210 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
211 & ~B43_DMA64_TXSUSPEND);
212}
213
214static int op64_get_current_rxslot(struct b43_dmaring *ring)
215{
216 u32 val;
217
218 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
219 val &= B43_DMA64_RXSTATDPTR;
220
221 return (val / sizeof(struct b43_dmadesc64));
222}
223
224static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
225{
226 b43_dma_write(ring, B43_DMA64_RXINDEX,
227 (u32) (slot * sizeof(struct b43_dmadesc64)));
228}
229
230static const struct b43_dma_ops dma64_ops = {
231 .idx2desc = op64_idx2desc,
232 .fill_descriptor = op64_fill_descriptor,
233 .poke_tx = op64_poke_tx,
234 .tx_suspend = op64_tx_suspend,
235 .tx_resume = op64_tx_resume,
236 .get_current_rxslot = op64_get_current_rxslot,
237 .set_current_rxslot = op64_set_current_rxslot,
238};
239
240static inline int free_slots(struct b43_dmaring *ring)
241{
242 return (ring->nr_slots - ring->used_slots);
243}
244
245static inline int next_slot(struct b43_dmaring *ring, int slot)
246{
247 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
248 if (slot == ring->nr_slots - 1)
249 return 0;
250 return slot + 1;
251}
252
253static inline int prev_slot(struct b43_dmaring *ring, int slot)
254{
255 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
256 if (slot == 0)
257 return ring->nr_slots - 1;
258 return slot - 1;
259}
260
261#ifdef CONFIG_B43_DEBUG
262static void update_max_used_slots(struct b43_dmaring *ring,
263 int current_used_slots)
264{
265 if (current_used_slots <= ring->max_used_slots)
266 return;
267 ring->max_used_slots = current_used_slots;
268 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
269 b43dbg(ring->dev->wl,
270 "max_used_slots increased to %d on %s ring %d\n",
271 ring->max_used_slots,
272 ring->tx ? "TX" : "RX", ring->index);
273 }
274}
275#else
276static inline
277 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
278{
279}
280#endif /* DEBUG */
281
282/* Request a slot for usage. */
283static inline int request_slot(struct b43_dmaring *ring)
284{
285 int slot;
286
287 B43_WARN_ON(!ring->tx);
288 B43_WARN_ON(ring->stopped);
289 B43_WARN_ON(free_slots(ring) == 0);
290
291 slot = next_slot(ring, ring->current_slot);
292 ring->current_slot = slot;
293 ring->used_slots++;
294
295 update_max_used_slots(ring, ring->used_slots);
296
297 return slot;
298}
299
Michael Bueschb79caa62008-02-05 12:50:41 +0100300static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
Michael Buesche4d6b792007-09-18 15:39:42 -0400301{
302 static const u16 map64[] = {
303 B43_MMIO_DMA64_BASE0,
304 B43_MMIO_DMA64_BASE1,
305 B43_MMIO_DMA64_BASE2,
306 B43_MMIO_DMA64_BASE3,
307 B43_MMIO_DMA64_BASE4,
308 B43_MMIO_DMA64_BASE5,
309 };
310 static const u16 map32[] = {
311 B43_MMIO_DMA32_BASE0,
312 B43_MMIO_DMA32_BASE1,
313 B43_MMIO_DMA32_BASE2,
314 B43_MMIO_DMA32_BASE3,
315 B43_MMIO_DMA32_BASE4,
316 B43_MMIO_DMA32_BASE5,
317 };
318
Michael Bueschb79caa62008-02-05 12:50:41 +0100319 if (type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400320 B43_WARN_ON(!(controller_idx >= 0 &&
321 controller_idx < ARRAY_SIZE(map64)));
322 return map64[controller_idx];
323 }
324 B43_WARN_ON(!(controller_idx >= 0 &&
325 controller_idx < ARRAY_SIZE(map32)));
326 return map32[controller_idx];
327}
328
329static inline
330 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
331 unsigned char *buf, size_t len, int tx)
332{
333 dma_addr_t dmaaddr;
334
335 if (tx) {
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700336 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
337 buf, len, DMA_TO_DEVICE);
Michael Buesche4d6b792007-09-18 15:39:42 -0400338 } else {
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700339 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
340 buf, len, DMA_FROM_DEVICE);
Michael Buesche4d6b792007-09-18 15:39:42 -0400341 }
342
343 return dmaaddr;
344}
345
346static inline
347 void unmap_descbuffer(struct b43_dmaring *ring,
348 dma_addr_t addr, size_t len, int tx)
349{
350 if (tx) {
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700351 dma_unmap_single(ring->dev->dev->dma_dev,
352 addr, len, DMA_TO_DEVICE);
Michael Buesche4d6b792007-09-18 15:39:42 -0400353 } else {
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700354 dma_unmap_single(ring->dev->dev->dma_dev,
355 addr, len, DMA_FROM_DEVICE);
Michael Buesche4d6b792007-09-18 15:39:42 -0400356 }
357}
358
359static inline
360 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
361 dma_addr_t addr, size_t len)
362{
363 B43_WARN_ON(ring->tx);
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700364 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
Michael Bueschf2257632008-06-20 11:50:29 +0200365 addr, len, DMA_FROM_DEVICE);
Michael Buesche4d6b792007-09-18 15:39:42 -0400366}
367
368static inline
369 void sync_descbuffer_for_device(struct b43_dmaring *ring,
370 dma_addr_t addr, size_t len)
371{
372 B43_WARN_ON(ring->tx);
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700373 dma_sync_single_for_device(ring->dev->dev->dma_dev,
374 addr, len, DMA_FROM_DEVICE);
Michael Buesche4d6b792007-09-18 15:39:42 -0400375}
376
377static inline
378 void free_descriptor_buffer(struct b43_dmaring *ring,
379 struct b43_dmadesc_meta *meta)
380{
381 if (meta->skb) {
382 dev_kfree_skb_any(meta->skb);
383 meta->skb = NULL;
384 }
385}
386
387static int alloc_ringmemory(struct b43_dmaring *ring)
388{
John W. Linville55afc802009-12-29 14:07:42 -0500389 gfp_t flags = GFP_KERNEL;
Michael Buesche4d6b792007-09-18 15:39:42 -0400390
John W. Linville55afc802009-12-29 14:07:42 -0500391 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
392 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
393 * has shown that 4K is sufficient for the latter as long as the buffer
394 * does not cross an 8K boundary.
395 *
396 * For unknown reasons - possibly a hardware error - the BCM4311 rev
397 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
398 * which accounts for the GFP_DMA flag below.
399 *
400 * The flags here must match the flags in free_ringmemory below!
Larry Finger013978b2007-11-26 10:29:47 -0600401 */
Michael Bueschb79caa62008-02-05 12:50:41 +0100402 if (ring->type == B43_DMA_64BIT)
John W. Linville55afc802009-12-29 14:07:42 -0500403 flags |= GFP_DMA;
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700404 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
405 B43_DMA_RINGMEMSIZE,
406 &(ring->dmabase), flags);
John W. Linville55afc802009-12-29 14:07:42 -0500407 if (!ring->descbase) {
408 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
Michael Buesche4d6b792007-09-18 15:39:42 -0400409 return -ENOMEM;
410 }
John W. Linville55afc802009-12-29 14:07:42 -0500411 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
Michael Buesche4d6b792007-09-18 15:39:42 -0400412
413 return 0;
414}
415
416static void free_ringmemory(struct b43_dmaring *ring)
417{
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700418 dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
419 ring->descbase, ring->dmabase);
Michael Buesche4d6b792007-09-18 15:39:42 -0400420}
421
422/* Reset the RX DMA channel */
Michael Bueschb79caa62008-02-05 12:50:41 +0100423static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
424 enum b43_dmatype type)
Michael Buesche4d6b792007-09-18 15:39:42 -0400425{
426 int i;
427 u32 value;
428 u16 offset;
429
430 might_sleep();
431
Michael Bueschb79caa62008-02-05 12:50:41 +0100432 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
Michael Buesche4d6b792007-09-18 15:39:42 -0400433 b43_write32(dev, mmio_base + offset, 0);
434 for (i = 0; i < 10; i++) {
Michael Bueschb79caa62008-02-05 12:50:41 +0100435 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
436 B43_DMA32_RXSTATUS;
Michael Buesche4d6b792007-09-18 15:39:42 -0400437 value = b43_read32(dev, mmio_base + offset);
Michael Bueschb79caa62008-02-05 12:50:41 +0100438 if (type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400439 value &= B43_DMA64_RXSTAT;
440 if (value == B43_DMA64_RXSTAT_DISABLED) {
441 i = -1;
442 break;
443 }
444 } else {
445 value &= B43_DMA32_RXSTATE;
446 if (value == B43_DMA32_RXSTAT_DISABLED) {
447 i = -1;
448 break;
449 }
450 }
451 msleep(1);
452 }
453 if (i != -1) {
454 b43err(dev->wl, "DMA RX reset timed out\n");
455 return -ENODEV;
456 }
457
458 return 0;
459}
460
Larry Finger013978b2007-11-26 10:29:47 -0600461/* Reset the TX DMA channel */
Michael Bueschb79caa62008-02-05 12:50:41 +0100462static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
463 enum b43_dmatype type)
Michael Buesche4d6b792007-09-18 15:39:42 -0400464{
465 int i;
466 u32 value;
467 u16 offset;
468
469 might_sleep();
470
471 for (i = 0; i < 10; i++) {
Michael Bueschb79caa62008-02-05 12:50:41 +0100472 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
473 B43_DMA32_TXSTATUS;
Michael Buesche4d6b792007-09-18 15:39:42 -0400474 value = b43_read32(dev, mmio_base + offset);
Michael Bueschb79caa62008-02-05 12:50:41 +0100475 if (type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400476 value &= B43_DMA64_TXSTAT;
477 if (value == B43_DMA64_TXSTAT_DISABLED ||
478 value == B43_DMA64_TXSTAT_IDLEWAIT ||
479 value == B43_DMA64_TXSTAT_STOPPED)
480 break;
481 } else {
482 value &= B43_DMA32_TXSTATE;
483 if (value == B43_DMA32_TXSTAT_DISABLED ||
484 value == B43_DMA32_TXSTAT_IDLEWAIT ||
485 value == B43_DMA32_TXSTAT_STOPPED)
486 break;
487 }
488 msleep(1);
489 }
Michael Bueschb79caa62008-02-05 12:50:41 +0100490 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
Michael Buesche4d6b792007-09-18 15:39:42 -0400491 b43_write32(dev, mmio_base + offset, 0);
492 for (i = 0; i < 10; i++) {
Michael Bueschb79caa62008-02-05 12:50:41 +0100493 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
494 B43_DMA32_TXSTATUS;
Michael Buesche4d6b792007-09-18 15:39:42 -0400495 value = b43_read32(dev, mmio_base + offset);
Michael Bueschb79caa62008-02-05 12:50:41 +0100496 if (type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400497 value &= B43_DMA64_TXSTAT;
498 if (value == B43_DMA64_TXSTAT_DISABLED) {
499 i = -1;
500 break;
501 }
502 } else {
503 value &= B43_DMA32_TXSTATE;
504 if (value == B43_DMA32_TXSTAT_DISABLED) {
505 i = -1;
506 break;
507 }
508 }
509 msleep(1);
510 }
511 if (i != -1) {
512 b43err(dev->wl, "DMA TX reset timed out\n");
513 return -ENODEV;
514 }
515 /* ensure the reset is completed. */
516 msleep(1);
517
518 return 0;
519}
520
Michael Bueschb79caa62008-02-05 12:50:41 +0100521/* Check if a DMA mapping address is invalid. */
522static bool b43_dma_mapping_error(struct b43_dmaring *ring,
523 dma_addr_t addr,
Michael Bueschffa92562008-03-22 22:04:45 +0100524 size_t buffersize, bool dma_to_device)
Michael Bueschb79caa62008-02-05 12:50:41 +0100525{
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700526 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
Michael Bueschb79caa62008-02-05 12:50:41 +0100527 return 1;
528
John W. Linville55afc802009-12-29 14:07:42 -0500529 switch (ring->type) {
530 case B43_DMA_30BIT:
531 if ((u64)addr + buffersize > (1ULL << 30))
532 goto address_error;
533 break;
534 case B43_DMA_32BIT:
535 if ((u64)addr + buffersize > (1ULL << 32))
536 goto address_error;
537 break;
538 case B43_DMA_64BIT:
539 /* Currently we can't have addresses beyond
540 * 64bit in the kernel. */
541 break;
Michael Bueschb79caa62008-02-05 12:50:41 +0100542 }
543
544 /* The address is OK. */
545 return 0;
John W. Linville55afc802009-12-29 14:07:42 -0500546
547address_error:
548 /* We can't support this address. Unmap it again. */
549 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
550
551 return 1;
Michael Bueschb79caa62008-02-05 12:50:41 +0100552}
553
Michael Bueschec9a1d82009-03-27 22:51:58 +0100554static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
555{
556 unsigned char *f = skb->data + ring->frameoffset;
557
558 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
559}
560
561static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
562{
563 struct b43_rxhdr_fw4 *rxhdr;
564 unsigned char *frame;
565
566 /* This poisons the RX buffer to detect DMA failures. */
567
568 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
569 rxhdr->frame_len = 0;
570
571 B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
572 frame = skb->data + ring->frameoffset;
573 memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
574}
575
Michael Buesche4d6b792007-09-18 15:39:42 -0400576static int setup_rx_descbuffer(struct b43_dmaring *ring,
577 struct b43_dmadesc_generic *desc,
578 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
579{
Michael Buesche4d6b792007-09-18 15:39:42 -0400580 dma_addr_t dmaaddr;
581 struct sk_buff *skb;
582
583 B43_WARN_ON(ring->tx);
584
585 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
586 if (unlikely(!skb))
587 return -ENOMEM;
Michael Bueschec9a1d82009-03-27 22:51:58 +0100588 b43_poison_rx_buffer(ring, skb);
Michael Buesche4d6b792007-09-18 15:39:42 -0400589 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
Michael Bueschffa92562008-03-22 22:04:45 +0100590 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400591 /* ugh. try to realloc in zone_dma */
592 gfp_flags |= GFP_DMA;
593
594 dev_kfree_skb_any(skb);
595
596 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
597 if (unlikely(!skb))
598 return -ENOMEM;
Michael Bueschec9a1d82009-03-27 22:51:58 +0100599 b43_poison_rx_buffer(ring, skb);
Michael Buesche4d6b792007-09-18 15:39:42 -0400600 dmaaddr = map_descbuffer(ring, skb->data,
601 ring->rx_buffersize, 0);
Michael Bueschbdceeb22009-02-19 23:45:43 +0100602 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
603 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
604 dev_kfree_skb_any(skb);
605 return -EIO;
606 }
Michael Buesche4d6b792007-09-18 15:39:42 -0400607 }
608
609 meta->skb = skb;
610 meta->dmaaddr = dmaaddr;
611 ring->ops->fill_descriptor(ring, desc, dmaaddr,
612 ring->rx_buffersize, 0, 0, 0);
613
Michael Buesche4d6b792007-09-18 15:39:42 -0400614 return 0;
615}
616
617/* Allocate the initial descbuffers.
618 * This is used for an RX ring only.
619 */
620static int alloc_initial_descbuffers(struct b43_dmaring *ring)
621{
622 int i, err = -ENOMEM;
623 struct b43_dmadesc_generic *desc;
624 struct b43_dmadesc_meta *meta;
625
626 for (i = 0; i < ring->nr_slots; i++) {
627 desc = ring->ops->idx2desc(ring, i, &meta);
628
629 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
630 if (err) {
631 b43err(ring->dev->wl,
632 "Failed to allocate initial descbuffers\n");
633 goto err_unwind;
634 }
635 }
636 mb();
637 ring->used_slots = ring->nr_slots;
638 err = 0;
639 out:
640 return err;
641
642 err_unwind:
643 for (i--; i >= 0; i--) {
644 desc = ring->ops->idx2desc(ring, i, &meta);
645
646 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
647 dev_kfree_skb(meta->skb);
648 }
649 goto out;
650}
651
652/* Do initial setup of the DMA controller.
653 * Reset the controller, write the ring busaddress
654 * and switch the "enable" bit on.
655 */
656static int dmacontroller_setup(struct b43_dmaring *ring)
657{
658 int err = 0;
659 u32 value;
660 u32 addrext;
661 u32 trans = ssb_dma_translation(ring->dev->dev);
662
663 if (ring->tx) {
Michael Bueschb79caa62008-02-05 12:50:41 +0100664 if (ring->type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400665 u64 ringbase = (u64) (ring->dmabase);
666
667 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
668 >> SSB_DMA_TRANSLATION_SHIFT;
669 value = B43_DMA64_TXENABLE;
670 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
671 & B43_DMA64_TXADDREXT_MASK;
672 b43_dma_write(ring, B43_DMA64_TXCTL, value);
673 b43_dma_write(ring, B43_DMA64_TXRINGLO,
674 (ringbase & 0xFFFFFFFF));
675 b43_dma_write(ring, B43_DMA64_TXRINGHI,
676 ((ringbase >> 32) &
677 ~SSB_DMA_TRANSLATION_MASK)
Larry Finger013978b2007-11-26 10:29:47 -0600678 | (trans << 1));
Michael Buesche4d6b792007-09-18 15:39:42 -0400679 } else {
680 u32 ringbase = (u32) (ring->dmabase);
681
682 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
683 >> SSB_DMA_TRANSLATION_SHIFT;
684 value = B43_DMA32_TXENABLE;
685 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
686 & B43_DMA32_TXADDREXT_MASK;
687 b43_dma_write(ring, B43_DMA32_TXCTL, value);
688 b43_dma_write(ring, B43_DMA32_TXRING,
689 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
690 | trans);
691 }
692 } else {
693 err = alloc_initial_descbuffers(ring);
694 if (err)
695 goto out;
Michael Bueschb79caa62008-02-05 12:50:41 +0100696 if (ring->type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400697 u64 ringbase = (u64) (ring->dmabase);
698
699 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
700 >> SSB_DMA_TRANSLATION_SHIFT;
701 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
702 value |= B43_DMA64_RXENABLE;
703 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
704 & B43_DMA64_RXADDREXT_MASK;
705 b43_dma_write(ring, B43_DMA64_RXCTL, value);
706 b43_dma_write(ring, B43_DMA64_RXRINGLO,
707 (ringbase & 0xFFFFFFFF));
708 b43_dma_write(ring, B43_DMA64_RXRINGHI,
709 ((ringbase >> 32) &
710 ~SSB_DMA_TRANSLATION_MASK)
Larry Finger013978b2007-11-26 10:29:47 -0600711 | (trans << 1));
712 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
713 sizeof(struct b43_dmadesc64));
Michael Buesche4d6b792007-09-18 15:39:42 -0400714 } else {
715 u32 ringbase = (u32) (ring->dmabase);
716
717 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
718 >> SSB_DMA_TRANSLATION_SHIFT;
719 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
720 value |= B43_DMA32_RXENABLE;
721 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
722 & B43_DMA32_RXADDREXT_MASK;
723 b43_dma_write(ring, B43_DMA32_RXCTL, value);
724 b43_dma_write(ring, B43_DMA32_RXRING,
725 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
726 | trans);
Larry Finger013978b2007-11-26 10:29:47 -0600727 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
728 sizeof(struct b43_dmadesc32));
Michael Buesche4d6b792007-09-18 15:39:42 -0400729 }
730 }
731
Larry Finger013978b2007-11-26 10:29:47 -0600732out:
Michael Buesche4d6b792007-09-18 15:39:42 -0400733 return err;
734}
735
736/* Shutdown the DMA controller. */
737static void dmacontroller_cleanup(struct b43_dmaring *ring)
738{
739 if (ring->tx) {
740 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
Michael Bueschb79caa62008-02-05 12:50:41 +0100741 ring->type);
742 if (ring->type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400743 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
744 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
745 } else
746 b43_dma_write(ring, B43_DMA32_TXRING, 0);
747 } else {
748 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
Michael Bueschb79caa62008-02-05 12:50:41 +0100749 ring->type);
750 if (ring->type == B43_DMA_64BIT) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400751 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
752 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
753 } else
754 b43_dma_write(ring, B43_DMA32_RXRING, 0);
755 }
756}
757
758static void free_all_descbuffers(struct b43_dmaring *ring)
759{
760 struct b43_dmadesc_generic *desc;
761 struct b43_dmadesc_meta *meta;
762 int i;
763
764 if (!ring->used_slots)
765 return;
766 for (i = 0; i < ring->nr_slots; i++) {
767 desc = ring->ops->idx2desc(ring, i, &meta);
768
Michael Buesch07681e22009-11-19 22:24:29 +0100769 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
Michael Buesche4d6b792007-09-18 15:39:42 -0400770 B43_WARN_ON(!ring->tx);
771 continue;
772 }
773 if (ring->tx) {
774 unmap_descbuffer(ring, meta->dmaaddr,
775 meta->skb->len, 1);
776 } else {
777 unmap_descbuffer(ring, meta->dmaaddr,
778 ring->rx_buffersize, 0);
779 }
780 free_descriptor_buffer(ring, meta);
781 }
782}
783
784static u64 supported_dma_mask(struct b43_wldev *dev)
785{
786 u32 tmp;
787 u16 mmio_base;
788
789 tmp = b43_read32(dev, SSB_TMSHIGH);
790 if (tmp & SSB_TMSHIGH_DMA64)
Yang Hongyang6a355282009-04-06 19:01:13 -0700791 return DMA_BIT_MASK(64);
Michael Buesche4d6b792007-09-18 15:39:42 -0400792 mmio_base = b43_dmacontroller_base(0, 0);
793 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
794 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
795 if (tmp & B43_DMA32_TXADDREXT_MASK)
Yang Hongyang284901a2009-04-06 19:01:15 -0700796 return DMA_BIT_MASK(32);
Michael Buesche4d6b792007-09-18 15:39:42 -0400797
Yang Hongyang28b76792009-04-06 19:01:17 -0700798 return DMA_BIT_MASK(30);
Michael Buesche4d6b792007-09-18 15:39:42 -0400799}
800
Michael Buesch5100d5a2008-03-29 21:01:16 +0100801static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
802{
Yang Hongyang28b76792009-04-06 19:01:17 -0700803 if (dmamask == DMA_BIT_MASK(30))
Michael Buesch5100d5a2008-03-29 21:01:16 +0100804 return B43_DMA_30BIT;
Yang Hongyang284901a2009-04-06 19:01:15 -0700805 if (dmamask == DMA_BIT_MASK(32))
Michael Buesch5100d5a2008-03-29 21:01:16 +0100806 return B43_DMA_32BIT;
Yang Hongyang6a355282009-04-06 19:01:13 -0700807 if (dmamask == DMA_BIT_MASK(64))
Michael Buesch5100d5a2008-03-29 21:01:16 +0100808 return B43_DMA_64BIT;
809 B43_WARN_ON(1);
810 return B43_DMA_30BIT;
811}
812
Michael Buesche4d6b792007-09-18 15:39:42 -0400813/* Main initialization function. */
814static
815struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
816 int controller_index,
Michael Bueschb79caa62008-02-05 12:50:41 +0100817 int for_tx,
818 enum b43_dmatype type)
Michael Buesche4d6b792007-09-18 15:39:42 -0400819{
820 struct b43_dmaring *ring;
Michael Buesch07681e22009-11-19 22:24:29 +0100821 int i, err;
Michael Buesche4d6b792007-09-18 15:39:42 -0400822 dma_addr_t dma_test;
823
824 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
825 if (!ring)
826 goto out;
827
Michael Buesch028118a2008-06-12 11:58:56 +0200828 ring->nr_slots = B43_RXRING_SLOTS;
Michael Buesche4d6b792007-09-18 15:39:42 -0400829 if (for_tx)
Michael Buesch028118a2008-06-12 11:58:56 +0200830 ring->nr_slots = B43_TXRING_SLOTS;
Michael Buesche4d6b792007-09-18 15:39:42 -0400831
Michael Buesch028118a2008-06-12 11:58:56 +0200832 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
Michael Buesche4d6b792007-09-18 15:39:42 -0400833 GFP_KERNEL);
834 if (!ring->meta)
835 goto err_kfree_ring;
Michael Buesch07681e22009-11-19 22:24:29 +0100836 for (i = 0; i < ring->nr_slots; i++)
837 ring->meta->skb = B43_DMA_PTR_POISON;
Michael Buesche4d6b792007-09-18 15:39:42 -0400838
Michael Buesch028118a2008-06-12 11:58:56 +0200839 ring->type = type;
Michael Buesche4d6b792007-09-18 15:39:42 -0400840 ring->dev = dev;
Michael Bueschb79caa62008-02-05 12:50:41 +0100841 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
Michael Buesche4d6b792007-09-18 15:39:42 -0400842 ring->index = controller_index;
Michael Bueschb79caa62008-02-05 12:50:41 +0100843 if (type == B43_DMA_64BIT)
Michael Buesche4d6b792007-09-18 15:39:42 -0400844 ring->ops = &dma64_ops;
845 else
846 ring->ops = &dma32_ops;
847 if (for_tx) {
848 ring->tx = 1;
849 ring->current_slot = -1;
850 } else {
851 if (ring->index == 0) {
852 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
853 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
Michael Buesche4d6b792007-09-18 15:39:42 -0400854 } else
855 B43_WARN_ON(1);
856 }
Michael Buesche4d6b792007-09-18 15:39:42 -0400857#ifdef CONFIG_B43_DEBUG
858 ring->last_injected_overflow = jiffies;
859#endif
860
Michael Buesch028118a2008-06-12 11:58:56 +0200861 if (for_tx) {
Michael Buesch2d071ca2009-02-20 12:24:52 +0100862 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
863 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
864
Michael Bueschbdceeb22009-02-19 23:45:43 +0100865 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
Michael Buesch028118a2008-06-12 11:58:56 +0200866 b43_txhdr_size(dev),
867 GFP_KERNEL);
868 if (!ring->txhdr_cache)
869 goto err_kfree_meta;
870
871 /* test for ability to dma to txhdr_cache */
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700872 dma_test = dma_map_single(dev->dev->dma_dev,
873 ring->txhdr_cache,
874 b43_txhdr_size(dev),
875 DMA_TO_DEVICE);
Michael Buesch028118a2008-06-12 11:58:56 +0200876
877 if (b43_dma_mapping_error(ring, dma_test,
878 b43_txhdr_size(dev), 1)) {
879 /* ugh realloc */
880 kfree(ring->txhdr_cache);
Michael Bueschbdceeb22009-02-19 23:45:43 +0100881 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
Michael Buesch028118a2008-06-12 11:58:56 +0200882 b43_txhdr_size(dev),
883 GFP_KERNEL | GFP_DMA);
884 if (!ring->txhdr_cache)
885 goto err_kfree_meta;
886
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700887 dma_test = dma_map_single(dev->dev->dma_dev,
888 ring->txhdr_cache,
889 b43_txhdr_size(dev),
890 DMA_TO_DEVICE);
Michael Buesch028118a2008-06-12 11:58:56 +0200891
892 if (b43_dma_mapping_error(ring, dma_test,
893 b43_txhdr_size(dev), 1)) {
894
895 b43err(dev->wl,
896 "TXHDR DMA allocation failed\n");
897 goto err_kfree_txhdr_cache;
898 }
899 }
900
FUJITA Tomonori718e8892010-06-03 19:37:36 -0700901 dma_unmap_single(dev->dev->dma_dev,
902 dma_test, b43_txhdr_size(dev),
903 DMA_TO_DEVICE);
Michael Buesch028118a2008-06-12 11:58:56 +0200904 }
905
Michael Buesche4d6b792007-09-18 15:39:42 -0400906 err = alloc_ringmemory(ring);
907 if (err)
908 goto err_kfree_txhdr_cache;
909 err = dmacontroller_setup(ring);
910 if (err)
911 goto err_free_ringmemory;
912
913 out:
914 return ring;
915
916 err_free_ringmemory:
917 free_ringmemory(ring);
918 err_kfree_txhdr_cache:
919 kfree(ring->txhdr_cache);
920 err_kfree_meta:
921 kfree(ring->meta);
922 err_kfree_ring:
923 kfree(ring);
924 ring = NULL;
925 goto out;
926}
927
Michael Buesch57df40d2008-03-07 15:50:02 +0100928#define divide(a, b) ({ \
929 typeof(a) __a = a; \
930 do_div(__a, b); \
931 __a; \
932 })
933
934#define modulo(a, b) ({ \
935 typeof(a) __a = a; \
936 do_div(__a, b); \
937 })
938
Michael Buesche4d6b792007-09-18 15:39:42 -0400939/* Main cleanup function. */
Michael Bueschb27faf82008-03-06 16:32:46 +0100940static void b43_destroy_dmaring(struct b43_dmaring *ring,
941 const char *ringname)
Michael Buesche4d6b792007-09-18 15:39:42 -0400942{
943 if (!ring)
944 return;
945
Michael Buesch57df40d2008-03-07 15:50:02 +0100946#ifdef CONFIG_B43_DEBUG
947 {
948 /* Print some statistics. */
949 u64 failed_packets = ring->nr_failed_tx_packets;
950 u64 succeed_packets = ring->nr_succeed_tx_packets;
951 u64 nr_packets = failed_packets + succeed_packets;
952 u64 permille_failed = 0, average_tries = 0;
953
954 if (nr_packets)
955 permille_failed = divide(failed_packets * 1000, nr_packets);
956 if (nr_packets)
957 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
958
959 b43dbg(ring->dev->wl, "DMA-%u %s: "
960 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
961 "Average tries %llu.%02llu\n",
962 (unsigned int)(ring->type), ringname,
963 ring->max_used_slots,
964 ring->nr_slots,
965 (unsigned long long)failed_packets,
Michael Buesch87d96112008-03-07 19:52:24 +0100966 (unsigned long long)nr_packets,
Michael Buesch57df40d2008-03-07 15:50:02 +0100967 (unsigned long long)divide(permille_failed, 10),
968 (unsigned long long)modulo(permille_failed, 10),
969 (unsigned long long)divide(average_tries, 100),
970 (unsigned long long)modulo(average_tries, 100));
971 }
972#endif /* DEBUG */
973
Michael Buesche4d6b792007-09-18 15:39:42 -0400974 /* Device IRQs are disabled prior entering this function,
975 * so no need to take care of concurrency with rx handler stuff.
976 */
977 dmacontroller_cleanup(ring);
978 free_all_descbuffers(ring);
979 free_ringmemory(ring);
980
981 kfree(ring->txhdr_cache);
982 kfree(ring->meta);
983 kfree(ring);
984}
985
Michael Bueschb27faf82008-03-06 16:32:46 +0100986#define destroy_ring(dma, ring) do { \
987 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
988 (dma)->ring = NULL; \
989 } while (0)
990
Michael Buesche4d6b792007-09-18 15:39:42 -0400991void b43_dma_free(struct b43_wldev *dev)
992{
Michael Buesch5100d5a2008-03-29 21:01:16 +0100993 struct b43_dma *dma;
994
995 if (b43_using_pio_transfers(dev))
996 return;
997 dma = &dev->dma;
Michael Buesche4d6b792007-09-18 15:39:42 -0400998
Michael Bueschb27faf82008-03-06 16:32:46 +0100999 destroy_ring(dma, rx_ring);
1000 destroy_ring(dma, tx_ring_AC_BK);
1001 destroy_ring(dma, tx_ring_AC_BE);
1002 destroy_ring(dma, tx_ring_AC_VI);
1003 destroy_ring(dma, tx_ring_AC_VO);
1004 destroy_ring(dma, tx_ring_mcast);
Michael Buesche4d6b792007-09-18 15:39:42 -04001005}
1006
Michael Buesch1033b3e2008-04-23 19:13:01 +02001007static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1008{
1009 u64 orig_mask = mask;
1010 bool fallback = 0;
1011 int err;
1012
1013 /* Try to set the DMA mask. If it fails, try falling back to a
1014 * lower mask, as we can always also support a lower one. */
1015 while (1) {
FUJITA Tomonori718e8892010-06-03 19:37:36 -07001016 err = dma_set_mask(dev->dev->dma_dev, mask);
1017 if (!err) {
1018 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1019 if (!err)
1020 break;
1021 }
Yang Hongyang6a355282009-04-06 19:01:13 -07001022 if (mask == DMA_BIT_MASK(64)) {
Yang Hongyang284901a2009-04-06 19:01:15 -07001023 mask = DMA_BIT_MASK(32);
Michael Buesch1033b3e2008-04-23 19:13:01 +02001024 fallback = 1;
1025 continue;
1026 }
Yang Hongyang284901a2009-04-06 19:01:15 -07001027 if (mask == DMA_BIT_MASK(32)) {
Yang Hongyang28b76792009-04-06 19:01:17 -07001028 mask = DMA_BIT_MASK(30);
Michael Buesch1033b3e2008-04-23 19:13:01 +02001029 fallback = 1;
1030 continue;
1031 }
1032 b43err(dev->wl, "The machine/kernel does not support "
1033 "the required %u-bit DMA mask\n",
1034 (unsigned int)dma_mask_to_engine_type(orig_mask));
1035 return -EOPNOTSUPP;
1036 }
1037 if (fallback) {
1038 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1039 (unsigned int)dma_mask_to_engine_type(orig_mask),
1040 (unsigned int)dma_mask_to_engine_type(mask));
1041 }
1042
1043 return 0;
1044}
1045
Michael Buesche4d6b792007-09-18 15:39:42 -04001046int b43_dma_init(struct b43_wldev *dev)
1047{
1048 struct b43_dma *dma = &dev->dma;
Michael Buesche4d6b792007-09-18 15:39:42 -04001049 int err;
1050 u64 dmamask;
Michael Bueschb79caa62008-02-05 12:50:41 +01001051 enum b43_dmatype type;
Michael Buesche4d6b792007-09-18 15:39:42 -04001052
1053 dmamask = supported_dma_mask(dev);
Michael Buesch5100d5a2008-03-29 21:01:16 +01001054 type = dma_mask_to_engine_type(dmamask);
Michael Buesch1033b3e2008-04-23 19:13:01 +02001055 err = b43_dma_set_mask(dev, dmamask);
1056 if (err)
1057 return err;
Michael Buesche4d6b792007-09-18 15:39:42 -04001058
1059 err = -ENOMEM;
1060 /* setup TX DMA channels. */
Michael Bueschb27faf82008-03-06 16:32:46 +01001061 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1062 if (!dma->tx_ring_AC_BK)
Michael Buesche4d6b792007-09-18 15:39:42 -04001063 goto out;
Michael Buesche4d6b792007-09-18 15:39:42 -04001064
Michael Bueschb27faf82008-03-06 16:32:46 +01001065 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1066 if (!dma->tx_ring_AC_BE)
1067 goto err_destroy_bk;
Michael Buesche4d6b792007-09-18 15:39:42 -04001068
Michael Bueschb27faf82008-03-06 16:32:46 +01001069 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1070 if (!dma->tx_ring_AC_VI)
1071 goto err_destroy_be;
Michael Buesche4d6b792007-09-18 15:39:42 -04001072
Michael Bueschb27faf82008-03-06 16:32:46 +01001073 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1074 if (!dma->tx_ring_AC_VO)
1075 goto err_destroy_vi;
Michael Buesche4d6b792007-09-18 15:39:42 -04001076
Michael Bueschb27faf82008-03-06 16:32:46 +01001077 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1078 if (!dma->tx_ring_mcast)
1079 goto err_destroy_vo;
Michael Buesche4d6b792007-09-18 15:39:42 -04001080
Michael Bueschb27faf82008-03-06 16:32:46 +01001081 /* setup RX DMA channel. */
1082 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1083 if (!dma->rx_ring)
1084 goto err_destroy_mcast;
Michael Buesche4d6b792007-09-18 15:39:42 -04001085
Michael Bueschb27faf82008-03-06 16:32:46 +01001086 /* No support for the TX status DMA ring. */
1087 B43_WARN_ON(dev->dev->id.revision < 5);
Michael Buesche4d6b792007-09-18 15:39:42 -04001088
Michael Bueschb79caa62008-02-05 12:50:41 +01001089 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1090 (unsigned int)type);
Michael Buesche4d6b792007-09-18 15:39:42 -04001091 err = 0;
Michael Bueschb27faf82008-03-06 16:32:46 +01001092out:
Michael Buesche4d6b792007-09-18 15:39:42 -04001093 return err;
1094
Michael Bueschb27faf82008-03-06 16:32:46 +01001095err_destroy_mcast:
1096 destroy_ring(dma, tx_ring_mcast);
1097err_destroy_vo:
1098 destroy_ring(dma, tx_ring_AC_VO);
1099err_destroy_vi:
1100 destroy_ring(dma, tx_ring_AC_VI);
1101err_destroy_be:
1102 destroy_ring(dma, tx_ring_AC_BE);
1103err_destroy_bk:
1104 destroy_ring(dma, tx_ring_AC_BK);
1105 return err;
Michael Buesche4d6b792007-09-18 15:39:42 -04001106}
1107
1108/* Generate a cookie for the TX header. */
1109static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1110{
Michael Bueschb27faf82008-03-06 16:32:46 +01001111 u16 cookie;
Michael Buesche4d6b792007-09-18 15:39:42 -04001112
1113 /* Use the upper 4 bits of the cookie as
1114 * DMA controller ID and store the slot number
1115 * in the lower 12 bits.
1116 * Note that the cookie must never be 0, as this
1117 * is a special value used in RX path.
Michael Buesch280d0e12007-12-26 18:26:17 +01001118 * It can also not be 0xFFFF because that is special
1119 * for multicast frames.
Michael Buesche4d6b792007-09-18 15:39:42 -04001120 */
Michael Bueschb27faf82008-03-06 16:32:46 +01001121 cookie = (((u16)ring->index + 1) << 12);
Michael Buesche4d6b792007-09-18 15:39:42 -04001122 B43_WARN_ON(slot & ~0x0FFF);
Michael Bueschb27faf82008-03-06 16:32:46 +01001123 cookie |= (u16)slot;
Michael Buesche4d6b792007-09-18 15:39:42 -04001124
1125 return cookie;
1126}
1127
1128/* Inspect a cookie and find out to which controller/slot it belongs. */
1129static
1130struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1131{
1132 struct b43_dma *dma = &dev->dma;
1133 struct b43_dmaring *ring = NULL;
1134
1135 switch (cookie & 0xF000) {
Michael Buesch280d0e12007-12-26 18:26:17 +01001136 case 0x1000:
Michael Bueschb27faf82008-03-06 16:32:46 +01001137 ring = dma->tx_ring_AC_BK;
Michael Buesche4d6b792007-09-18 15:39:42 -04001138 break;
Michael Buesch280d0e12007-12-26 18:26:17 +01001139 case 0x2000:
Michael Bueschb27faf82008-03-06 16:32:46 +01001140 ring = dma->tx_ring_AC_BE;
Michael Buesche4d6b792007-09-18 15:39:42 -04001141 break;
Michael Buesch280d0e12007-12-26 18:26:17 +01001142 case 0x3000:
Michael Bueschb27faf82008-03-06 16:32:46 +01001143 ring = dma->tx_ring_AC_VI;
Michael Buesche4d6b792007-09-18 15:39:42 -04001144 break;
Michael Buesch280d0e12007-12-26 18:26:17 +01001145 case 0x4000:
Michael Bueschb27faf82008-03-06 16:32:46 +01001146 ring = dma->tx_ring_AC_VO;
Michael Buesche4d6b792007-09-18 15:39:42 -04001147 break;
Michael Buesch280d0e12007-12-26 18:26:17 +01001148 case 0x5000:
Michael Bueschb27faf82008-03-06 16:32:46 +01001149 ring = dma->tx_ring_mcast;
Michael Buesche4d6b792007-09-18 15:39:42 -04001150 break;
Michael Buesche4d6b792007-09-18 15:39:42 -04001151 }
1152 *slot = (cookie & 0x0FFF);
Michael Buesch07681e22009-11-19 22:24:29 +01001153 if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1154 b43dbg(dev->wl, "TX-status contains "
1155 "invalid cookie: 0x%04X\n", cookie);
1156 return NULL;
1157 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001158
1159 return ring;
1160}
1161
1162static int dma_tx_fragment(struct b43_dmaring *ring,
Michael Bueschf54a5202009-11-06 18:32:44 +01001163 struct sk_buff *skb)
Michael Buesche4d6b792007-09-18 15:39:42 -04001164{
1165 const struct b43_dma_ops *ops = ring->ops;
Johannes Berge039fa42008-05-15 12:55:29 +02001166 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Michael Bueschf54a5202009-11-06 18:32:44 +01001167 struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
Michael Buesche4d6b792007-09-18 15:39:42 -04001168 u8 *header;
Michael Buesch09552cc2008-01-23 21:44:15 +01001169 int slot, old_top_slot, old_used_slots;
Michael Buesche4d6b792007-09-18 15:39:42 -04001170 int err;
1171 struct b43_dmadesc_generic *desc;
1172 struct b43_dmadesc_meta *meta;
1173 struct b43_dmadesc_meta *meta_hdr;
Michael Buesch280d0e12007-12-26 18:26:17 +01001174 u16 cookie;
Michael Buescheb189d8b2008-01-28 14:47:41 -08001175 size_t hdrsize = b43_txhdr_size(ring->dev);
Michael Buesche4d6b792007-09-18 15:39:42 -04001176
Michael Bueschbdceeb22009-02-19 23:45:43 +01001177 /* Important note: If the number of used DMA slots per TX frame
1178 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1179 * the file has to be updated, too!
1180 */
Michael Buesche4d6b792007-09-18 15:39:42 -04001181
Michael Buesch09552cc2008-01-23 21:44:15 +01001182 old_top_slot = ring->current_slot;
1183 old_used_slots = ring->used_slots;
1184
Michael Buesche4d6b792007-09-18 15:39:42 -04001185 /* Get a slot for the header. */
1186 slot = request_slot(ring);
1187 desc = ops->idx2desc(ring, slot, &meta_hdr);
1188 memset(meta_hdr, 0, sizeof(*meta_hdr));
1189
Michael Bueschbdceeb22009-02-19 23:45:43 +01001190 header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
Michael Buesch280d0e12007-12-26 18:26:17 +01001191 cookie = generate_cookie(ring, slot);
Michael Buesch09552cc2008-01-23 21:44:15 +01001192 err = b43_generate_txhdr(ring->dev, header,
gregor kowski035d0242009-08-19 22:35:45 +02001193 skb, info, cookie);
Michael Buesch09552cc2008-01-23 21:44:15 +01001194 if (unlikely(err)) {
1195 ring->current_slot = old_top_slot;
1196 ring->used_slots = old_used_slots;
1197 return err;
1198 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001199
1200 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
Michael Buescheb189d8b2008-01-28 14:47:41 -08001201 hdrsize, 1);
Michael Bueschffa92562008-03-22 22:04:45 +01001202 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
Michael Buesch09552cc2008-01-23 21:44:15 +01001203 ring->current_slot = old_top_slot;
1204 ring->used_slots = old_used_slots;
Michael Buesche4d6b792007-09-18 15:39:42 -04001205 return -EIO;
Michael Buesch09552cc2008-01-23 21:44:15 +01001206 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001207 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
Michael Buescheb189d8b2008-01-28 14:47:41 -08001208 hdrsize, 1, 0, 0);
Michael Buesche4d6b792007-09-18 15:39:42 -04001209
1210 /* Get a slot for the payload. */
1211 slot = request_slot(ring);
1212 desc = ops->idx2desc(ring, slot, &meta);
1213 memset(meta, 0, sizeof(*meta));
1214
Michael Buesche4d6b792007-09-18 15:39:42 -04001215 meta->skb = skb;
1216 meta->is_last_fragment = 1;
Michael Bueschf54a5202009-11-06 18:32:44 +01001217 priv_info->bouncebuffer = NULL;
Michael Buesche4d6b792007-09-18 15:39:42 -04001218
1219 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1220 /* create a bounce buffer in zone_dma on mapping failure. */
Michael Bueschffa92562008-03-22 22:04:45 +01001221 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
Julia Lawalla61aac72010-05-15 23:20:26 +02001222 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1223 GFP_ATOMIC | GFP_DMA);
Michael Bueschf54a5202009-11-06 18:32:44 +01001224 if (!priv_info->bouncebuffer) {
Michael Buesch09552cc2008-01-23 21:44:15 +01001225 ring->current_slot = old_top_slot;
1226 ring->used_slots = old_used_slots;
Michael Buesche4d6b792007-09-18 15:39:42 -04001227 err = -ENOMEM;
1228 goto out_unmap_hdr;
1229 }
1230
Michael Bueschf54a5202009-11-06 18:32:44 +01001231 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
Michael Bueschffa92562008-03-22 22:04:45 +01001232 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
Michael Bueschf54a5202009-11-06 18:32:44 +01001233 kfree(priv_info->bouncebuffer);
1234 priv_info->bouncebuffer = NULL;
Michael Buesch09552cc2008-01-23 21:44:15 +01001235 ring->current_slot = old_top_slot;
1236 ring->used_slots = old_used_slots;
Michael Buesche4d6b792007-09-18 15:39:42 -04001237 err = -EIO;
Michael Bueschf54a5202009-11-06 18:32:44 +01001238 goto out_unmap_hdr;
Michael Buesche4d6b792007-09-18 15:39:42 -04001239 }
1240 }
1241
1242 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1243
Johannes Berge039fa42008-05-15 12:55:29 +02001244 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
Michael Buesch280d0e12007-12-26 18:26:17 +01001245 /* Tell the firmware about the cookie of the last
1246 * mcast frame, so it can clear the more-data bit in it. */
1247 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1248 B43_SHM_SH_MCASTCOOKIE, cookie);
1249 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001250 /* Now transfer the whole frame. */
1251 wmb();
1252 ops->poke_tx(ring, next_slot(ring, slot));
1253 return 0;
1254
Michael Buesch280d0e12007-12-26 18:26:17 +01001255out_unmap_hdr:
Michael Buesche4d6b792007-09-18 15:39:42 -04001256 unmap_descbuffer(ring, meta_hdr->dmaaddr,
Michael Buescheb189d8b2008-01-28 14:47:41 -08001257 hdrsize, 1);
Michael Buesche4d6b792007-09-18 15:39:42 -04001258 return err;
1259}
1260
1261static inline int should_inject_overflow(struct b43_dmaring *ring)
1262{
1263#ifdef CONFIG_B43_DEBUG
1264 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1265 /* Check if we should inject another ringbuffer overflow
1266 * to test handling of this situation in the stack. */
1267 unsigned long next_overflow;
1268
1269 next_overflow = ring->last_injected_overflow + HZ;
1270 if (time_after(jiffies, next_overflow)) {
1271 ring->last_injected_overflow = jiffies;
1272 b43dbg(ring->dev->wl,
1273 "Injecting TX ring overflow on "
1274 "DMA controller %d\n", ring->index);
1275 return 1;
1276 }
1277 }
1278#endif /* CONFIG_B43_DEBUG */
1279 return 0;
1280}
1281
Michael Buesche6f5b932008-03-05 21:18:49 +01001282/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
John Daiker99da1852009-02-24 02:16:42 -08001283static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1284 u8 queue_prio)
Michael Buesche6f5b932008-03-05 21:18:49 +01001285{
1286 struct b43_dmaring *ring;
1287
Michael Buesch403a3a12009-06-08 21:04:57 +02001288 if (dev->qos_enabled) {
Michael Buesche6f5b932008-03-05 21:18:49 +01001289 /* 0 = highest priority */
1290 switch (queue_prio) {
1291 default:
1292 B43_WARN_ON(1);
1293 /* fallthrough */
1294 case 0:
Michael Bueschb27faf82008-03-06 16:32:46 +01001295 ring = dev->dma.tx_ring_AC_VO;
Michael Buesche6f5b932008-03-05 21:18:49 +01001296 break;
1297 case 1:
Michael Bueschb27faf82008-03-06 16:32:46 +01001298 ring = dev->dma.tx_ring_AC_VI;
Michael Buesche6f5b932008-03-05 21:18:49 +01001299 break;
1300 case 2:
Michael Bueschb27faf82008-03-06 16:32:46 +01001301 ring = dev->dma.tx_ring_AC_BE;
Michael Buesche6f5b932008-03-05 21:18:49 +01001302 break;
1303 case 3:
Michael Bueschb27faf82008-03-06 16:32:46 +01001304 ring = dev->dma.tx_ring_AC_BK;
Michael Buesche6f5b932008-03-05 21:18:49 +01001305 break;
1306 }
1307 } else
Michael Bueschb27faf82008-03-06 16:32:46 +01001308 ring = dev->dma.tx_ring_AC_BE;
Michael Buesche6f5b932008-03-05 21:18:49 +01001309
1310 return ring;
1311}
1312
Johannes Berge039fa42008-05-15 12:55:29 +02001313int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
Michael Buesche4d6b792007-09-18 15:39:42 -04001314{
1315 struct b43_dmaring *ring;
Michael Buesch280d0e12007-12-26 18:26:17 +01001316 struct ieee80211_hdr *hdr;
Michael Buesche4d6b792007-09-18 15:39:42 -04001317 int err = 0;
Johannes Berge039fa42008-05-15 12:55:29 +02001318 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Michael Buesche4d6b792007-09-18 15:39:42 -04001319
Michael Buesch280d0e12007-12-26 18:26:17 +01001320 hdr = (struct ieee80211_hdr *)skb->data;
Johannes Berge039fa42008-05-15 12:55:29 +02001321 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
Michael Buesch280d0e12007-12-26 18:26:17 +01001322 /* The multicast ring will be sent after the DTIM */
Michael Bueschb27faf82008-03-06 16:32:46 +01001323 ring = dev->dma.tx_ring_mcast;
Michael Buesch280d0e12007-12-26 18:26:17 +01001324 /* Set the more-data bit. Ucode will clear it on
1325 * the last frame for us. */
1326 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1327 } else {
1328 /* Decide by priority where to put this frame. */
Johannes Berge2530082008-05-17 00:57:14 +02001329 ring = select_ring_by_priority(
1330 dev, skb_get_queue_mapping(skb));
Michael Buesch280d0e12007-12-26 18:26:17 +01001331 }
1332
Michael Buesche4d6b792007-09-18 15:39:42 -04001333 B43_WARN_ON(!ring->tx);
Michael Bueschca2d5592009-02-19 20:17:36 +01001334
Larry Finger18c69512009-07-29 10:54:06 -05001335 if (unlikely(ring->stopped)) {
1336 /* We get here only because of a bug in mac80211.
1337 * Because of a race, one packet may be queued after
1338 * the queue is stopped, thus we got called when we shouldn't.
1339 * For now, just refuse the transmit. */
1340 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1341 b43err(dev->wl, "Packet after queue stopped\n");
1342 err = -ENOSPC;
Michael Buesch637dae32009-09-04 22:55:00 +02001343 goto out;
Larry Finger18c69512009-07-29 10:54:06 -05001344 }
1345
1346 if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1347 /* If we get here, we have a real error with the queue
1348 * full, but queues not stopped. */
1349 b43err(dev->wl, "DMA queue overflow\n");
Michael Buesche4d6b792007-09-18 15:39:42 -04001350 err = -ENOSPC;
Michael Buesch637dae32009-09-04 22:55:00 +02001351 goto out;
Michael Buesche4d6b792007-09-18 15:39:42 -04001352 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001353
Michael Buesche6f5b932008-03-05 21:18:49 +01001354 /* Assign the queue number to the ring (if not already done before)
1355 * so TX status handling can use it. The queue to ring mapping is
1356 * static, so we don't need to store it per frame. */
Johannes Berge2530082008-05-17 00:57:14 +02001357 ring->queue_prio = skb_get_queue_mapping(skb);
Michael Buesche6f5b932008-03-05 21:18:49 +01001358
Michael Bueschf54a5202009-11-06 18:32:44 +01001359 err = dma_tx_fragment(ring, skb);
Michael Buesch09552cc2008-01-23 21:44:15 +01001360 if (unlikely(err == -ENOKEY)) {
1361 /* Drop this packet, as we don't have the encryption key
1362 * anymore and must not transmit it unencrypted. */
1363 dev_kfree_skb_any(skb);
1364 err = 0;
Michael Buesch637dae32009-09-04 22:55:00 +02001365 goto out;
Michael Buesch09552cc2008-01-23 21:44:15 +01001366 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001367 if (unlikely(err)) {
1368 b43err(dev->wl, "DMA tx mapping failure\n");
Michael Buesch637dae32009-09-04 22:55:00 +02001369 goto out;
Michael Buesche4d6b792007-09-18 15:39:42 -04001370 }
Michael Bueschbdceeb22009-02-19 23:45:43 +01001371 if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
Michael Buesche4d6b792007-09-18 15:39:42 -04001372 should_inject_overflow(ring)) {
1373 /* This TX ring is full. */
Johannes Berge2530082008-05-17 00:57:14 +02001374 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
Michael Buesche4d6b792007-09-18 15:39:42 -04001375 ring->stopped = 1;
1376 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1377 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1378 }
1379 }
Michael Buesch637dae32009-09-04 22:55:00 +02001380out:
Michael Buesche4d6b792007-09-18 15:39:42 -04001381
1382 return err;
1383}
1384
1385void b43_dma_handle_txstatus(struct b43_wldev *dev,
1386 const struct b43_txstatus *status)
1387{
1388 const struct b43_dma_ops *ops;
1389 struct b43_dmaring *ring;
1390 struct b43_dmadesc_generic *desc;
1391 struct b43_dmadesc_meta *meta;
Michael Buesch07681e22009-11-19 22:24:29 +01001392 int slot, firstused;
Michael Buesch5100d5a2008-03-29 21:01:16 +01001393 bool frame_succeed;
Michael Buesche4d6b792007-09-18 15:39:42 -04001394
1395 ring = parse_cookie(dev, status->cookie, &slot);
1396 if (unlikely(!ring))
1397 return;
Michael Buesche4d6b792007-09-18 15:39:42 -04001398 B43_WARN_ON(!ring->tx);
Michael Buesch07681e22009-11-19 22:24:29 +01001399
1400 /* Sanity check: TX packets are processed in-order on one ring.
1401 * Check if the slot deduced from the cookie really is the first
1402 * used slot. */
1403 firstused = ring->current_slot - ring->used_slots + 1;
1404 if (firstused < 0)
1405 firstused = ring->nr_slots + firstused;
1406 if (unlikely(slot != firstused)) {
1407 /* This possibly is a firmware bug and will result in
1408 * malfunction, memory leaks and/or stall of DMA functionality. */
1409 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1410 "Expected %d, but got %d\n",
1411 ring->index, firstused, slot);
1412 return;
1413 }
1414
Michael Buesche4d6b792007-09-18 15:39:42 -04001415 ops = ring->ops;
1416 while (1) {
Michael Buesch07681e22009-11-19 22:24:29 +01001417 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
Michael Buesche4d6b792007-09-18 15:39:42 -04001418 desc = ops->idx2desc(ring, slot, &meta);
1419
Michael Buesch07681e22009-11-19 22:24:29 +01001420 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1421 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1422 "on ring %d\n",
1423 slot, firstused, ring->index);
1424 break;
1425 }
Michael Bueschf54a5202009-11-06 18:32:44 +01001426 if (meta->skb) {
1427 struct b43_private_tx_info *priv_info =
1428 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1429
1430 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1431 kfree(priv_info->bouncebuffer);
1432 priv_info->bouncebuffer = NULL;
1433 } else {
Michael Buesche4d6b792007-09-18 15:39:42 -04001434 unmap_descbuffer(ring, meta->dmaaddr,
Michael Buescheb189d8b2008-01-28 14:47:41 -08001435 b43_txhdr_size(dev), 1);
Michael Bueschf54a5202009-11-06 18:32:44 +01001436 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001437
1438 if (meta->is_last_fragment) {
Johannes Berge039fa42008-05-15 12:55:29 +02001439 struct ieee80211_tx_info *info;
1440
Michael Buesch07681e22009-11-19 22:24:29 +01001441 if (unlikely(!meta->skb)) {
1442 /* This is a scatter-gather fragment of a frame, so
1443 * the skb pointer must not be NULL. */
1444 b43dbg(dev->wl, "TX status unexpected NULL skb "
1445 "at slot %d (first=%d) on ring %d\n",
1446 slot, firstused, ring->index);
1447 break;
1448 }
Johannes Berge039fa42008-05-15 12:55:29 +02001449
1450 info = IEEE80211_SKB_CB(meta->skb);
1451
Johannes Berge039fa42008-05-15 12:55:29 +02001452 /*
1453 * Call back to inform the ieee80211 subsystem about
1454 * the status of the transmission.
Michael Buesche4d6b792007-09-18 15:39:42 -04001455 */
Johannes Berge6a98542008-10-21 12:40:02 +02001456 frame_succeed = b43_fill_txstatus_report(dev, info, status);
Michael Buesch5100d5a2008-03-29 21:01:16 +01001457#ifdef CONFIG_B43_DEBUG
1458 if (frame_succeed)
1459 ring->nr_succeed_tx_packets++;
1460 else
1461 ring->nr_failed_tx_packets++;
1462 ring->nr_total_packet_tries += status->frame_count;
1463#endif /* DEBUG */
Michael Bueschce6c4a12009-09-10 20:22:02 +02001464 ieee80211_tx_status(dev->wl->hw, meta->skb);
Johannes Berge039fa42008-05-15 12:55:29 +02001465
Michael Buesch07681e22009-11-19 22:24:29 +01001466 /* skb will be freed by ieee80211_tx_status().
1467 * Poison our pointer. */
1468 meta->skb = B43_DMA_PTR_POISON;
Michael Buesche4d6b792007-09-18 15:39:42 -04001469 } else {
1470 /* No need to call free_descriptor_buffer here, as
1471 * this is only the txhdr, which is not allocated.
1472 */
Michael Buesch07681e22009-11-19 22:24:29 +01001473 if (unlikely(meta->skb)) {
1474 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1475 "at slot %d (first=%d) on ring %d\n",
1476 slot, firstused, ring->index);
1477 break;
1478 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001479 }
1480
1481 /* Everything unmapped and free'd. So it's not used anymore. */
1482 ring->used_slots--;
1483
Michael Buesch07681e22009-11-19 22:24:29 +01001484 if (meta->is_last_fragment) {
1485 /* This is the last scatter-gather
1486 * fragment of the frame. We are done. */
Michael Buesche4d6b792007-09-18 15:39:42 -04001487 break;
Michael Buesch07681e22009-11-19 22:24:29 +01001488 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001489 slot = next_slot(ring, slot);
1490 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001491 if (ring->stopped) {
Michael Bueschbdceeb22009-02-19 23:45:43 +01001492 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
Michael Buesche6f5b932008-03-05 21:18:49 +01001493 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
Michael Buesche4d6b792007-09-18 15:39:42 -04001494 ring->stopped = 0;
1495 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1496 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1497 }
1498 }
Michael Buesche4d6b792007-09-18 15:39:42 -04001499}
1500
Michael Buesche4d6b792007-09-18 15:39:42 -04001501static void dma_rx(struct b43_dmaring *ring, int *slot)
1502{
1503 const struct b43_dma_ops *ops = ring->ops;
1504 struct b43_dmadesc_generic *desc;
1505 struct b43_dmadesc_meta *meta;
1506 struct b43_rxhdr_fw4 *rxhdr;
1507 struct sk_buff *skb;
1508 u16 len;
1509 int err;
1510 dma_addr_t dmaaddr;
1511
1512 desc = ops->idx2desc(ring, *slot, &meta);
1513
1514 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1515 skb = meta->skb;
1516
Michael Buesche4d6b792007-09-18 15:39:42 -04001517 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1518 len = le16_to_cpu(rxhdr->frame_len);
1519 if (len == 0) {
1520 int i = 0;
1521
1522 do {
1523 udelay(2);
1524 barrier();
1525 len = le16_to_cpu(rxhdr->frame_len);
1526 } while (len == 0 && i++ < 5);
1527 if (unlikely(len == 0)) {
Michael Bueschcf686362009-03-28 00:41:25 +01001528 dmaaddr = meta->dmaaddr;
1529 goto drop_recycle_buffer;
Michael Buesche4d6b792007-09-18 15:39:42 -04001530 }
1531 }
Michael Bueschec9a1d82009-03-27 22:51:58 +01001532 if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1533 /* Something went wrong with the DMA.
1534 * The device did not touch the buffer and did not overwrite the poison. */
1535 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
Michael Bueschcf686362009-03-28 00:41:25 +01001536 dmaaddr = meta->dmaaddr;
1537 goto drop_recycle_buffer;
Michael Bueschec9a1d82009-03-27 22:51:58 +01001538 }
John W. Linvillec85ce652011-03-30 14:02:46 -04001539 if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
Michael Buesche4d6b792007-09-18 15:39:42 -04001540 /* The data did not fit into one descriptor buffer
1541 * and is split over multiple buffers.
1542 * This should never happen, as we try to allocate buffers
1543 * big enough. So simply ignore this packet.
1544 */
1545 int cnt = 0;
1546 s32 tmp = len;
1547
1548 while (1) {
1549 desc = ops->idx2desc(ring, *slot, &meta);
1550 /* recycle the descriptor buffer. */
Michael Bueschcf686362009-03-28 00:41:25 +01001551 b43_poison_rx_buffer(ring, meta->skb);
Michael Buesche4d6b792007-09-18 15:39:42 -04001552 sync_descbuffer_for_device(ring, meta->dmaaddr,
1553 ring->rx_buffersize);
1554 *slot = next_slot(ring, *slot);
1555 cnt++;
1556 tmp -= ring->rx_buffersize;
1557 if (tmp <= 0)
1558 break;
1559 }
1560 b43err(ring->dev->wl, "DMA RX buffer too small "
1561 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1562 len, ring->rx_buffersize, cnt);
1563 goto drop;
1564 }
1565
1566 dmaaddr = meta->dmaaddr;
1567 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1568 if (unlikely(err)) {
1569 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
Michael Bueschcf686362009-03-28 00:41:25 +01001570 goto drop_recycle_buffer;
Michael Buesche4d6b792007-09-18 15:39:42 -04001571 }
1572
1573 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1574 skb_put(skb, len + ring->frameoffset);
1575 skb_pull(skb, ring->frameoffset);
1576
1577 b43_rx(ring->dev, skb, rxhdr);
Michael Bueschb27faf82008-03-06 16:32:46 +01001578drop:
Michael Buesche4d6b792007-09-18 15:39:42 -04001579 return;
Michael Bueschcf686362009-03-28 00:41:25 +01001580
1581drop_recycle_buffer:
1582 /* Poison and recycle the RX buffer. */
1583 b43_poison_rx_buffer(ring, skb);
1584 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
Michael Buesche4d6b792007-09-18 15:39:42 -04001585}
1586
1587void b43_dma_rx(struct b43_dmaring *ring)
1588{
1589 const struct b43_dma_ops *ops = ring->ops;
1590 int slot, current_slot;
1591 int used_slots = 0;
1592
1593 B43_WARN_ON(ring->tx);
1594 current_slot = ops->get_current_rxslot(ring);
1595 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1596
1597 slot = ring->current_slot;
1598 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1599 dma_rx(ring, &slot);
1600 update_max_used_slots(ring, ++used_slots);
1601 }
1602 ops->set_current_rxslot(ring, slot);
1603 ring->current_slot = slot;
1604}
1605
1606static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1607{
Michael Buesche4d6b792007-09-18 15:39:42 -04001608 B43_WARN_ON(!ring->tx);
1609 ring->ops->tx_suspend(ring);
Michael Buesche4d6b792007-09-18 15:39:42 -04001610}
1611
1612static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1613{
Michael Buesche4d6b792007-09-18 15:39:42 -04001614 B43_WARN_ON(!ring->tx);
1615 ring->ops->tx_resume(ring);
Michael Buesche4d6b792007-09-18 15:39:42 -04001616}
1617
1618void b43_dma_tx_suspend(struct b43_wldev *dev)
1619{
1620 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
Michael Bueschb27faf82008-03-06 16:32:46 +01001621 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1622 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1623 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1624 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1625 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
Michael Buesche4d6b792007-09-18 15:39:42 -04001626}
1627
1628void b43_dma_tx_resume(struct b43_wldev *dev)
1629{
Michael Bueschb27faf82008-03-06 16:32:46 +01001630 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1631 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1632 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1633 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1634 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
Michael Buesche4d6b792007-09-18 15:39:42 -04001635 b43_power_saving_ctl_bits(dev, 0);
1636}
Michael Buesch5100d5a2008-03-29 21:01:16 +01001637
Michael Buesch5100d5a2008-03-29 21:01:16 +01001638static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1639 u16 mmio_base, bool enable)
1640{
1641 u32 ctl;
1642
1643 if (type == B43_DMA_64BIT) {
1644 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1645 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1646 if (enable)
1647 ctl |= B43_DMA64_RXDIRECTFIFO;
1648 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1649 } else {
1650 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1651 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1652 if (enable)
1653 ctl |= B43_DMA32_RXDIRECTFIFO;
1654 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1655 }
1656}
1657
1658/* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1659 * This is called from PIO code, so DMA structures are not available. */
1660void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1661 unsigned int engine_index, bool enable)
1662{
1663 enum b43_dmatype type;
1664 u16 mmio_base;
1665
1666 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1667
1668 mmio_base = b43_dmacontroller_base(type, engine_index);
1669 direct_fifo_rx(dev, type, mmio_base, enable);
1670}