Oscar Mateo | b20385f | 2014-07-24 17:04:10 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Ben Widawsky <ben@bwidawsk.net> |
| 25 | * Michel Thierry <michel.thierry@intel.com> |
| 26 | * Thomas Daniel <thomas.daniel@intel.com> |
| 27 | * Oscar Mateo <oscar.mateo@intel.com> |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | /* |
| 32 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
| 33 | * These expanded contexts enable a number of new abilities, especially |
| 34 | * "Execlists" (also implemented in this file). |
| 35 | * |
| 36 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
| 37 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). |
| 38 | */ |
| 39 | |
| 40 | #include <drm/drmP.h> |
| 41 | #include <drm/i915_drm.h> |
| 42 | #include "i915_drv.h" |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 43 | |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 44 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
| 45 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) |
| 46 | |
| 47 | #define GEN8_LR_CONTEXT_ALIGN 4096 |
| 48 | |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 49 | #define RING_ELSP(ring) ((ring)->mmio_base+0x230) |
| 50 | #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) |
| 51 | |
| 52 | #define CTX_LRI_HEADER_0 0x01 |
| 53 | #define CTX_CONTEXT_CONTROL 0x02 |
| 54 | #define CTX_RING_HEAD 0x04 |
| 55 | #define CTX_RING_TAIL 0x06 |
| 56 | #define CTX_RING_BUFFER_START 0x08 |
| 57 | #define CTX_RING_BUFFER_CONTROL 0x0a |
| 58 | #define CTX_BB_HEAD_U 0x0c |
| 59 | #define CTX_BB_HEAD_L 0x0e |
| 60 | #define CTX_BB_STATE 0x10 |
| 61 | #define CTX_SECOND_BB_HEAD_U 0x12 |
| 62 | #define CTX_SECOND_BB_HEAD_L 0x14 |
| 63 | #define CTX_SECOND_BB_STATE 0x16 |
| 64 | #define CTX_BB_PER_CTX_PTR 0x18 |
| 65 | #define CTX_RCS_INDIRECT_CTX 0x1a |
| 66 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c |
| 67 | #define CTX_LRI_HEADER_1 0x21 |
| 68 | #define CTX_CTX_TIMESTAMP 0x22 |
| 69 | #define CTX_PDP3_UDW 0x24 |
| 70 | #define CTX_PDP3_LDW 0x26 |
| 71 | #define CTX_PDP2_UDW 0x28 |
| 72 | #define CTX_PDP2_LDW 0x2a |
| 73 | #define CTX_PDP1_UDW 0x2c |
| 74 | #define CTX_PDP1_LDW 0x2e |
| 75 | #define CTX_PDP0_UDW 0x30 |
| 76 | #define CTX_PDP0_LDW 0x32 |
| 77 | #define CTX_LRI_HEADER_2 0x41 |
| 78 | #define CTX_R_PWR_CLK_STATE 0x42 |
| 79 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 |
| 80 | |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 81 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
| 82 | { |
Daniel Vetter | bd84b1e | 2014-08-11 15:57:57 +0200 | [diff] [blame] | 83 | WARN_ON(i915.enable_ppgtt == -1); |
| 84 | |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 85 | if (enable_execlists == 0) |
| 86 | return 0; |
| 87 | |
| 88 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev)) |
| 89 | return 1; |
| 90 | |
| 91 | return 0; |
| 92 | } |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 93 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 94 | int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
| 95 | struct intel_engine_cs *ring, |
| 96 | struct intel_context *ctx, |
| 97 | struct drm_i915_gem_execbuffer2 *args, |
| 98 | struct list_head *vmas, |
| 99 | struct drm_i915_gem_object *batch_obj, |
| 100 | u64 exec_start, u32 flags) |
| 101 | { |
| 102 | /* TODO */ |
| 103 | return 0; |
| 104 | } |
| 105 | |
| 106 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
| 107 | { |
Oscar Mateo | 9832b9d | 2014-07-24 17:04:30 +0100 | [diff] [blame^] | 108 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 109 | int ret; |
| 110 | |
| 111 | if (!intel_ring_initialized(ring)) |
| 112 | return; |
| 113 | |
| 114 | ret = intel_ring_idle(ring); |
| 115 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) |
| 116 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 117 | ring->name, ret); |
| 118 | |
| 119 | /* TODO: Is this correct with Execlists enabled? */ |
| 120 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
| 121 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
| 122 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); |
| 123 | return; |
| 124 | } |
| 125 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 126 | } |
| 127 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 128 | void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) |
| 129 | { |
| 130 | intel_logical_ring_advance(ringbuf); |
| 131 | |
| 132 | if (intel_ring_stopped(ringbuf->ring)) |
| 133 | return; |
| 134 | |
| 135 | /* TODO: how to submit a context to the ELSP is not here yet */ |
| 136 | } |
| 137 | |
| 138 | static int logical_ring_alloc_seqno(struct intel_engine_cs *ring) |
| 139 | { |
| 140 | if (ring->outstanding_lazy_seqno) |
| 141 | return 0; |
| 142 | |
| 143 | if (ring->preallocated_lazy_request == NULL) { |
| 144 | struct drm_i915_gem_request *request; |
| 145 | |
| 146 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 147 | if (request == NULL) |
| 148 | return -ENOMEM; |
| 149 | |
| 150 | ring->preallocated_lazy_request = request; |
| 151 | } |
| 152 | |
| 153 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
| 154 | } |
| 155 | |
| 156 | static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, |
| 157 | int bytes) |
| 158 | { |
| 159 | struct intel_engine_cs *ring = ringbuf->ring; |
| 160 | struct drm_i915_gem_request *request; |
| 161 | u32 seqno = 0; |
| 162 | int ret; |
| 163 | |
| 164 | if (ringbuf->last_retired_head != -1) { |
| 165 | ringbuf->head = ringbuf->last_retired_head; |
| 166 | ringbuf->last_retired_head = -1; |
| 167 | |
| 168 | ringbuf->space = intel_ring_space(ringbuf); |
| 169 | if (ringbuf->space >= bytes) |
| 170 | return 0; |
| 171 | } |
| 172 | |
| 173 | list_for_each_entry(request, &ring->request_list, list) { |
| 174 | if (__intel_ring_space(request->tail, ringbuf->tail, |
| 175 | ringbuf->size) >= bytes) { |
| 176 | seqno = request->seqno; |
| 177 | break; |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | if (seqno == 0) |
| 182 | return -ENOSPC; |
| 183 | |
| 184 | ret = i915_wait_seqno(ring, seqno); |
| 185 | if (ret) |
| 186 | return ret; |
| 187 | |
| 188 | /* TODO: make sure we update the right ringbuffer's last_retired_head |
| 189 | * when retiring requests */ |
| 190 | i915_gem_retire_requests_ring(ring); |
| 191 | ringbuf->head = ringbuf->last_retired_head; |
| 192 | ringbuf->last_retired_head = -1; |
| 193 | |
| 194 | ringbuf->space = intel_ring_space(ringbuf); |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, |
| 199 | int bytes) |
| 200 | { |
| 201 | struct intel_engine_cs *ring = ringbuf->ring; |
| 202 | struct drm_device *dev = ring->dev; |
| 203 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 204 | unsigned long end; |
| 205 | int ret; |
| 206 | |
| 207 | ret = logical_ring_wait_request(ringbuf, bytes); |
| 208 | if (ret != -ENOSPC) |
| 209 | return ret; |
| 210 | |
| 211 | /* Force the context submission in case we have been skipping it */ |
| 212 | intel_logical_ring_advance_and_submit(ringbuf); |
| 213 | |
| 214 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 215 | * leaving it early runs the risk of corrupting GEM state (due |
| 216 | * to running on almost untested codepaths). But on resume |
| 217 | * timers don't work yet, so prevent a complete hang in that |
| 218 | * case by choosing an insanely large timeout. */ |
| 219 | end = jiffies + 60 * HZ; |
| 220 | |
| 221 | do { |
| 222 | ringbuf->head = I915_READ_HEAD(ring); |
| 223 | ringbuf->space = intel_ring_space(ringbuf); |
| 224 | if (ringbuf->space >= bytes) { |
| 225 | ret = 0; |
| 226 | break; |
| 227 | } |
| 228 | |
| 229 | msleep(1); |
| 230 | |
| 231 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
| 232 | ret = -ERESTARTSYS; |
| 233 | break; |
| 234 | } |
| 235 | |
| 236 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 237 | dev_priv->mm.interruptible); |
| 238 | if (ret) |
| 239 | break; |
| 240 | |
| 241 | if (time_after(jiffies, end)) { |
| 242 | ret = -EBUSY; |
| 243 | break; |
| 244 | } |
| 245 | } while (1); |
| 246 | |
| 247 | return ret; |
| 248 | } |
| 249 | |
| 250 | static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) |
| 251 | { |
| 252 | uint32_t __iomem *virt; |
| 253 | int rem = ringbuf->size - ringbuf->tail; |
| 254 | |
| 255 | if (ringbuf->space < rem) { |
| 256 | int ret = logical_ring_wait_for_space(ringbuf, rem); |
| 257 | |
| 258 | if (ret) |
| 259 | return ret; |
| 260 | } |
| 261 | |
| 262 | virt = ringbuf->virtual_start + ringbuf->tail; |
| 263 | rem /= 4; |
| 264 | while (rem--) |
| 265 | iowrite32(MI_NOOP, virt++); |
| 266 | |
| 267 | ringbuf->tail = 0; |
| 268 | ringbuf->space = intel_ring_space(ringbuf); |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) |
| 274 | { |
| 275 | int ret; |
| 276 | |
| 277 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
| 278 | ret = logical_ring_wrap_buffer(ringbuf); |
| 279 | if (unlikely(ret)) |
| 280 | return ret; |
| 281 | } |
| 282 | |
| 283 | if (unlikely(ringbuf->space < bytes)) { |
| 284 | ret = logical_ring_wait_for_space(ringbuf, bytes); |
| 285 | if (unlikely(ret)) |
| 286 | return ret; |
| 287 | } |
| 288 | |
| 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) |
| 293 | { |
| 294 | struct intel_engine_cs *ring = ringbuf->ring; |
| 295 | struct drm_device *dev = ring->dev; |
| 296 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 297 | int ret; |
| 298 | |
| 299 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 300 | dev_priv->mm.interruptible); |
| 301 | if (ret) |
| 302 | return ret; |
| 303 | |
| 304 | ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); |
| 305 | if (ret) |
| 306 | return ret; |
| 307 | |
| 308 | /* Preallocate the olr before touching the ring */ |
| 309 | ret = logical_ring_alloc_seqno(ring); |
| 310 | if (ret) |
| 311 | return ret; |
| 312 | |
| 313 | ringbuf->space -= num_dwords * sizeof(uint32_t); |
| 314 | return 0; |
| 315 | } |
| 316 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 317 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
| 318 | { |
| 319 | struct drm_device *dev = ring->dev; |
| 320 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 321 | |
| 322 | I915_WRITE(RING_MODE_GEN7(ring), |
| 323 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
| 324 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
| 325 | POSTING_READ(RING_MODE_GEN7(ring)); |
| 326 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
| 327 | |
| 328 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 329 | |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | static int gen8_init_render_ring(struct intel_engine_cs *ring) |
| 334 | { |
| 335 | struct drm_device *dev = ring->dev; |
| 336 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 337 | int ret; |
| 338 | |
| 339 | ret = gen8_init_common_ring(ring); |
| 340 | if (ret) |
| 341 | return ret; |
| 342 | |
| 343 | /* We need to disable the AsyncFlip performance optimisations in order |
| 344 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 345 | * programmed to '1' on all products. |
| 346 | * |
| 347 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
| 348 | */ |
| 349 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 350 | |
| 351 | ret = intel_init_pipe_control(ring); |
| 352 | if (ret) |
| 353 | return ret; |
| 354 | |
| 355 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
| 356 | |
| 357 | return ret; |
| 358 | } |
| 359 | |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 360 | static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
| 361 | u32 invalidate_domains, |
| 362 | u32 unused) |
| 363 | { |
| 364 | struct intel_engine_cs *ring = ringbuf->ring; |
| 365 | struct drm_device *dev = ring->dev; |
| 366 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 367 | uint32_t cmd; |
| 368 | int ret; |
| 369 | |
| 370 | ret = intel_logical_ring_begin(ringbuf, 4); |
| 371 | if (ret) |
| 372 | return ret; |
| 373 | |
| 374 | cmd = MI_FLUSH_DW + 1; |
| 375 | |
| 376 | if (ring == &dev_priv->ring[VCS]) { |
| 377 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
| 378 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 379 | MI_FLUSH_DW_STORE_INDEX | |
| 380 | MI_FLUSH_DW_OP_STOREDW; |
| 381 | } else { |
| 382 | if (invalidate_domains & I915_GEM_DOMAIN_RENDER) |
| 383 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
| 384 | MI_FLUSH_DW_OP_STOREDW; |
| 385 | } |
| 386 | |
| 387 | intel_logical_ring_emit(ringbuf, cmd); |
| 388 | intel_logical_ring_emit(ringbuf, |
| 389 | I915_GEM_HWS_SCRATCH_ADDR | |
| 390 | MI_FLUSH_DW_USE_GTT); |
| 391 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ |
| 392 | intel_logical_ring_emit(ringbuf, 0); /* value */ |
| 393 | intel_logical_ring_advance(ringbuf); |
| 394 | |
| 395 | return 0; |
| 396 | } |
| 397 | |
| 398 | static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, |
| 399 | u32 invalidate_domains, |
| 400 | u32 flush_domains) |
| 401 | { |
| 402 | struct intel_engine_cs *ring = ringbuf->ring; |
| 403 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
| 404 | u32 flags = 0; |
| 405 | int ret; |
| 406 | |
| 407 | flags |= PIPE_CONTROL_CS_STALL; |
| 408 | |
| 409 | if (flush_domains) { |
| 410 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 411 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 412 | } |
| 413 | |
| 414 | if (invalidate_domains) { |
| 415 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 416 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 417 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 418 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 419 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 420 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 421 | flags |= PIPE_CONTROL_QW_WRITE; |
| 422 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
| 423 | } |
| 424 | |
| 425 | ret = intel_logical_ring_begin(ringbuf, 6); |
| 426 | if (ret) |
| 427 | return ret; |
| 428 | |
| 429 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
| 430 | intel_logical_ring_emit(ringbuf, flags); |
| 431 | intel_logical_ring_emit(ringbuf, scratch_addr); |
| 432 | intel_logical_ring_emit(ringbuf, 0); |
| 433 | intel_logical_ring_emit(ringbuf, 0); |
| 434 | intel_logical_ring_emit(ringbuf, 0); |
| 435 | intel_logical_ring_advance(ringbuf); |
| 436 | |
| 437 | return 0; |
| 438 | } |
| 439 | |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 440 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
| 441 | { |
| 442 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 443 | } |
| 444 | |
| 445 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
| 446 | { |
| 447 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 448 | } |
| 449 | |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 450 | static int gen8_emit_request(struct intel_ringbuffer *ringbuf) |
| 451 | { |
| 452 | struct intel_engine_cs *ring = ringbuf->ring; |
| 453 | u32 cmd; |
| 454 | int ret; |
| 455 | |
| 456 | ret = intel_logical_ring_begin(ringbuf, 6); |
| 457 | if (ret) |
| 458 | return ret; |
| 459 | |
| 460 | cmd = MI_STORE_DWORD_IMM_GEN8; |
| 461 | cmd |= MI_GLOBAL_GTT; |
| 462 | |
| 463 | intel_logical_ring_emit(ringbuf, cmd); |
| 464 | intel_logical_ring_emit(ringbuf, |
| 465 | (ring->status_page.gfx_addr + |
| 466 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); |
| 467 | intel_logical_ring_emit(ringbuf, 0); |
| 468 | intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno); |
| 469 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
| 470 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 471 | intel_logical_ring_advance_and_submit(ringbuf); |
| 472 | |
| 473 | return 0; |
| 474 | } |
| 475 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 476 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
| 477 | { |
Oscar Mateo | 9832b9d | 2014-07-24 17:04:30 +0100 | [diff] [blame^] | 478 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 479 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 480 | if (!intel_ring_initialized(ring)) |
| 481 | return; |
| 482 | |
Oscar Mateo | 9832b9d | 2014-07-24 17:04:30 +0100 | [diff] [blame^] | 483 | intel_logical_ring_stop(ring); |
| 484 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 485 | ring->preallocated_lazy_request = NULL; |
| 486 | ring->outstanding_lazy_seqno = 0; |
| 487 | |
| 488 | if (ring->cleanup) |
| 489 | ring->cleanup(ring); |
| 490 | |
| 491 | i915_cmd_parser_fini_ring(ring); |
| 492 | |
| 493 | if (ring->status_page.obj) { |
| 494 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); |
| 495 | ring->status_page.obj = NULL; |
| 496 | } |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 497 | } |
| 498 | |
| 499 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) |
| 500 | { |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 501 | int ret; |
| 502 | struct intel_context *dctx = ring->default_context; |
| 503 | struct drm_i915_gem_object *dctx_obj; |
| 504 | |
| 505 | /* Intentionally left blank. */ |
| 506 | ring->buffer = NULL; |
| 507 | |
| 508 | ring->dev = dev; |
| 509 | INIT_LIST_HEAD(&ring->active_list); |
| 510 | INIT_LIST_HEAD(&ring->request_list); |
| 511 | init_waitqueue_head(&ring->irq_queue); |
| 512 | |
| 513 | ret = intel_lr_context_deferred_create(dctx, ring); |
| 514 | if (ret) |
| 515 | return ret; |
| 516 | |
| 517 | /* The status page is offset 0 from the context object in LRCs. */ |
| 518 | dctx_obj = dctx->engine[ring->id].state; |
| 519 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj); |
| 520 | ring->status_page.page_addr = kmap(sg_page(dctx_obj->pages->sgl)); |
| 521 | if (ring->status_page.page_addr == NULL) |
| 522 | return -ENOMEM; |
| 523 | ring->status_page.obj = dctx_obj; |
| 524 | |
| 525 | ret = i915_cmd_parser_init_ring(ring); |
| 526 | if (ret) |
| 527 | return ret; |
| 528 | |
| 529 | if (ring->init) { |
| 530 | ret = ring->init(ring); |
| 531 | if (ret) |
| 532 | return ret; |
| 533 | } |
| 534 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | static int logical_render_ring_init(struct drm_device *dev) |
| 539 | { |
| 540 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 541 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
| 542 | |
| 543 | ring->name = "render ring"; |
| 544 | ring->id = RCS; |
| 545 | ring->mmio_base = RENDER_RING_BASE; |
| 546 | ring->irq_enable_mask = |
| 547 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; |
| 548 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 549 | ring->init = gen8_init_render_ring; |
| 550 | ring->cleanup = intel_fini_pipe_control; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 551 | ring->get_seqno = gen8_get_seqno; |
| 552 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 553 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 554 | ring->emit_flush = gen8_emit_flush_render; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 555 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 556 | return logical_ring_init(dev, ring); |
| 557 | } |
| 558 | |
| 559 | static int logical_bsd_ring_init(struct drm_device *dev) |
| 560 | { |
| 561 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 562 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
| 563 | |
| 564 | ring->name = "bsd ring"; |
| 565 | ring->id = VCS; |
| 566 | ring->mmio_base = GEN6_BSD_RING_BASE; |
| 567 | ring->irq_enable_mask = |
| 568 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
| 569 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 570 | ring->init = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 571 | ring->get_seqno = gen8_get_seqno; |
| 572 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 573 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 574 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 575 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 576 | return logical_ring_init(dev, ring); |
| 577 | } |
| 578 | |
| 579 | static int logical_bsd2_ring_init(struct drm_device *dev) |
| 580 | { |
| 581 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 582 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
| 583 | |
| 584 | ring->name = "bds2 ring"; |
| 585 | ring->id = VCS2; |
| 586 | ring->mmio_base = GEN8_BSD2_RING_BASE; |
| 587 | ring->irq_enable_mask = |
| 588 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
| 589 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 590 | ring->init = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 591 | ring->get_seqno = gen8_get_seqno; |
| 592 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 593 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 594 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 595 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 596 | return logical_ring_init(dev, ring); |
| 597 | } |
| 598 | |
| 599 | static int logical_blt_ring_init(struct drm_device *dev) |
| 600 | { |
| 601 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 602 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
| 603 | |
| 604 | ring->name = "blitter ring"; |
| 605 | ring->id = BCS; |
| 606 | ring->mmio_base = BLT_RING_BASE; |
| 607 | ring->irq_enable_mask = |
| 608 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
| 609 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 610 | ring->init = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 611 | ring->get_seqno = gen8_get_seqno; |
| 612 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 613 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 614 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 615 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 616 | return logical_ring_init(dev, ring); |
| 617 | } |
| 618 | |
| 619 | static int logical_vebox_ring_init(struct drm_device *dev) |
| 620 | { |
| 621 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 622 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
| 623 | |
| 624 | ring->name = "video enhancement ring"; |
| 625 | ring->id = VECS; |
| 626 | ring->mmio_base = VEBOX_RING_BASE; |
| 627 | ring->irq_enable_mask = |
| 628 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
| 629 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 630 | ring->init = gen8_init_common_ring; |
Oscar Mateo | e94e37a | 2014-07-24 17:04:25 +0100 | [diff] [blame] | 631 | ring->get_seqno = gen8_get_seqno; |
| 632 | ring->set_seqno = gen8_set_seqno; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 633 | ring->emit_request = gen8_emit_request; |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 634 | ring->emit_flush = gen8_emit_flush; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 635 | |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 636 | return logical_ring_init(dev, ring); |
| 637 | } |
| 638 | |
| 639 | int intel_logical_rings_init(struct drm_device *dev) |
| 640 | { |
| 641 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 642 | int ret; |
| 643 | |
| 644 | ret = logical_render_ring_init(dev); |
| 645 | if (ret) |
| 646 | return ret; |
| 647 | |
| 648 | if (HAS_BSD(dev)) { |
| 649 | ret = logical_bsd_ring_init(dev); |
| 650 | if (ret) |
| 651 | goto cleanup_render_ring; |
| 652 | } |
| 653 | |
| 654 | if (HAS_BLT(dev)) { |
| 655 | ret = logical_blt_ring_init(dev); |
| 656 | if (ret) |
| 657 | goto cleanup_bsd_ring; |
| 658 | } |
| 659 | |
| 660 | if (HAS_VEBOX(dev)) { |
| 661 | ret = logical_vebox_ring_init(dev); |
| 662 | if (ret) |
| 663 | goto cleanup_blt_ring; |
| 664 | } |
| 665 | |
| 666 | if (HAS_BSD2(dev)) { |
| 667 | ret = logical_bsd2_ring_init(dev); |
| 668 | if (ret) |
| 669 | goto cleanup_vebox_ring; |
| 670 | } |
| 671 | |
| 672 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 673 | if (ret) |
| 674 | goto cleanup_bsd2_ring; |
| 675 | |
| 676 | return 0; |
| 677 | |
| 678 | cleanup_bsd2_ring: |
| 679 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); |
| 680 | cleanup_vebox_ring: |
| 681 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); |
| 682 | cleanup_blt_ring: |
| 683 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); |
| 684 | cleanup_bsd_ring: |
| 685 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); |
| 686 | cleanup_render_ring: |
| 687 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); |
| 688 | |
| 689 | return ret; |
| 690 | } |
| 691 | |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 692 | static int |
| 693 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, |
| 694 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) |
| 695 | { |
| 696 | struct drm_i915_gem_object *ring_obj = ringbuf->obj; |
| 697 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); |
| 698 | struct page *page; |
| 699 | uint32_t *reg_state; |
| 700 | int ret; |
| 701 | |
| 702 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
| 703 | if (ret) { |
| 704 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); |
| 705 | return ret; |
| 706 | } |
| 707 | |
| 708 | ret = i915_gem_object_get_pages(ctx_obj); |
| 709 | if (ret) { |
| 710 | DRM_DEBUG_DRIVER("Could not get object pages\n"); |
| 711 | return ret; |
| 712 | } |
| 713 | |
| 714 | i915_gem_object_pin_pages(ctx_obj); |
| 715 | |
| 716 | /* The second page of the context object contains some fields which must |
| 717 | * be set up prior to the first execution. */ |
| 718 | page = i915_gem_object_get_page(ctx_obj, 1); |
| 719 | reg_state = kmap_atomic(page); |
| 720 | |
| 721 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM |
| 722 | * commands followed by (reg, value) pairs. The values we are setting here are |
| 723 | * only for the first context restore: on a subsequent save, the GPU will |
| 724 | * recreate this batchbuffer with new values (including all the missing |
| 725 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ |
| 726 | if (ring->id == RCS) |
| 727 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); |
| 728 | else |
| 729 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); |
| 730 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; |
| 731 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); |
| 732 | reg_state[CTX_CONTEXT_CONTROL+1] = |
| 733 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); |
| 734 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
| 735 | reg_state[CTX_RING_HEAD+1] = 0; |
| 736 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); |
| 737 | reg_state[CTX_RING_TAIL+1] = 0; |
| 738 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); |
| 739 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); |
| 740 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
| 741 | reg_state[CTX_RING_BUFFER_CONTROL+1] = |
| 742 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; |
| 743 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; |
| 744 | reg_state[CTX_BB_HEAD_U+1] = 0; |
| 745 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; |
| 746 | reg_state[CTX_BB_HEAD_L+1] = 0; |
| 747 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; |
| 748 | reg_state[CTX_BB_STATE+1] = (1<<5); |
| 749 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; |
| 750 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; |
| 751 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; |
| 752 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; |
| 753 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; |
| 754 | reg_state[CTX_SECOND_BB_STATE+1] = 0; |
| 755 | if (ring->id == RCS) { |
| 756 | /* TODO: according to BSpec, the register state context |
| 757 | * for CHV does not have these. OTOH, these registers do |
| 758 | * exist in CHV. I'm waiting for a clarification */ |
| 759 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
| 760 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; |
| 761 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; |
| 762 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; |
| 763 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; |
| 764 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; |
| 765 | } |
| 766 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); |
| 767 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; |
| 768 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; |
| 769 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; |
| 770 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); |
| 771 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); |
| 772 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); |
| 773 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); |
| 774 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); |
| 775 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); |
| 776 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); |
| 777 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); |
| 778 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); |
| 779 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); |
| 780 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); |
| 781 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); |
| 782 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); |
| 783 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); |
| 784 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); |
| 785 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); |
| 786 | if (ring->id == RCS) { |
| 787 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
| 788 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; |
| 789 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; |
| 790 | } |
| 791 | |
| 792 | kunmap_atomic(reg_state); |
| 793 | |
| 794 | ctx_obj->dirty = 1; |
| 795 | set_page_dirty(page); |
| 796 | i915_gem_object_unpin_pages(ctx_obj); |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 801 | void intel_lr_context_free(struct intel_context *ctx) |
| 802 | { |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 803 | int i; |
| 804 | |
| 805 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 806 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 807 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
| 808 | |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 809 | if (ctx_obj) { |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 810 | intel_destroy_ringbuffer_obj(ringbuf); |
| 811 | kfree(ringbuf); |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 812 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 813 | drm_gem_object_unreference(&ctx_obj->base); |
| 814 | } |
| 815 | } |
| 816 | } |
| 817 | |
| 818 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) |
| 819 | { |
| 820 | int ret = 0; |
| 821 | |
| 822 | WARN_ON(INTEL_INFO(ring->dev)->gen != 8); |
| 823 | |
| 824 | switch (ring->id) { |
| 825 | case RCS: |
| 826 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; |
| 827 | break; |
| 828 | case VCS: |
| 829 | case BCS: |
| 830 | case VECS: |
| 831 | case VCS2: |
| 832 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; |
| 833 | break; |
| 834 | } |
| 835 | |
| 836 | return ret; |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 837 | } |
| 838 | |
| 839 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
| 840 | struct intel_engine_cs *ring) |
| 841 | { |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 842 | struct drm_device *dev = ring->dev; |
| 843 | struct drm_i915_gem_object *ctx_obj; |
| 844 | uint32_t context_size; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 845 | struct intel_ringbuffer *ringbuf; |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 846 | int ret; |
| 847 | |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 848 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 849 | if (ctx->engine[ring->id].state) |
| 850 | return 0; |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 851 | |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 852 | context_size = round_up(get_lr_context_size(ring), 4096); |
| 853 | |
| 854 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); |
| 855 | if (IS_ERR(ctx_obj)) { |
| 856 | ret = PTR_ERR(ctx_obj); |
| 857 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); |
| 858 | return ret; |
| 859 | } |
| 860 | |
| 861 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); |
| 862 | if (ret) { |
| 863 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); |
| 864 | drm_gem_object_unreference(&ctx_obj->base); |
| 865 | return ret; |
| 866 | } |
| 867 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 868 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
| 869 | if (!ringbuf) { |
| 870 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", |
| 871 | ring->name); |
| 872 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 873 | drm_gem_object_unreference(&ctx_obj->base); |
| 874 | ret = -ENOMEM; |
| 875 | return ret; |
| 876 | } |
| 877 | |
Daniel Vetter | 0c7dd53 | 2014-08-11 16:17:44 +0200 | [diff] [blame] | 878 | ringbuf->ring = ring; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 879 | ringbuf->size = 32 * PAGE_SIZE; |
| 880 | ringbuf->effective_size = ringbuf->size; |
| 881 | ringbuf->head = 0; |
| 882 | ringbuf->tail = 0; |
| 883 | ringbuf->space = ringbuf->size; |
| 884 | ringbuf->last_retired_head = -1; |
| 885 | |
| 886 | /* TODO: For now we put this in the mappable region so that we can reuse |
| 887 | * the existing ringbuffer code which ioremaps it. When we start |
| 888 | * creating many contexts, this will no longer work and we must switch |
| 889 | * to a kmapish interface. |
| 890 | */ |
| 891 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
| 892 | if (ret) { |
| 893 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", |
| 894 | ring->name, ret); |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 895 | goto error; |
| 896 | } |
| 897 | |
| 898 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); |
| 899 | if (ret) { |
| 900 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); |
| 901 | intel_destroy_ringbuffer_obj(ringbuf); |
| 902 | goto error; |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 903 | } |
| 904 | |
| 905 | ctx->engine[ring->id].ringbuf = ringbuf; |
Oscar Mateo | 8c857917 | 2014-07-24 17:04:14 +0100 | [diff] [blame] | 906 | ctx->engine[ring->id].state = ctx_obj; |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 907 | |
| 908 | return 0; |
Oscar Mateo | 8670d6f | 2014-07-24 17:04:17 +0100 | [diff] [blame] | 909 | |
| 910 | error: |
| 911 | kfree(ringbuf); |
| 912 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 913 | drm_gem_object_unreference(&ctx_obj->base); |
| 914 | return ret; |
Oscar Mateo | ede7d42 | 2014-07-24 17:04:12 +0100 | [diff] [blame] | 915 | } |