David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 1 | /* MN10300 CPU core caching routines |
| 2 | * |
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public Licence |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the Licence, or (at your option) any later version. |
| 10 | */ |
| 11 | #include <linux/sys.h> |
| 12 | #include <linux/linkage.h> |
| 13 | #include <asm/smp.h> |
| 14 | #include <asm/page.h> |
| 15 | #include <asm/cache.h> |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 16 | #include <asm/irqflags.h> |
| 17 | #include <asm/cacheflush.h> |
David Howells | b75bb23 | 2011-03-18 16:54:29 +0000 | [diff] [blame] | 18 | #include "cache.inc" |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 19 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 20 | #define mn10300_local_dcache_inv_range_intr_interval \ |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 21 | +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1) |
| 22 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 23 | #if mn10300_local_dcache_inv_range_intr_interval > 0xff |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 24 | #error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less |
| 25 | #endif |
| 26 | |
| 27 | .am33_2 |
| 28 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 29 | .globl mn10300_local_icache_inv_page |
| 30 | .globl mn10300_local_icache_inv_range |
| 31 | .globl mn10300_local_icache_inv_range2 |
| 32 | |
| 33 | mn10300_local_icache_inv_page = mn10300_local_icache_inv |
| 34 | mn10300_local_icache_inv_range = mn10300_local_icache_inv |
| 35 | mn10300_local_icache_inv_range2 = mn10300_local_icache_inv |
| 36 | |
| 37 | #ifndef CONFIG_SMP |
| 38 | .globl mn10300_icache_inv |
| 39 | .globl mn10300_icache_inv_page |
| 40 | .globl mn10300_icache_inv_range |
| 41 | .globl mn10300_icache_inv_range2 |
| 42 | .globl mn10300_dcache_inv |
| 43 | .globl mn10300_dcache_inv_page |
| 44 | .globl mn10300_dcache_inv_range |
| 45 | .globl mn10300_dcache_inv_range2 |
| 46 | |
| 47 | mn10300_icache_inv = mn10300_local_icache_inv |
| 48 | mn10300_icache_inv_page = mn10300_local_icache_inv_page |
| 49 | mn10300_icache_inv_range = mn10300_local_icache_inv_range |
| 50 | mn10300_icache_inv_range2 = mn10300_local_icache_inv_range2 |
| 51 | mn10300_dcache_inv = mn10300_local_dcache_inv |
| 52 | mn10300_dcache_inv_page = mn10300_local_dcache_inv_page |
| 53 | mn10300_dcache_inv_range = mn10300_local_dcache_inv_range |
| 54 | mn10300_dcache_inv_range2 = mn10300_local_dcache_inv_range2 |
| 55 | |
| 56 | #endif /* !CONFIG_SMP */ |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 57 | |
| 58 | ############################################################################### |
| 59 | # |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 60 | # void mn10300_local_icache_inv(void) |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 61 | # Invalidate the entire icache |
| 62 | # |
| 63 | ############################################################################### |
| 64 | ALIGN |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 65 | .globl mn10300_local_icache_inv |
| 66 | .type mn10300_local_icache_inv,@function |
| 67 | mn10300_local_icache_inv: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 68 | mov CHCTR,a0 |
| 69 | |
| 70 | movhu (a0),d0 |
| 71 | btst CHCTR_ICEN,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 72 | beq mn10300_local_icache_inv_end |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 73 | |
David Howells | b75bb23 | 2011-03-18 16:54:29 +0000 | [diff] [blame] | 74 | invalidate_icache 1 |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 75 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 76 | mn10300_local_icache_inv_end: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 77 | ret [],0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 78 | .size mn10300_local_icache_inv,.-mn10300_local_icache_inv |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 79 | |
| 80 | ############################################################################### |
| 81 | # |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 82 | # void mn10300_local_dcache_inv(void) |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 83 | # Invalidate the entire dcache |
| 84 | # |
| 85 | ############################################################################### |
| 86 | ALIGN |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 87 | .globl mn10300_local_dcache_inv |
| 88 | .type mn10300_local_dcache_inv,@function |
| 89 | mn10300_local_dcache_inv: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 90 | mov CHCTR,a0 |
| 91 | |
| 92 | movhu (a0),d0 |
| 93 | btst CHCTR_DCEN,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 94 | beq mn10300_local_dcache_inv_end |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 95 | |
David Howells | b75bb23 | 2011-03-18 16:54:29 +0000 | [diff] [blame] | 96 | invalidate_dcache 1 |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 97 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 98 | mn10300_local_dcache_inv_end: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 99 | ret [],0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 100 | .size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 101 | |
| 102 | ############################################################################### |
| 103 | # |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 104 | # void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end) |
| 105 | # void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size) |
| 106 | # void mn10300_local_dcache_inv_page(unsigned long start) |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 107 | # Invalidate a range of addresses on a page in the dcache |
| 108 | # |
| 109 | ############################################################################### |
| 110 | ALIGN |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 111 | .globl mn10300_local_dcache_inv_page |
| 112 | .globl mn10300_local_dcache_inv_range |
| 113 | .globl mn10300_local_dcache_inv_range2 |
| 114 | .type mn10300_local_dcache_inv_page,@function |
| 115 | .type mn10300_local_dcache_inv_range,@function |
| 116 | .type mn10300_local_dcache_inv_range2,@function |
| 117 | mn10300_local_dcache_inv_page: |
| 118 | and ~(PAGE_SIZE-1),d0 |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 119 | mov PAGE_SIZE,d1 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 120 | mn10300_local_dcache_inv_range2: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 121 | add d0,d1 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 122 | mn10300_local_dcache_inv_range: |
| 123 | # If we are in writeback mode we check the start and end alignments, |
| 124 | # and if they're not cacheline-aligned, we must flush any bits outside |
| 125 | # the range that share cachelines with stuff inside the range |
| 126 | #ifdef CONFIG_MN10300_CACHE_WBACK |
David Howells | 7f386ac | 2011-03-18 16:54:30 +0000 | [diff] [blame] | 127 | btst ~L1_CACHE_TAG_MASK,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 128 | bne 1f |
David Howells | 7f386ac | 2011-03-18 16:54:30 +0000 | [diff] [blame] | 129 | btst ~L1_CACHE_TAG_MASK,d1 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 130 | beq 2f |
| 131 | 1: |
| 132 | bra mn10300_local_dcache_flush_inv_range |
| 133 | 2: |
| 134 | #endif /* CONFIG_MN10300_CACHE_WBACK */ |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 135 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 136 | movm [d2,d3,a2],(sp) |
| 137 | |
| 138 | mov CHCTR,a2 |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 139 | movhu (a2),d2 |
| 140 | btst CHCTR_DCEN,d2 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 141 | beq mn10300_local_dcache_inv_range_end |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 142 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 143 | #ifndef CONFIG_MN10300_CACHE_WBACK |
David Howells | 7f386ac | 2011-03-18 16:54:30 +0000 | [diff] [blame] | 144 | and L1_CACHE_TAG_MASK,d0 # round start addr down |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 145 | |
| 146 | add L1_CACHE_BYTES,d1 # round end addr up |
David Howells | 7f386ac | 2011-03-18 16:54:30 +0000 | [diff] [blame] | 147 | and L1_CACHE_TAG_MASK,d1 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 148 | #endif /* !CONFIG_MN10300_CACHE_WBACK */ |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 149 | mov d0,a1 |
| 150 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 151 | clr d2 # we're going to clear tag RAM |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 152 | # entries |
| 153 | |
| 154 | # read the tags from the tag RAM, and if they indicate a valid dirty |
| 155 | # cache line then invalidate that line |
| 156 | mov DCACHE_TAG(0,0),a0 |
| 157 | mov a1,d0 |
| 158 | and L1_CACHE_TAG_ENTRY,d0 |
| 159 | add d0,a0 # starting dcache tag RAM |
| 160 | # access address |
| 161 | |
| 162 | sub a1,d1 |
| 163 | lsr L1_CACHE_SHIFT,d1 # total number of entries to |
| 164 | # examine |
| 165 | |
| 166 | and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base |
| 167 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 168 | mn10300_local_dcache_inv_range_outer_loop: |
| 169 | LOCAL_CLI_SAVE(d3) |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 170 | |
| 171 | # disable the dcache |
| 172 | movhu (a2),d0 |
| 173 | and ~CHCTR_DCEN,d0 |
| 174 | movhu d0,(a2) |
| 175 | |
| 176 | # and wait for it to calm down |
| 177 | setlb |
| 178 | movhu (a2),d0 |
| 179 | btst CHCTR_DCBUSY,d0 |
| 180 | lne |
| 181 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 182 | mn10300_local_dcache_inv_range_loop: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 183 | |
| 184 | # process the way 0 slot |
| 185 | mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot |
| 186 | btst L1_CACHE_TAG_VALID,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 187 | beq mn10300_local_dcache_inv_range_skip_0 # jump if this cacheline |
| 188 | # is not valid |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 189 | |
| 190 | xor a1,d0 |
| 191 | lsr 12,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 192 | bne mn10300_local_dcache_inv_range_skip_0 # jump if not this cacheline |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 193 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 194 | mov d2,(L1_CACHE_WAYDISP*0,a0) # kill the tag |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 195 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 196 | mn10300_local_dcache_inv_range_skip_0: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 197 | |
| 198 | # process the way 1 slot |
| 199 | mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot |
| 200 | btst L1_CACHE_TAG_VALID,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 201 | beq mn10300_local_dcache_inv_range_skip_1 # jump if this cacheline |
| 202 | # is not valid |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 203 | |
| 204 | xor a1,d0 |
| 205 | lsr 12,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 206 | bne mn10300_local_dcache_inv_range_skip_1 # jump if not this cacheline |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 207 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 208 | mov d2,(L1_CACHE_WAYDISP*1,a0) # kill the tag |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 209 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 210 | mn10300_local_dcache_inv_range_skip_1: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 211 | |
| 212 | # process the way 2 slot |
| 213 | mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot |
| 214 | btst L1_CACHE_TAG_VALID,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 215 | beq mn10300_local_dcache_inv_range_skip_2 # jump if this cacheline |
| 216 | # is not valid |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 217 | |
| 218 | xor a1,d0 |
| 219 | lsr 12,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 220 | bne mn10300_local_dcache_inv_range_skip_2 # jump if not this cacheline |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 221 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 222 | mov d2,(L1_CACHE_WAYDISP*2,a0) # kill the tag |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 223 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 224 | mn10300_local_dcache_inv_range_skip_2: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 225 | |
| 226 | # process the way 3 slot |
| 227 | mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot |
| 228 | btst L1_CACHE_TAG_VALID,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 229 | beq mn10300_local_dcache_inv_range_skip_3 # jump if this cacheline |
| 230 | # is not valid |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 231 | |
| 232 | xor a1,d0 |
| 233 | lsr 12,d0 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 234 | bne mn10300_local_dcache_inv_range_skip_3 # jump if not this cacheline |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 235 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 236 | mov d2,(L1_CACHE_WAYDISP*3,a0) # kill the tag |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 237 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 238 | mn10300_local_dcache_inv_range_skip_3: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 239 | |
| 240 | # approx every N steps we re-enable the cache and see if there are any |
| 241 | # interrupts to be processed |
| 242 | # we also break out if we've reached the end of the loop |
| 243 | # (the bottom nibble of the count is zero in both cases) |
| 244 | add L1_CACHE_BYTES,a0 |
| 245 | add L1_CACHE_BYTES,a1 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 246 | and ~L1_CACHE_WAYDISP,a0 |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 247 | add -1,d1 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 248 | btst mn10300_local_dcache_inv_range_intr_interval,d1 |
| 249 | bne mn10300_local_dcache_inv_range_loop |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 250 | |
| 251 | # wait for the cache to finish what it's doing |
| 252 | setlb |
| 253 | movhu (a2),d0 |
| 254 | btst CHCTR_DCBUSY,d0 |
| 255 | lne |
| 256 | |
| 257 | # and reenable it |
| 258 | or CHCTR_DCEN,d0 |
| 259 | movhu d0,(a2) |
| 260 | movhu (a2),d0 |
| 261 | |
| 262 | # re-enable interrupts |
| 263 | # - we don't bother with delay NOPs as we'll have enough instructions |
| 264 | # before we disable interrupts again to give the interrupts a chance |
| 265 | # to happen |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 266 | LOCAL_IRQ_RESTORE(d3) |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 267 | |
| 268 | # go around again if the counter hasn't yet reached zero |
| 269 | add 0,d1 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 270 | bne mn10300_local_dcache_inv_range_outer_loop |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 271 | |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 272 | mn10300_local_dcache_inv_range_end: |
David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 273 | ret [d2,d3,a2],12 |
Akira Takeuchi | 0bd3eb6 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 274 | .size mn10300_local_dcache_inv_page,.-mn10300_local_dcache_inv_page |
| 275 | .size mn10300_local_dcache_inv_range,.-mn10300_local_dcache_inv_range |
| 276 | .size mn10300_local_dcache_inv_range2,.-mn10300_local_dcache_inv_range2 |