blob: 2bef086fb34268afaf0e65ec01e5017627142721 [file] [log] [blame]
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001/*
2 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
Patrick McHardy37a80232007-11-21 12:47:13 +080022#include <linux/moduleparam.h>
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +080023#include <linux/mod_devicetable.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/mm.h>
Andrew Morton102d49d2007-11-13 21:55:28 +080029#include <linux/dma-mapping.h>
30#include <linux/scatterlist.h>
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +080031#include <linux/highmem.h>
32#include <linux/crypto.h>
Patrick McHardyfcd06752007-11-21 12:51:52 +080033#include <linux/hw_random.h>
34#include <linux/ktime.h>
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +080035
36#include <crypto/algapi.h>
Evgeniy Polyakovc3041f92007-10-11 19:58:16 +080037#include <crypto/des.h>
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +080038
39#include <asm/kmap_types.h>
40
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +080041//#define HIFN_DEBUG
42
43#ifdef HIFN_DEBUG
44#define dprintk(f, a...) printk(f, ##a)
45#else
46#define dprintk(f, a...) do {} while (0)
47#endif
48
Patrick McHardy37a80232007-11-21 12:47:13 +080049static char hifn_pll_ref[sizeof("extNNN")] = "ext";
50module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
51MODULE_PARM_DESC(hifn_pll_ref,
52 "PLL reference clock (pci[freq] or ext[freq], default ext)");
53
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +080054static atomic_t hifn_dev_number;
55
56#define ACRYPTO_OP_DECRYPT 0
57#define ACRYPTO_OP_ENCRYPT 1
58#define ACRYPTO_OP_HMAC 2
59#define ACRYPTO_OP_RNG 3
60
61#define ACRYPTO_MODE_ECB 0
62#define ACRYPTO_MODE_CBC 1
63#define ACRYPTO_MODE_CFB 2
64#define ACRYPTO_MODE_OFB 3
65
66#define ACRYPTO_TYPE_AES_128 0
67#define ACRYPTO_TYPE_AES_192 1
68#define ACRYPTO_TYPE_AES_256 2
69#define ACRYPTO_TYPE_3DES 3
70#define ACRYPTO_TYPE_DES 4
71
72#define PCI_VENDOR_ID_HIFN 0x13A3
73#define PCI_DEVICE_ID_HIFN_7955 0x0020
74#define PCI_DEVICE_ID_HIFN_7956 0x001d
75
76/* I/O region sizes */
77
78#define HIFN_BAR0_SIZE 0x1000
79#define HIFN_BAR1_SIZE 0x2000
80#define HIFN_BAR2_SIZE 0x8000
81
82/* DMA registres */
83
84#define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
85#define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
86#define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
87#define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
88#define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
89#define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
90#define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
91#define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
92#define HIFN_CHIP_ID 0x98 /* Chip ID */
93
94/*
95 * Processing Unit Registers (offset from BASEREG0)
96 */
97#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
98#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
99#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
100#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
101#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
102#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
103#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
104#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
105#define HIFN_0_SPACESIZE 0x20 /* Register space size */
106
107/* Processing Unit Control Register (HIFN_0_PUCTRL) */
108#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
109#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
110#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
111#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
112#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
113
114/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
115#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
116#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
117#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
118#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
119#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
120#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
121#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
122#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
123#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
124#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
125
126/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
127#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
128#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
129#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
130#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
131#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
132#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
133#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
134#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
135#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
136#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
137#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
138#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
139#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
140#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
141#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
142#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
143#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
144#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
145#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
146#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
147#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
148#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
149#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
150
151/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
152#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
153#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
154#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
155#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
156#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
157#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
158#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
159#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
160#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
161#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
162
163/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
164#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
165#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
166#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
167#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
168#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
169#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
170#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
171#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
172#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
173#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
174#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
175#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
176#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
177#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
178#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
179#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
180#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
181
182/* FIFO Status Register (HIFN_0_FIFOSTAT) */
183#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
184#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
185
186/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
187#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
188
189/*
190 * DMA Interface Registers (offset from BASEREG1)
191 */
192#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
193#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
194#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
195#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
196#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
197#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
198#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
199#define HIFN_1_PLL 0x4c /* 795x: PLL config */
200#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
201#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
202#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
203#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
204#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
205#define HIFN_1_REVID 0x98 /* Revision ID */
206#define HIFN_1_UNLOCK_SECRET1 0xf4
207#define HIFN_1_UNLOCK_SECRET2 0xfc
208#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
209#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
210#define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
211#define HIFN_1_PUB_OP 0x308 /* Public Operand */
212#define HIFN_1_PUB_STATUS 0x30c /* Public Status */
213#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
214#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
215#define HIFN_1_RNG_DATA 0x318 /* RNG data */
216#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
217#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
218
219/* DMA Status and Control Register (HIFN_1_DMA_CSR) */
220#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
221#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
222#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
223#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
224#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
225#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
226#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
227#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
228#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
229#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
230#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
231#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
232#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
233#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
234#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
235#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
236#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
237#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
238#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
239#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
240#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
241#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
242#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
243#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
244#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
245#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
246#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
247#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
248#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
249#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
250#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
251#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
252#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
253#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
254#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
255#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
256#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
257#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
258
259/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
260#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
261#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
262#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
263#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
264#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
265#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
266#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
267#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
268#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
269#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
270#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
271#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
272#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
273#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
274#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
275#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
276#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
277#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
278#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
279#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
280#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
281#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
282
283/* DMA Configuration Register (HIFN_1_DMA_CNFG) */
284#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
285#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
286#define HIFN_DMACNFG_UNLOCK 0x00000800
287#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
288#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
289#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
290#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
291#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
292
Patrick McHardy37a80232007-11-21 12:47:13 +0800293/* PLL configuration register */
294#define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */
295#define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */
296#define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */
297#define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */
298#define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */
299#define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */
300#define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */
301#define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */
302#define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */
303#define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */
304#define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */
305#define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */
306#define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */
307#define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */
308#define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */
309#define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */
310#define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */
311
312#define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800313
314/* Public key reset register (HIFN_1_PUB_RESET) */
315#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
316
317/* Public base address register (HIFN_1_PUB_BASE) */
318#define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
319
320/* Public operand length register (HIFN_1_PUB_OPLEN) */
321#define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
322#define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
323#define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
324#define HIFN_PUBOPLEN_EXP_S 7 /* exponent lenght shift */
325#define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
326#define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
327
328/* Public operation register (HIFN_1_PUB_OP) */
329#define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
330#define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
331#define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
332#define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
333#define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
334#define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
335#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
336#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
337#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
338#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
339#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
340#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
341#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
342#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
343#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
344#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
345#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
346#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
347#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
348#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
349
350/* Public status register (HIFN_1_PUB_STATUS) */
351#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
352#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
353
354/* Public interrupt enable register (HIFN_1_PUB_IEN) */
355#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
356
357/* Random number generator config register (HIFN_1_RNG_CONFIG) */
358#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
359
360#define HIFN_NAMESIZE 32
361#define HIFN_MAX_RESULT_ORDER 5
362
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +0800363#define HIFN_D_CMD_RSIZE 24*1
364#define HIFN_D_SRC_RSIZE 80*1
365#define HIFN_D_DST_RSIZE 80*1
366#define HIFN_D_RES_RSIZE 24*1
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800367
Patrick McHardyd0690332008-05-07 22:33:37 +0800368#define HIFN_D_DST_DALIGN 4
369
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +0800370#define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800371
372#define AES_MIN_KEY_SIZE 16
373#define AES_MAX_KEY_SIZE 32
374
375#define HIFN_DES_KEY_LENGTH 8
376#define HIFN_3DES_KEY_LENGTH 24
377#define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
378#define HIFN_IV_LENGTH 8
379#define HIFN_AES_IV_LENGTH 16
380#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
381
382#define HIFN_MAC_KEY_LENGTH 64
383#define HIFN_MD5_LENGTH 16
384#define HIFN_SHA1_LENGTH 20
385#define HIFN_MAC_TRUNC_LENGTH 12
386
387#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
388#define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
389#define HIFN_USED_RESULT 12
390
391struct hifn_desc
392{
Al Viroe68970c2008-03-29 03:09:58 +0000393 volatile __le32 l;
394 volatile __le32 p;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800395};
396
397struct hifn_dma {
398 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
399 struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
400 struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
401 struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
402
403 u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
404 u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
405
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800406 /*
407 * Our current positions for insertion and removal from the descriptor
408 * rings.
409 */
410 volatile int cmdi, srci, dsti, resi;
411 volatile int cmdu, srcu, dstu, resu;
412 int cmdk, srck, dstk, resk;
413};
414
415#define HIFN_FLAG_CMD_BUSY (1<<0)
416#define HIFN_FLAG_SRC_BUSY (1<<1)
417#define HIFN_FLAG_DST_BUSY (1<<2)
418#define HIFN_FLAG_RES_BUSY (1<<3)
419#define HIFN_FLAG_OLD_KEY (1<<4)
420
421#define HIFN_DEFAULT_ACTIVE_NUM 5
422
423struct hifn_device
424{
425 char name[HIFN_NAMESIZE];
426
427 int irq;
428
429 struct pci_dev *pdev;
430 void __iomem *bar[3];
431
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800432 void *desc_virt;
433 dma_addr_t desc_dma;
434
435 u32 dmareg;
436
437 void *sa[HIFN_D_RES_RSIZE];
438
439 spinlock_t lock;
440
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800441 u32 flags;
442 int active, started;
443 struct delayed_work work;
444 unsigned long reset;
445 unsigned long success;
446 unsigned long prev_success;
447
448 u8 snum;
449
Evgeniy Polyakova1e6ef22007-11-10 20:24:18 +0800450 struct tasklet_struct tasklet;
451
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800452 struct crypto_queue queue;
453 struct list_head alg_list;
Patrick McHardyfcd06752007-11-21 12:51:52 +0800454
455 unsigned int pk_clk_freq;
456
Patrick McHardyf881d822008-02-15 19:15:05 +0800457#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
Patrick McHardyfcd06752007-11-21 12:51:52 +0800458 unsigned int rng_wait_time;
459 ktime_t rngtime;
460 struct hwrng rng;
461#endif
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800462};
463
464#define HIFN_D_LENGTH 0x0000ffff
465#define HIFN_D_NOINVALID 0x01000000
466#define HIFN_D_MASKDONEIRQ 0x02000000
467#define HIFN_D_DESTOVER 0x04000000
468#define HIFN_D_OVER 0x08000000
469#define HIFN_D_LAST 0x20000000
470#define HIFN_D_JUMP 0x40000000
471#define HIFN_D_VALID 0x80000000
472
473struct hifn_base_command
474{
Al Viroe68970c2008-03-29 03:09:58 +0000475 volatile __le16 masks;
476 volatile __le16 session_num;
477 volatile __le16 total_source_count;
478 volatile __le16 total_dest_count;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800479};
480
481#define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
482#define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
483#define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
484#define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
485#define HIFN_BASE_CMD_DECODE 0x2000
486#define HIFN_BASE_CMD_SRCLEN_M 0xc000
487#define HIFN_BASE_CMD_SRCLEN_S 14
488#define HIFN_BASE_CMD_DSTLEN_M 0x3000
489#define HIFN_BASE_CMD_DSTLEN_S 12
490#define HIFN_BASE_CMD_LENMASK_HI 0x30000
491#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
492
493/*
494 * Structure to help build up the command data structure.
495 */
496struct hifn_crypt_command
497{
Al Viroe68970c2008-03-29 03:09:58 +0000498 volatile __le16 masks;
499 volatile __le16 header_skip;
500 volatile __le16 source_count;
501 volatile __le16 reserved;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800502};
503
504#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
505#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
506#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
507#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
508#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
509#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
510#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
511#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
512#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
513#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
514#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
515#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
516#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
517#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
518#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
519#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
520#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
521#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
522#define HIFN_CRYPT_CMD_SRCLEN_S 14
523
524/*
525 * Structure to help build up the command data structure.
526 */
527struct hifn_mac_command
528{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800529 volatile __le16 masks;
530 volatile __le16 header_skip;
531 volatile __le16 source_count;
532 volatile __le16 reserved;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800533};
534
535#define HIFN_MAC_CMD_ALG_MASK 0x0001
536#define HIFN_MAC_CMD_ALG_SHA1 0x0000
537#define HIFN_MAC_CMD_ALG_MD5 0x0001
538#define HIFN_MAC_CMD_MODE_MASK 0x000c
539#define HIFN_MAC_CMD_MODE_HMAC 0x0000
540#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
541#define HIFN_MAC_CMD_MODE_HASH 0x0008
542#define HIFN_MAC_CMD_MODE_FULL 0x0004
543#define HIFN_MAC_CMD_TRUNC 0x0010
544#define HIFN_MAC_CMD_RESULT 0x0020
545#define HIFN_MAC_CMD_APPEND 0x0040
546#define HIFN_MAC_CMD_SRCLEN_M 0xc000
547#define HIFN_MAC_CMD_SRCLEN_S 14
548
549/*
550 * MAC POS IPsec initiates authentication after encryption on encodes
551 * and before decryption on decodes.
552 */
553#define HIFN_MAC_CMD_POS_IPSEC 0x0200
554#define HIFN_MAC_CMD_NEW_KEY 0x0800
555
556struct hifn_comp_command
557{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800558 volatile __le16 masks;
559 volatile __le16 header_skip;
560 volatile __le16 source_count;
561 volatile __le16 reserved;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800562};
563
564#define HIFN_COMP_CMD_SRCLEN_M 0xc000
565#define HIFN_COMP_CMD_SRCLEN_S 14
566#define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
567#define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
568#define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
569#define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
570#define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
571#define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
572#define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
573#define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
574
575struct hifn_base_result
576{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800577 volatile __le16 flags;
578 volatile __le16 session;
579 volatile __le16 src_cnt; /* 15:0 of source count */
580 volatile __le16 dst_cnt; /* 15:0 of dest count */
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800581};
582
583#define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
584#define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
585#define HIFN_BASE_RES_SRCLEN_S 14
586#define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
587#define HIFN_BASE_RES_DSTLEN_S 12
588
589struct hifn_comp_result
590{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800591 volatile __le16 flags;
592 volatile __le16 crc;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800593};
594
595#define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
596#define HIFN_COMP_RES_LCB_S 8
597#define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
598#define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
599#define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
600
601struct hifn_mac_result
602{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800603 volatile __le16 flags;
604 volatile __le16 reserved;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800605 /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
606};
607
608#define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
609#define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
610
611struct hifn_crypt_result
612{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800613 volatile __le16 flags;
614 volatile __le16 reserved;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800615};
616
617#define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
618
619#ifndef HIFN_POLL_FREQUENCY
620#define HIFN_POLL_FREQUENCY 0x1
621#endif
622
623#ifndef HIFN_POLL_SCALAR
624#define HIFN_POLL_SCALAR 0x0
625#endif
626
627#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
628#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
629
630struct hifn_crypto_alg
631{
632 struct list_head entry;
633 struct crypto_alg alg;
634 struct hifn_device *dev;
635};
636
637#define ASYNC_SCATTERLIST_CACHE 16
638
639#define ASYNC_FLAGS_MISALIGNED (1<<0)
640
641struct ablkcipher_walk
642{
643 struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
644 u32 flags;
645 int num;
646};
647
648struct hifn_context
649{
Patrick McHardy5df4c0c2008-11-24 22:01:42 +0800650 u8 key[HIFN_MAX_CRYPT_KEY_LENGTH];
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800651 struct hifn_device *dev;
Patrick McHardy5df4c0c2008-11-24 22:01:42 +0800652 unsigned int keysize;
653};
654
655struct hifn_request_context
656{
657 u8 *iv;
658 unsigned int ivsize;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800659 u8 op, type, mode, unused;
660 struct ablkcipher_walk walk;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800661};
662
Alexey Dobriyanb966b542008-01-08 21:36:34 +1100663#define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800664
665static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
666{
667 u32 ret;
668
Al Viroe68970c2008-03-29 03:09:58 +0000669 ret = readl(dev->bar[0] + reg);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800670
671 return ret;
672}
673
674static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
675{
676 u32 ret;
677
Al Viroe68970c2008-03-29 03:09:58 +0000678 ret = readl(dev->bar[1] + reg);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800679
680 return ret;
681}
682
683static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
684{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800685 writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800686}
687
688static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
689{
Patrick McHardy3c42cbc2008-05-07 22:28:27 +0800690 writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800691}
692
693static void hifn_wait_puc(struct hifn_device *dev)
694{
695 int i;
696 u32 ret;
697
698 for (i=10000; i > 0; --i) {
699 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
700 if (!(ret & HIFN_PUCTRL_RESET))
701 break;
702
703 udelay(1);
704 }
705
706 if (!i)
707 dprintk("%s: Failed to reset PUC unit.\n", dev->name);
708}
709
710static void hifn_reset_puc(struct hifn_device *dev)
711{
712 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
713 hifn_wait_puc(dev);
714}
715
716static void hifn_stop_device(struct hifn_device *dev)
717{
718 hifn_write_1(dev, HIFN_1_DMA_CSR,
719 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
720 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
721 hifn_write_0(dev, HIFN_0_PUIER, 0);
722 hifn_write_1(dev, HIFN_1_DMA_IER, 0);
723}
724
725static void hifn_reset_dma(struct hifn_device *dev, int full)
726{
727 hifn_stop_device(dev);
728
729 /*
730 * Setting poll frequency and others to 0.
731 */
732 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
733 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
734 mdelay(1);
735
736 /*
737 * Reset DMA.
738 */
739 if (full) {
740 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
741 mdelay(1);
742 } else {
743 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
744 HIFN_DMACNFG_MSTRESET);
745 hifn_reset_puc(dev);
746 }
747
748 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
749 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
750
751 hifn_reset_puc(dev);
752}
753
754static u32 hifn_next_signature(u_int32_t a, u_int cnt)
755{
756 int i;
757 u32 v;
758
759 for (i = 0; i < cnt; i++) {
760
761 /* get the parity */
762 v = a & 0x80080125;
763 v ^= v >> 16;
764 v ^= v >> 8;
765 v ^= v >> 4;
766 v ^= v >> 2;
767 v ^= v >> 1;
768
769 a = (v & 1) ^ (a << 1);
770 }
771
772 return a;
773}
774
775static struct pci2id {
776 u_short pci_vendor;
777 u_short pci_prod;
778 char card_id[13];
779} pci2id[] = {
780 {
781 PCI_VENDOR_ID_HIFN,
782 PCI_DEVICE_ID_HIFN_7955,
783 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
784 0x00, 0x00, 0x00, 0x00, 0x00 }
785 },
786 {
787 PCI_VENDOR_ID_HIFN,
788 PCI_DEVICE_ID_HIFN_7956,
789 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
790 0x00, 0x00, 0x00, 0x00, 0x00 }
791 }
792};
793
Patrick McHardyf881d822008-02-15 19:15:05 +0800794#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
Patrick McHardyfcd06752007-11-21 12:51:52 +0800795static int hifn_rng_data_present(struct hwrng *rng, int wait)
796{
797 struct hifn_device *dev = (struct hifn_device *)rng->priv;
798 s64 nsec;
799
800 nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
801 nsec -= dev->rng_wait_time;
802 if (nsec <= 0)
803 return 1;
804 if (!wait)
805 return 0;
806 ndelay(nsec);
807 return 1;
808}
809
810static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
811{
812 struct hifn_device *dev = (struct hifn_device *)rng->priv;
813
814 *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
815 dev->rngtime = ktime_get();
816 return 4;
817}
818
819static int hifn_register_rng(struct hifn_device *dev)
820{
821 /*
822 * We must wait at least 256 Pk_clk cycles between two reads of the rng.
823 */
824 dev->rng_wait_time = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) *
825 256;
826
827 dev->rng.name = dev->name;
828 dev->rng.data_present = hifn_rng_data_present,
829 dev->rng.data_read = hifn_rng_data_read,
830 dev->rng.priv = (unsigned long)dev;
831
832 return hwrng_register(&dev->rng);
833}
834
835static void hifn_unregister_rng(struct hifn_device *dev)
836{
837 hwrng_unregister(&dev->rng);
838}
839#else
840#define hifn_register_rng(dev) 0
841#define hifn_unregister_rng(dev)
842#endif
843
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800844static int hifn_init_pubrng(struct hifn_device *dev)
845{
846 int i;
847
848 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
849 HIFN_PUBRST_RESET);
850
851 for (i=100; i > 0; --i) {
852 mdelay(1);
853
854 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
855 break;
856 }
857
858 if (!i)
859 dprintk("Chip %s: Failed to initialise public key engine.\n",
860 dev->name);
861 else {
862 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
863 dev->dmareg |= HIFN_DMAIER_PUBDONE;
864 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
865
866 dprintk("Chip %s: Public key engine has been sucessfully "
867 "initialised.\n", dev->name);
868 }
869
870 /*
871 * Enable RNG engine.
872 */
873
874 hifn_write_1(dev, HIFN_1_RNG_CONFIG,
875 hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
876 dprintk("Chip %s: RNG engine has been successfully initialised.\n",
877 dev->name);
878
Patrick McHardyf881d822008-02-15 19:15:05 +0800879#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
Patrick McHardyfcd06752007-11-21 12:51:52 +0800880 /* First value must be discarded */
881 hifn_read_1(dev, HIFN_1_RNG_DATA);
882 dev->rngtime = ktime_get();
883#endif
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800884 return 0;
885}
886
887static int hifn_enable_crypto(struct hifn_device *dev)
888{
889 u32 dmacfg, addr;
890 char *offtbl = NULL;
891 int i;
892
Robert P. J. Day0936a942008-05-26 21:21:07 +1000893 for (i = 0; i < ARRAY_SIZE(pci2id); i++) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800894 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
895 pci2id[i].pci_prod == dev->pdev->device) {
896 offtbl = pci2id[i].card_id;
897 break;
898 }
899 }
900
901 if (offtbl == NULL) {
902 dprintk("Chip %s: Unknown card!\n", dev->name);
903 return -ENODEV;
904 }
905
906 dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
907
908 hifn_write_1(dev, HIFN_1_DMA_CNFG,
909 HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
910 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
911 mdelay(1);
912 addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
913 mdelay(1);
914 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
915 mdelay(1);
916
917 for (i=0; i<12; ++i) {
918 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
919 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
920
921 mdelay(1);
922 }
923 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
924
925 dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev));
926
927 return 0;
928}
929
930static void hifn_init_dma(struct hifn_device *dev)
931{
932 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
933 u32 dptr = dev->desc_dma;
934 int i;
935
936 for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
937 dma->cmdr[i].p = __cpu_to_le32(dptr +
938 offsetof(struct hifn_dma, command_bufs[i][0]));
939 for (i=0; i<HIFN_D_RES_RSIZE; ++i)
940 dma->resr[i].p = __cpu_to_le32(dptr +
941 offsetof(struct hifn_dma, result_bufs[i][0]));
942
943 /*
944 * Setup LAST descriptors.
945 */
946 dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
947 offsetof(struct hifn_dma, cmdr[0]));
948 dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
949 offsetof(struct hifn_dma, srcr[0]));
950 dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
951 offsetof(struct hifn_dma, dstr[0]));
952 dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
953 offsetof(struct hifn_dma, resr[0]));
954
955 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
956 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
957 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
958}
959
Patrick McHardy37a80232007-11-21 12:47:13 +0800960/*
961 * Initialize the PLL. We need to know the frequency of the reference clock
962 * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
963 * allows us to operate without the risk of overclocking the chip. If it
964 * actually uses 33MHz, the chip will operate at half the speed, this can be
965 * overriden by specifying the frequency as module parameter (pci33).
966 *
967 * Unfortunately the PCI clock is not very suitable since the HIFN needs a
968 * stable clock and the PCI clock frequency may vary, so the default is the
969 * external clock. There is no way to find out its frequency, we default to
970 * 66MHz since according to Mike Ham of HiFn, almost every board in existence
971 * has an external crystal populated at 66MHz.
972 */
973static void hifn_init_pll(struct hifn_device *dev)
974{
975 unsigned int freq, m;
976 u32 pllcfg;
977
978 pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
979
980 if (strncmp(hifn_pll_ref, "ext", 3) == 0)
981 pllcfg |= HIFN_PLL_REF_CLK_PLL;
982 else
983 pllcfg |= HIFN_PLL_REF_CLK_HBI;
984
985 if (hifn_pll_ref[3] != '\0')
986 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
987 else {
988 freq = 66;
989 printk(KERN_INFO "hifn795x: assuming %uMHz clock speed, "
990 "override with hifn_pll_ref=%.3s<frequency>\n",
991 freq, hifn_pll_ref);
992 }
993
994 m = HIFN_PLL_FCK_MAX / freq;
995
996 pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
997 if (m <= 8)
998 pllcfg |= HIFN_PLL_IS_1_8;
999 else
1000 pllcfg |= HIFN_PLL_IS_9_12;
1001
1002 /* Select clock source and enable clock bypass */
1003 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
1004 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
1005
1006 /* Let the chip lock to the input clock */
1007 mdelay(10);
1008
1009 /* Disable clock bypass */
1010 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
1011 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
1012
1013 /* Switch the engines to the PLL */
1014 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
1015 HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
Patrick McHardyfcd06752007-11-21 12:51:52 +08001016
1017 /*
1018 * The Fpk_clk runs at half the total speed. Its frequency is needed to
1019 * calculate the minimum time between two reads of the rng. Since 33MHz
1020 * is actually 33.333... we overestimate the frequency here, resulting
1021 * in slightly larger intervals.
1022 */
1023 dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
Patrick McHardy37a80232007-11-21 12:47:13 +08001024}
1025
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001026static void hifn_init_registers(struct hifn_device *dev)
1027{
1028 u32 dptr = dev->desc_dma;
1029
1030 /* Initialization magic... */
1031 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1032 hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1033 hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1034
1035 /* write all 4 ring address registers */
Patrick McHardy3c42cbc2008-05-07 22:28:27 +08001036 hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
1037 offsetof(struct hifn_dma, cmdr[0]));
1038 hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
1039 offsetof(struct hifn_dma, srcr[0]));
1040 hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
1041 offsetof(struct hifn_dma, dstr[0]));
1042 hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
1043 offsetof(struct hifn_dma, resr[0]));
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001044
1045 mdelay(2);
1046#if 0
1047 hifn_write_1(dev, HIFN_1_DMA_CSR,
1048 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1049 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1050 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1051 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1052 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1053 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1054 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1055 HIFN_DMACSR_S_WAIT |
1056 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1057 HIFN_DMACSR_C_WAIT |
1058 HIFN_DMACSR_ENGINE |
1059 HIFN_DMACSR_PUBDONE);
1060#else
1061 hifn_write_1(dev, HIFN_1_DMA_CSR,
1062 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1063 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
1064 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1065 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1066 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1067 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1068 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1069 HIFN_DMACSR_S_WAIT |
1070 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1071 HIFN_DMACSR_C_WAIT |
1072 HIFN_DMACSR_ENGINE |
1073 HIFN_DMACSR_PUBDONE);
1074#endif
1075 hifn_read_1(dev, HIFN_1_DMA_CSR);
1076
1077 dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1078 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1079 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1080 HIFN_DMAIER_ENGINE;
1081 dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
1082
1083 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1084 hifn_read_1(dev, HIFN_1_DMA_IER);
1085#if 0
1086 hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
1087 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1088 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1089 HIFN_PUCNFG_DRAM);
1090#else
1091 hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
1092#endif
Patrick McHardy37a80232007-11-21 12:47:13 +08001093 hifn_init_pll(dev);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001094
1095 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1096 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1097 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1098 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1099 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1100}
1101
1102static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
1103 unsigned dlen, unsigned slen, u16 mask, u8 snum)
1104{
1105 struct hifn_base_command *base_cmd;
1106 u8 *buf_pos = buf;
1107
1108 base_cmd = (struct hifn_base_command *)buf_pos;
1109 base_cmd->masks = __cpu_to_le16(mask);
1110 base_cmd->total_source_count =
1111 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
1112 base_cmd->total_dest_count =
1113 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1114
1115 dlen >>= 16;
1116 slen >>= 16;
1117 base_cmd->session_num = __cpu_to_le16(snum |
1118 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1119 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1120
1121 return sizeof(struct hifn_base_command);
1122}
1123
1124static int hifn_setup_crypto_command(struct hifn_device *dev,
1125 u8 *buf, unsigned dlen, unsigned slen,
1126 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
1127{
1128 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1129 struct hifn_crypt_command *cry_cmd;
1130 u8 *buf_pos = buf;
1131 u16 cmd_len;
1132
1133 cry_cmd = (struct hifn_crypt_command *)buf_pos;
1134
1135 cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
1136 dlen >>= 16;
1137 cry_cmd->masks = __cpu_to_le16(mode |
1138 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
1139 HIFN_CRYPT_CMD_SRCLEN_M));
1140 cry_cmd->header_skip = 0;
1141 cry_cmd->reserved = 0;
1142
1143 buf_pos += sizeof(struct hifn_crypt_command);
1144
1145 dma->cmdu++;
1146 if (dma->cmdu > 1) {
1147 dev->dmareg |= HIFN_DMAIER_C_WAIT;
1148 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1149 }
1150
1151 if (keylen) {
1152 memcpy(buf_pos, key, keylen);
1153 buf_pos += keylen;
1154 }
1155 if (ivsize) {
1156 memcpy(buf_pos, iv, ivsize);
1157 buf_pos += ivsize;
1158 }
1159
1160 cmd_len = buf_pos - buf;
1161
1162 return cmd_len;
1163}
1164
Patrick McHardy85e7e602008-05-07 22:36:54 +08001165static int hifn_setup_cmd_desc(struct hifn_device *dev,
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001166 struct hifn_context *ctx, struct hifn_request_context *rctx,
1167 void *priv, unsigned int nbytes)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001168{
1169 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1170 int cmd_len, sa_idx;
1171 u8 *buf, *buf_pos;
1172 u16 mask;
1173
Patrick McHardy85e7e602008-05-07 22:36:54 +08001174 sa_idx = dma->cmdi;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001175 buf_pos = buf = dma->command_bufs[dma->cmdi];
1176
1177 mask = 0;
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001178 switch (rctx->op) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001179 case ACRYPTO_OP_DECRYPT:
1180 mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1181 break;
1182 case ACRYPTO_OP_ENCRYPT:
1183 mask = HIFN_BASE_CMD_CRYPT;
1184 break;
1185 case ACRYPTO_OP_HMAC:
1186 mask = HIFN_BASE_CMD_MAC;
1187 break;
1188 default:
1189 goto err_out;
1190 }
1191
1192 buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1193 nbytes, mask, dev->snum);
1194
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001195 if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001196 u16 md = 0;
1197
1198 if (ctx->keysize)
1199 md |= HIFN_CRYPT_CMD_NEW_KEY;
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001200 if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001201 md |= HIFN_CRYPT_CMD_NEW_IV;
1202
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001203 switch (rctx->mode) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001204 case ACRYPTO_MODE_ECB:
1205 md |= HIFN_CRYPT_CMD_MODE_ECB;
1206 break;
1207 case ACRYPTO_MODE_CBC:
1208 md |= HIFN_CRYPT_CMD_MODE_CBC;
1209 break;
1210 case ACRYPTO_MODE_CFB:
1211 md |= HIFN_CRYPT_CMD_MODE_CFB;
1212 break;
1213 case ACRYPTO_MODE_OFB:
1214 md |= HIFN_CRYPT_CMD_MODE_OFB;
1215 break;
1216 default:
1217 goto err_out;
1218 }
1219
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001220 switch (rctx->type) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001221 case ACRYPTO_TYPE_AES_128:
1222 if (ctx->keysize != 16)
1223 goto err_out;
1224 md |= HIFN_CRYPT_CMD_KSZ_128 |
1225 HIFN_CRYPT_CMD_ALG_AES;
1226 break;
1227 case ACRYPTO_TYPE_AES_192:
1228 if (ctx->keysize != 24)
1229 goto err_out;
1230 md |= HIFN_CRYPT_CMD_KSZ_192 |
1231 HIFN_CRYPT_CMD_ALG_AES;
1232 break;
1233 case ACRYPTO_TYPE_AES_256:
1234 if (ctx->keysize != 32)
1235 goto err_out;
1236 md |= HIFN_CRYPT_CMD_KSZ_256 |
1237 HIFN_CRYPT_CMD_ALG_AES;
1238 break;
1239 case ACRYPTO_TYPE_3DES:
1240 if (ctx->keysize != 24)
1241 goto err_out;
1242 md |= HIFN_CRYPT_CMD_ALG_3DES;
1243 break;
1244 case ACRYPTO_TYPE_DES:
1245 if (ctx->keysize != 8)
1246 goto err_out;
1247 md |= HIFN_CRYPT_CMD_ALG_DES;
1248 break;
1249 default:
1250 goto err_out;
1251 }
1252
1253 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1254 nbytes, nbytes, ctx->key, ctx->keysize,
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001255 rctx->iv, rctx->ivsize, md);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001256 }
1257
1258 dev->sa[sa_idx] = priv;
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001259 dev->started++;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001260
1261 cmd_len = buf_pos - buf;
1262 dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1263 HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1264
1265 if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001266 dma->cmdr[dma->cmdi].l = __cpu_to_le32(
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001267 HIFN_D_VALID | HIFN_D_LAST |
1268 HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1269 dma->cmdi = 0;
1270 } else
1271 dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
1272
1273 if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1274 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1275 dev->flags |= HIFN_FLAG_CMD_BUSY;
1276 }
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001277 return 0;
1278
1279err_out:
1280 return -EINVAL;
1281}
1282
Patrick McHardy85e7e602008-05-07 22:36:54 +08001283static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
Patrick McHardy75741a02008-11-24 21:59:25 +08001284 unsigned int offset, unsigned int size, int last)
Patrick McHardy85e7e602008-05-07 22:36:54 +08001285{
1286 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1287 int idx;
1288 dma_addr_t addr;
1289
1290 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1291
1292 idx = dma->srci;
1293
1294 dma->srcr[idx].p = __cpu_to_le32(addr);
1295 dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
Patrick McHardy75741a02008-11-24 21:59:25 +08001296 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
Patrick McHardy85e7e602008-05-07 22:36:54 +08001297
1298 if (++idx == HIFN_D_SRC_RSIZE) {
1299 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
Patrick McHardy75741a02008-11-24 21:59:25 +08001300 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1301 (last ? HIFN_D_LAST : 0));
Patrick McHardy85e7e602008-05-07 22:36:54 +08001302 idx = 0;
1303 }
1304
1305 dma->srci = idx;
1306 dma->srcu++;
1307
1308 if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1309 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1310 dev->flags |= HIFN_FLAG_SRC_BUSY;
1311 }
1312
1313 return size;
1314}
1315
1316static void hifn_setup_res_desc(struct hifn_device *dev)
1317{
1318 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1319
1320 dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1321 HIFN_D_VALID | HIFN_D_LAST);
1322 /*
1323 * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
Patrick McHardy692af5d2008-05-07 22:37:29 +08001324 * HIFN_D_LAST);
Patrick McHardy85e7e602008-05-07 22:36:54 +08001325 */
1326
1327 if (++dma->resi == HIFN_D_RES_RSIZE) {
1328 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1329 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1330 dma->resi = 0;
1331 }
1332
1333 dma->resu++;
1334
1335 if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1336 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1337 dev->flags |= HIFN_FLAG_RES_BUSY;
1338 }
1339}
1340
1341static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
Patrick McHardy75741a02008-11-24 21:59:25 +08001342 unsigned offset, unsigned size, int last)
Patrick McHardy85e7e602008-05-07 22:36:54 +08001343{
1344 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1345 int idx;
1346 dma_addr_t addr;
1347
1348 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1349
1350 idx = dma->dsti;
1351 dma->dstr[idx].p = __cpu_to_le32(addr);
1352 dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
Patrick McHardy75741a02008-11-24 21:59:25 +08001353 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
Patrick McHardy85e7e602008-05-07 22:36:54 +08001354
1355 if (++idx == HIFN_D_DST_RSIZE) {
1356 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1357 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
Patrick McHardy75741a02008-11-24 21:59:25 +08001358 (last ? HIFN_D_LAST : 0));
Patrick McHardy85e7e602008-05-07 22:36:54 +08001359 idx = 0;
1360 }
1361 dma->dsti = idx;
1362 dma->dstu++;
1363
1364 if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1365 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1366 dev->flags |= HIFN_FLAG_DST_BUSY;
1367 }
1368}
1369
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001370static int hifn_setup_dma(struct hifn_device *dev,
1371 struct hifn_context *ctx, struct hifn_request_context *rctx,
Patrick McHardy75741a02008-11-24 21:59:25 +08001372 struct scatterlist *src, struct scatterlist *dst,
1373 unsigned int nbytes, void *priv)
Patrick McHardy85e7e602008-05-07 22:36:54 +08001374{
Patrick McHardy75741a02008-11-24 21:59:25 +08001375 struct scatterlist *t;
1376 struct page *spage, *dpage;
1377 unsigned int soff, doff;
1378 unsigned int n, len;
1379
Patrick McHardy34161582008-11-24 22:00:49 +08001380 n = nbytes;
1381 while (n) {
1382 spage = sg_page(src);
1383 soff = src->offset;
1384 len = min(src->length, n);
1385
Patrick McHardy34161582008-11-24 22:00:49 +08001386 hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);
1387
1388 src++;
1389 n -= len;
1390 }
1391
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001392 t = &rctx->walk.cache[0];
Patrick McHardy75741a02008-11-24 21:59:25 +08001393 n = nbytes;
1394 while (n) {
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001395 if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
Evgeniy Polyakov5f459f02008-11-25 23:17:10 +08001396 BUG_ON(!sg_page(t));
Patrick McHardy34161582008-11-24 22:00:49 +08001397 dpage = sg_page(t);
1398 doff = 0;
Patrick McHardy75741a02008-11-24 21:59:25 +08001399 len = t->length;
1400 } else {
Evgeniy Polyakov5f459f02008-11-25 23:17:10 +08001401 BUG_ON(!sg_page(dst));
Patrick McHardy75741a02008-11-24 21:59:25 +08001402 dpage = sg_page(dst);
1403 doff = dst->offset;
Patrick McHardy75741a02008-11-24 21:59:25 +08001404 len = dst->length;
1405 }
1406 len = min(len, n);
1407
Patrick McHardy75741a02008-11-24 21:59:25 +08001408 hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);
1409
Patrick McHardy75741a02008-11-24 21:59:25 +08001410 dst++;
1411 t++;
1412 n -= len;
1413 }
1414
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001415 hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes);
Patrick McHardy85e7e602008-05-07 22:36:54 +08001416 hifn_setup_res_desc(dev);
1417 return 0;
1418}
1419
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001420static int ablkcipher_walk_init(struct ablkcipher_walk *w,
1421 int num, gfp_t gfp_flags)
1422{
1423 int i;
1424
1425 num = min(ASYNC_SCATTERLIST_CACHE, num);
1426 sg_init_table(w->cache, num);
1427
1428 w->num = 0;
1429 for (i=0; i<num; ++i) {
1430 struct page *page = alloc_page(gfp_flags);
1431 struct scatterlist *s;
1432
1433 if (!page)
1434 break;
1435
1436 s = &w->cache[i];
1437
1438 sg_set_page(s, page, PAGE_SIZE, 0);
1439 w->num++;
1440 }
1441
1442 return i;
1443}
1444
1445static void ablkcipher_walk_exit(struct ablkcipher_walk *w)
1446{
1447 int i;
1448
1449 for (i=0; i<w->num; ++i) {
1450 struct scatterlist *s = &w->cache[i];
1451
1452 __free_page(sg_page(s));
1453
1454 s->length = 0;
1455 }
1456
1457 w->num = 0;
1458}
1459
Patrick McHardy34161582008-11-24 22:00:49 +08001460static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001461 unsigned int size, unsigned int *nbytesp)
1462{
1463 unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1464 int idx = 0;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001465
1466 if (drest < size || size > nbytes)
1467 return -EINVAL;
1468
1469 while (size) {
Patrick McHardy34161582008-11-24 22:00:49 +08001470 copy = min(drest, min(size, dst->length));
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001471
1472 size -= copy;
1473 drest -= copy;
1474 nbytes -= copy;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001475
1476 dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1477 __func__, copy, size, drest, nbytes);
1478
Patrick McHardy34161582008-11-24 22:00:49 +08001479 dst++;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001480 idx++;
1481 }
1482
1483 *nbytesp = nbytes;
1484 *drestp = drest;
1485
1486 return idx;
1487}
1488
1489static int ablkcipher_walk(struct ablkcipher_request *req,
1490 struct ablkcipher_walk *w)
1491{
Patrick McHardy34161582008-11-24 22:00:49 +08001492 struct scatterlist *dst, *t;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001493 unsigned int nbytes = req->nbytes, offset, copy, diff;
1494 int idx, tidx, err;
1495
1496 tidx = idx = 0;
1497 offset = 0;
1498 while (nbytes) {
1499 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1500 return -EINVAL;
1501
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001502 dst = &req->dst[idx];
1503
Patrick McHardy34161582008-11-24 22:00:49 +08001504 dprintk("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
1505 __func__, dst->length, dst->offset, offset, nbytes);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001506
Patrick McHardyd0690332008-05-07 22:33:37 +08001507 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1508 !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
1509 offset) {
Patrick McHardy34161582008-11-24 22:00:49 +08001510 unsigned slen = min(dst->length - offset, nbytes);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001511 unsigned dlen = PAGE_SIZE;
1512
1513 t = &w->cache[idx];
1514
Patrick McHardy34161582008-11-24 22:00:49 +08001515 err = ablkcipher_add(&dlen, dst, slen, &nbytes);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001516 if (err < 0)
Patrick McHardy34161582008-11-24 22:00:49 +08001517 return err;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001518
1519 idx += err;
1520
Patrick McHardyd0690332008-05-07 22:33:37 +08001521 copy = slen & ~(HIFN_D_DST_DALIGN - 1);
1522 diff = slen & (HIFN_D_DST_DALIGN - 1);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001523
1524 if (dlen < nbytes) {
1525 /*
1526 * Destination page does not have enough space
1527 * to put there additional blocksized chunk,
1528 * so we mark that page as containing only
1529 * blocksize aligned chunks:
Patrick McHardyd0690332008-05-07 22:33:37 +08001530 * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001531 * and increase number of bytes to be processed
1532 * in next chunk:
1533 * nbytes += diff;
1534 */
1535 nbytes += diff;
1536
1537 /*
1538 * Temporary of course...
1539 * Kick author if you will catch this one.
1540 */
1541 printk(KERN_ERR "%s: dlen: %u, nbytes: %u,"
1542 "slen: %u, offset: %u.\n",
1543 __func__, dlen, nbytes, slen, offset);
1544 printk(KERN_ERR "%s: please contact author to fix this "
1545 "issue, generally you should not catch "
1546 "this path under any condition but who "
1547 "knows how did you use crypto code.\n"
1548 "Thank you.\n", __func__);
1549 BUG();
1550 } else {
1551 copy += diff + nbytes;
1552
Patrick McHardy34161582008-11-24 22:00:49 +08001553 dst = &req->dst[idx];
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001554
Patrick McHardy34161582008-11-24 22:00:49 +08001555 err = ablkcipher_add(&dlen, dst, nbytes, &nbytes);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001556 if (err < 0)
Patrick McHardy34161582008-11-24 22:00:49 +08001557 return err;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001558
1559 idx += err;
1560 }
1561
1562 t->length = copy;
1563 t->offset = offset;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001564 } else {
Patrick McHardy34161582008-11-24 22:00:49 +08001565 nbytes -= min(dst->length, nbytes);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001566 idx++;
1567 }
1568
1569 tidx++;
1570 }
1571
1572 return tidx;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001573}
1574
1575static int hifn_setup_session(struct ablkcipher_request *req)
1576{
1577 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001578 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001579 struct hifn_device *dev = ctx->dev;
Patrick McHardy75741a02008-11-24 21:59:25 +08001580 unsigned long dlen, flags;
1581 unsigned int nbytes = req->nbytes, idx = 0;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001582 int err = -EINVAL, sg_num;
Patrick McHardy75741a02008-11-24 21:59:25 +08001583 struct scatterlist *dst;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001584
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001585 if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001586 goto err_out_exit;
1587
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001588 rctx->walk.flags = 0;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001589
1590 while (nbytes) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001591 dst = &req->dst[idx];
Patrick McHardy136f7022008-05-07 22:34:27 +08001592 dlen = min(dst->length, nbytes);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001593
Patrick McHardyd0690332008-05-07 22:33:37 +08001594 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
Patrick McHardy136f7022008-05-07 22:34:27 +08001595 !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001596 rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001597
Patrick McHardy136f7022008-05-07 22:34:27 +08001598 nbytes -= dlen;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001599 idx++;
1600 }
1601
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001602 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1603 err = ablkcipher_walk_init(&rctx->walk, idx, GFP_ATOMIC);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001604 if (err < 0)
1605 return err;
1606 }
1607
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001608 sg_num = ablkcipher_walk(req, &rctx->walk);
Patrick McHardy94eaa1b2008-05-07 22:32:28 +08001609 if (sg_num < 0) {
1610 err = sg_num;
1611 goto err_out_exit;
1612 }
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001613
1614 spin_lock_irqsave(&dev->lock, flags);
1615 if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1616 err = -EAGAIN;
1617 goto err_out;
1618 }
1619
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001620 err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req);
Patrick McHardy75741a02008-11-24 21:59:25 +08001621 if (err)
1622 goto err_out;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001623
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001624 dev->snum++;
1625
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001626 dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1627 spin_unlock_irqrestore(&dev->lock, flags);
1628
1629 return 0;
1630
1631err_out:
1632 spin_unlock_irqrestore(&dev->lock, flags);
1633err_out_exit:
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001634 if (err) {
1635 printk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001636 "type: %u, err: %d.\n",
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001637 dev->name, rctx->iv, rctx->ivsize,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001638 ctx->key, ctx->keysize,
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001639 rctx->mode, rctx->op, rctx->type, err);
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001640 }
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001641
1642 return err;
1643}
1644
1645static int hifn_test(struct hifn_device *dev, int encdec, u8 snum)
1646{
1647 int n, err;
1648 u8 src[16];
1649 struct hifn_context ctx;
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001650 struct hifn_request_context rctx;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001651 u8 fips_aes_ecb_from_zero[16] = {
1652 0x66, 0xE9, 0x4B, 0xD4,
1653 0xEF, 0x8A, 0x2C, 0x3B,
1654 0x88, 0x4C, 0xFA, 0x59,
1655 0xCA, 0x34, 0x2B, 0x2E};
Patrick McHardy75741a02008-11-24 21:59:25 +08001656 struct scatterlist sg;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001657
1658 memset(src, 0, sizeof(src));
1659 memset(ctx.key, 0, sizeof(ctx.key));
1660
1661 ctx.dev = dev;
1662 ctx.keysize = 16;
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001663 rctx.ivsize = 0;
1664 rctx.iv = NULL;
1665 rctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT;
1666 rctx.mode = ACRYPTO_MODE_ECB;
1667 rctx.type = ACRYPTO_TYPE_AES_128;
1668 rctx.walk.cache[0].length = 0;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001669
Patrick McHardy75741a02008-11-24 21:59:25 +08001670 sg_init_one(&sg, &src, sizeof(src));
1671
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001672 err = hifn_setup_dma(dev, &ctx, &rctx, &sg, &sg, sizeof(src), NULL);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001673 if (err)
1674 goto err_out;
1675
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001676 dev->started = 0;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001677 msleep(200);
1678
1679 dprintk("%s: decoded: ", dev->name);
1680 for (n=0; n<sizeof(src); ++n)
1681 dprintk("%02x ", src[n]);
1682 dprintk("\n");
1683 dprintk("%s: FIPS : ", dev->name);
1684 for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n)
1685 dprintk("%02x ", fips_aes_ecb_from_zero[n]);
1686 dprintk("\n");
1687
1688 if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) {
1689 printk(KERN_INFO "%s: AES 128 ECB test has been successfully "
1690 "passed.\n", dev->name);
1691 return 0;
1692 }
1693
1694err_out:
1695 printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name);
1696 return -1;
1697}
1698
1699static int hifn_start_device(struct hifn_device *dev)
1700{
1701 int err;
1702
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001703 dev->started = dev->active = 0;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001704 hifn_reset_dma(dev, 1);
1705
1706 err = hifn_enable_crypto(dev);
1707 if (err)
1708 return err;
1709
1710 hifn_reset_puc(dev);
1711
1712 hifn_init_dma(dev);
1713
1714 hifn_init_registers(dev);
1715
1716 hifn_init_pubrng(dev);
1717
1718 return 0;
1719}
1720
1721static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1722 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1723{
1724 unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1725 void *daddr;
1726 int idx = 0;
1727
1728 if (srest < size || size > nbytes)
1729 return -EINVAL;
1730
1731 while (size) {
Patrick McHardy136f7022008-05-07 22:34:27 +08001732 copy = min(srest, min(dst->length, size));
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001733
1734 daddr = kmap_atomic(sg_page(dst), KM_IRQ0);
1735 memcpy(daddr + dst->offset + offset, saddr, copy);
1736 kunmap_atomic(daddr, KM_IRQ0);
1737
1738 nbytes -= copy;
1739 size -= copy;
1740 srest -= copy;
1741 saddr += copy;
1742 offset = 0;
1743
1744 dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1745 __func__, copy, size, srest, nbytes);
1746
1747 dst++;
1748 idx++;
1749 }
1750
1751 *nbytesp = nbytes;
1752 *srestp = srest;
1753
1754 return idx;
1755}
1756
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001757static inline void hifn_complete_sa(struct hifn_device *dev, int i)
1758{
1759 unsigned long flags;
1760
1761 spin_lock_irqsave(&dev->lock, flags);
1762 dev->sa[i] = NULL;
1763 dev->started--;
1764 if (dev->started < 0)
1765 printk("%s: started: %d.\n", __func__, dev->started);
1766 spin_unlock_irqrestore(&dev->lock, flags);
1767 BUG_ON(dev->started < 0);
1768}
1769
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001770static void hifn_process_ready(struct ablkcipher_request *req, int error)
1771{
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001772 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001773
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001774 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001775 unsigned int nbytes = req->nbytes;
1776 int idx = 0, err;
1777 struct scatterlist *dst, *t;
1778 void *saddr;
1779
Patrick McHardy75741a02008-11-24 21:59:25 +08001780 while (nbytes) {
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001781 t = &rctx->walk.cache[idx];
Patrick McHardy75741a02008-11-24 21:59:25 +08001782 dst = &req->dst[idx];
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001783
Patrick McHardy75741a02008-11-24 21:59:25 +08001784 dprintk("\n%s: sg_page(t): %p, t->length: %u, "
1785 "sg_page(dst): %p, dst->length: %u, "
1786 "nbytes: %u.\n",
1787 __func__, sg_page(t), t->length,
1788 sg_page(dst), dst->length, nbytes);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001789
Patrick McHardy75741a02008-11-24 21:59:25 +08001790 if (!t->length) {
1791 nbytes -= min(dst->length, nbytes);
1792 idx++;
1793 continue;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001794 }
1795
Evgeniy Polyakov5f459f02008-11-25 23:17:10 +08001796 saddr = kmap_atomic(sg_page(t), KM_SOFTIRQ0);
Patrick McHardy75741a02008-11-24 21:59:25 +08001797
1798 err = ablkcipher_get(saddr, &t->length, t->offset,
1799 dst, nbytes, &nbytes);
1800 if (err < 0) {
Evgeniy Polyakov5f459f02008-11-25 23:17:10 +08001801 kunmap_atomic(saddr, KM_SOFTIRQ0);
Patrick McHardy75741a02008-11-24 21:59:25 +08001802 break;
1803 }
1804
1805 idx += err;
Evgeniy Polyakov5f459f02008-11-25 23:17:10 +08001806 kunmap_atomic(saddr, KM_SOFTIRQ0);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001807 }
1808
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08001809 ablkcipher_walk_exit(&rctx->walk);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001810 }
Patrick McHardy75741a02008-11-24 21:59:25 +08001811
1812 req->base.complete(&req->base, error);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001813}
1814
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001815static void hifn_clear_rings(struct hifn_device *dev, int error)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001816{
1817 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1818 int i, u;
1819
1820 dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1821 "k: %d.%d.%d.%d.\n",
1822 dev->name,
1823 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1824 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1825 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1826
1827 i = dma->resk; u = dma->resu;
1828 while (u != 0) {
1829 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1830 break;
1831
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001832 if (dev->sa[i]) {
1833 dev->success++;
1834 dev->reset = 0;
1835 hifn_process_ready(dev->sa[i], error);
1836 hifn_complete_sa(dev, i);
1837 }
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001838
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001839 if (++i == HIFN_D_RES_RSIZE)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001840 i = 0;
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001841 u--;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001842 }
1843 dma->resk = i; dma->resu = u;
1844
1845 i = dma->srck; u = dma->srcu;
1846 while (u != 0) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001847 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1848 break;
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001849 if (++i == HIFN_D_SRC_RSIZE)
1850 i = 0;
1851 u--;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001852 }
1853 dma->srck = i; dma->srcu = u;
1854
1855 i = dma->cmdk; u = dma->cmdu;
1856 while (u != 0) {
1857 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1858 break;
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001859 if (++i == HIFN_D_CMD_RSIZE)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001860 i = 0;
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001861 u--;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001862 }
1863 dma->cmdk = i; dma->cmdu = u;
1864
1865 i = dma->dstk; u = dma->dstu;
1866 while (u != 0) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001867 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1868 break;
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001869 if (++i == HIFN_D_DST_RSIZE)
1870 i = 0;
1871 u--;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001872 }
1873 dma->dstk = i; dma->dstu = u;
1874
1875 dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1876 "k: %d.%d.%d.%d.\n",
1877 dev->name,
1878 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1879 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1880 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1881}
1882
1883static void hifn_work(struct work_struct *work)
1884{
Jean Delvarebf6aede2009-04-02 16:56:54 -07001885 struct delayed_work *dw = to_delayed_work(work);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001886 struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1887 unsigned long flags;
1888 int reset = 0;
1889 u32 r = 0;
1890
1891 spin_lock_irqsave(&dev->lock, flags);
1892 if (dev->active == 0) {
1893 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1894
1895 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1896 dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1897 r |= HIFN_DMACSR_C_CTRL_DIS;
1898 }
1899 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1900 dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1901 r |= HIFN_DMACSR_S_CTRL_DIS;
1902 }
1903 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1904 dev->flags &= ~HIFN_FLAG_DST_BUSY;
1905 r |= HIFN_DMACSR_D_CTRL_DIS;
1906 }
1907 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1908 dev->flags &= ~HIFN_FLAG_RES_BUSY;
1909 r |= HIFN_DMACSR_R_CTRL_DIS;
1910 }
1911 if (r)
1912 hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1913 } else
1914 dev->active--;
1915
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001916 if ((dev->prev_success == dev->success) && dev->started)
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001917 reset = 1;
1918 dev->prev_success = dev->success;
1919 spin_unlock_irqrestore(&dev->lock, flags);
1920
1921 if (reset) {
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001922 if (++dev->reset >= 5) {
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001923 int i;
1924 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1925
1926 printk("%s: r: %08x, active: %d, started: %d, "
1927 "success: %lu: qlen: %u/%u, reset: %d.\n",
1928 dev->name, r, dev->active, dev->started,
1929 dev->success, dev->queue.qlen, dev->queue.max_qlen,
1930 reset);
1931
1932 printk("%s: res: ", __func__);
1933 for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1934 printk("%x.%p ", dma->resr[i].l, dev->sa[i]);
1935 if (dev->sa[i]) {
1936 hifn_process_ready(dev->sa[i], -ENODEV);
1937 hifn_complete_sa(dev, i);
1938 }
1939 }
1940 printk("\n");
1941
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001942 hifn_reset_dma(dev, 1);
1943 hifn_stop_device(dev);
1944 hifn_start_device(dev);
1945 dev->reset = 0;
1946 }
1947
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001948 tasklet_schedule(&dev->tasklet);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001949 }
1950
1951 schedule_delayed_work(&dev->work, HZ);
1952}
1953
1954static irqreturn_t hifn_interrupt(int irq, void *data)
1955{
1956 struct hifn_device *dev = (struct hifn_device *)data;
1957 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1958 u32 dmacsr, restart;
1959
1960 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1961
1962 dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1963 "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1964 dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001965 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1966 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001967
1968 if ((dmacsr & dev->dmareg) == 0)
1969 return IRQ_NONE;
1970
1971 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1972
1973 if (dmacsr & HIFN_DMACSR_ENGINE)
1974 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1975 if (dmacsr & HIFN_DMACSR_PUBDONE)
1976 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1977 hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1978
1979 restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1980 if (restart) {
1981 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1982
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001983 printk(KERN_WARNING "%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1984 dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER),
1985 !!(dmacsr & HIFN_DMACSR_D_OVER),
1986 puisr, !!(puisr & HIFN_PUISR_DSTOVER));
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08001987 if (!!(puisr & HIFN_PUISR_DSTOVER))
1988 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1989 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1990 HIFN_DMACSR_D_OVER));
1991 }
1992
1993 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1994 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1995 if (restart) {
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08001996 printk(KERN_WARNING "%s: abort: c: %d, s: %d, d: %d, r: %d.\n",
1997 dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT),
1998 !!(dmacsr & HIFN_DMACSR_S_ABORT),
1999 !!(dmacsr & HIFN_DMACSR_D_ABORT),
2000 !!(dmacsr & HIFN_DMACSR_R_ABORT));
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002001 hifn_reset_dma(dev, 1);
2002 hifn_init_dma(dev);
2003 hifn_init_registers(dev);
2004 }
2005
2006 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2007 dprintk("%s: wait on command.\n", dev->name);
2008 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
2009 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
2010 }
2011
Evgeniy Polyakova1e6ef22007-11-10 20:24:18 +08002012 tasklet_schedule(&dev->tasklet);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002013
2014 return IRQ_HANDLED;
2015}
2016
2017static void hifn_flush(struct hifn_device *dev)
2018{
2019 unsigned long flags;
2020 struct crypto_async_request *async_req;
2021 struct hifn_context *ctx;
2022 struct ablkcipher_request *req;
2023 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
2024 int i;
2025
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002026 for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
2027 struct hifn_desc *d = &dma->resr[i];
2028
2029 if (dev->sa[i]) {
2030 hifn_process_ready(dev->sa[i],
2031 (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0);
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08002032 hifn_complete_sa(dev, i);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002033 }
2034 }
2035
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08002036 spin_lock_irqsave(&dev->lock, flags);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002037 while ((async_req = crypto_dequeue_request(&dev->queue))) {
2038 ctx = crypto_tfm_ctx(async_req->tfm);
2039 req = container_of(async_req, struct ablkcipher_request, base);
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08002040 spin_unlock_irqrestore(&dev->lock, flags);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002041
2042 hifn_process_ready(req, -ENODEV);
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08002043
2044 spin_lock_irqsave(&dev->lock, flags);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002045 }
2046 spin_unlock_irqrestore(&dev->lock, flags);
2047}
2048
2049static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
2050 unsigned int len)
2051{
2052 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
2053 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2054 struct hifn_device *dev = ctx->dev;
2055
2056 if (len > HIFN_MAX_CRYPT_KEY_LENGTH) {
2057 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
2058 return -1;
2059 }
2060
Evgeniy Polyakovc3041f92007-10-11 19:58:16 +08002061 if (len == HIFN_DES_KEY_LENGTH) {
2062 u32 tmp[DES_EXPKEY_WORDS];
2063 int ret = des_ekey(tmp, key);
2064
2065 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
2066 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
2067 return -EINVAL;
2068 }
2069 }
2070
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002071 dev->flags &= ~HIFN_FLAG_OLD_KEY;
2072
2073 memcpy(ctx->key, key, len);
2074 ctx->keysize = len;
2075
2076 return 0;
2077}
2078
2079static int hifn_handle_req(struct ablkcipher_request *req)
2080{
2081 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2082 struct hifn_device *dev = ctx->dev;
2083 int err = -EAGAIN;
2084
2085 if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
2086 err = hifn_setup_session(req);
2087
2088 if (err == -EAGAIN) {
2089 unsigned long flags;
2090
2091 spin_lock_irqsave(&dev->lock, flags);
2092 err = ablkcipher_enqueue_request(&dev->queue, req);
2093 spin_unlock_irqrestore(&dev->lock, flags);
2094 }
2095
2096 return err;
2097}
2098
2099static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
2100 u8 type, u8 mode)
2101{
2102 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08002103 struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002104 unsigned ivsize;
2105
2106 ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
2107
2108 if (req->info && mode != ACRYPTO_MODE_ECB) {
2109 if (type == ACRYPTO_TYPE_AES_128)
2110 ivsize = HIFN_AES_IV_LENGTH;
2111 else if (type == ACRYPTO_TYPE_DES)
2112 ivsize = HIFN_DES_KEY_LENGTH;
2113 else if (type == ACRYPTO_TYPE_3DES)
2114 ivsize = HIFN_3DES_KEY_LENGTH;
2115 }
2116
2117 if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
2118 if (ctx->keysize == 24)
2119 type = ACRYPTO_TYPE_AES_192;
2120 else if (ctx->keysize == 32)
2121 type = ACRYPTO_TYPE_AES_256;
2122 }
2123
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08002124 rctx->op = op;
2125 rctx->mode = mode;
2126 rctx->type = type;
2127 rctx->iv = req->info;
2128 rctx->ivsize = ivsize;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002129
2130 /*
2131 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2132 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2133 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2134 */
2135
2136 return hifn_handle_req(req);
2137}
2138
2139static int hifn_process_queue(struct hifn_device *dev)
2140{
Patrick McHardyed4f92e2008-11-24 22:02:55 +08002141 struct crypto_async_request *async_req, *backlog;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002142 struct hifn_context *ctx;
2143 struct ablkcipher_request *req;
2144 unsigned long flags;
2145 int err = 0;
2146
2147 while (dev->started < HIFN_QUEUE_LENGTH) {
2148 spin_lock_irqsave(&dev->lock, flags);
Patrick McHardyed4f92e2008-11-24 22:02:55 +08002149 backlog = crypto_get_backlog(&dev->queue);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002150 async_req = crypto_dequeue_request(&dev->queue);
2151 spin_unlock_irqrestore(&dev->lock, flags);
2152
2153 if (!async_req)
2154 break;
2155
Patrick McHardyed4f92e2008-11-24 22:02:55 +08002156 if (backlog)
2157 backlog->complete(backlog, -EINPROGRESS);
2158
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002159 ctx = crypto_tfm_ctx(async_req->tfm);
2160 req = container_of(async_req, struct ablkcipher_request, base);
2161
2162 err = hifn_handle_req(req);
2163 if (err)
2164 break;
2165 }
2166
2167 return err;
2168}
2169
2170static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2171 u8 type, u8 mode)
2172{
2173 int err;
2174 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2175 struct hifn_device *dev = ctx->dev;
2176
2177 err = hifn_setup_crypto_req(req, op, type, mode);
2178 if (err)
2179 return err;
2180
2181 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
Patrick McHardy9e70a402008-05-07 22:31:35 +08002182 hifn_process_queue(dev);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002183
Patrick McHardy9e70a402008-05-07 22:31:35 +08002184 return -EINPROGRESS;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002185}
2186
2187/*
2188 * AES ecryption functions.
2189 */
2190static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2191{
2192 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2193 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2194}
2195static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2196{
2197 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2198 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2199}
2200static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2201{
2202 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2203 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2204}
2205static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2206{
2207 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2208 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2209}
2210
2211/*
2212 * AES decryption functions.
2213 */
2214static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2215{
2216 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2217 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2218}
2219static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2220{
2221 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2222 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2223}
2224static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2225{
2226 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2227 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2228}
2229static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2230{
2231 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2232 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2233}
2234
2235/*
2236 * DES ecryption functions.
2237 */
2238static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2239{
2240 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2241 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2242}
2243static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2244{
2245 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2246 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2247}
2248static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2249{
2250 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2251 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2252}
2253static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2254{
2255 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2256 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2257}
2258
2259/*
2260 * DES decryption functions.
2261 */
2262static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2263{
2264 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2265 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2266}
2267static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2268{
2269 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2270 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2271}
2272static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2273{
2274 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2275 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2276}
2277static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2278{
2279 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2280 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2281}
2282
2283/*
2284 * 3DES ecryption functions.
2285 */
2286static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2287{
2288 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2289 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2290}
2291static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2292{
2293 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2294 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2295}
2296static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2297{
2298 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2299 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2300}
2301static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2302{
2303 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2304 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2305}
2306
2307/*
2308 * 3DES decryption functions.
2309 */
2310static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2311{
2312 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2313 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2314}
2315static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2316{
2317 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2318 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2319}
2320static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2321{
2322 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2323 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2324}
2325static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2326{
2327 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2328 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2329}
2330
2331struct hifn_alg_template
2332{
2333 char name[CRYPTO_MAX_ALG_NAME];
2334 char drv_name[CRYPTO_MAX_ALG_NAME];
2335 unsigned int bsize;
2336 struct ablkcipher_alg ablkcipher;
2337};
2338
2339static struct hifn_alg_template hifn_alg_templates[] = {
2340 /*
2341 * 3DES ECB, CBC, CFB and OFB modes.
2342 */
2343 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002344 .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002345 .ablkcipher = {
2346 .min_keysize = HIFN_3DES_KEY_LENGTH,
2347 .max_keysize = HIFN_3DES_KEY_LENGTH,
2348 .setkey = hifn_setkey,
2349 .encrypt = hifn_encrypt_3des_cfb,
2350 .decrypt = hifn_decrypt_3des_cfb,
2351 },
2352 },
2353 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002354 .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002355 .ablkcipher = {
2356 .min_keysize = HIFN_3DES_KEY_LENGTH,
2357 .max_keysize = HIFN_3DES_KEY_LENGTH,
2358 .setkey = hifn_setkey,
2359 .encrypt = hifn_encrypt_3des_ofb,
2360 .decrypt = hifn_decrypt_3des_ofb,
2361 },
2362 },
2363 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002364 .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002365 .ablkcipher = {
Patrick McHardy4b804b52008-05-07 22:35:47 +08002366 .ivsize = HIFN_IV_LENGTH,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002367 .min_keysize = HIFN_3DES_KEY_LENGTH,
2368 .max_keysize = HIFN_3DES_KEY_LENGTH,
2369 .setkey = hifn_setkey,
2370 .encrypt = hifn_encrypt_3des_cbc,
2371 .decrypt = hifn_decrypt_3des_cbc,
2372 },
2373 },
2374 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002375 .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002376 .ablkcipher = {
2377 .min_keysize = HIFN_3DES_KEY_LENGTH,
2378 .max_keysize = HIFN_3DES_KEY_LENGTH,
2379 .setkey = hifn_setkey,
2380 .encrypt = hifn_encrypt_3des_ecb,
2381 .decrypt = hifn_decrypt_3des_ecb,
2382 },
2383 },
2384
2385 /*
2386 * DES ECB, CBC, CFB and OFB modes.
2387 */
2388 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002389 .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002390 .ablkcipher = {
2391 .min_keysize = HIFN_DES_KEY_LENGTH,
2392 .max_keysize = HIFN_DES_KEY_LENGTH,
2393 .setkey = hifn_setkey,
2394 .encrypt = hifn_encrypt_des_cfb,
2395 .decrypt = hifn_decrypt_des_cfb,
2396 },
2397 },
2398 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002399 .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002400 .ablkcipher = {
2401 .min_keysize = HIFN_DES_KEY_LENGTH,
2402 .max_keysize = HIFN_DES_KEY_LENGTH,
2403 .setkey = hifn_setkey,
2404 .encrypt = hifn_encrypt_des_ofb,
2405 .decrypt = hifn_decrypt_des_ofb,
2406 },
2407 },
2408 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002409 .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002410 .ablkcipher = {
Patrick McHardy4b804b52008-05-07 22:35:47 +08002411 .ivsize = HIFN_IV_LENGTH,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002412 .min_keysize = HIFN_DES_KEY_LENGTH,
2413 .max_keysize = HIFN_DES_KEY_LENGTH,
2414 .setkey = hifn_setkey,
2415 .encrypt = hifn_encrypt_des_cbc,
2416 .decrypt = hifn_decrypt_des_cbc,
2417 },
2418 },
2419 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002420 .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002421 .ablkcipher = {
2422 .min_keysize = HIFN_DES_KEY_LENGTH,
2423 .max_keysize = HIFN_DES_KEY_LENGTH,
2424 .setkey = hifn_setkey,
2425 .encrypt = hifn_encrypt_des_ecb,
2426 .decrypt = hifn_decrypt_des_ecb,
2427 },
2428 },
2429
2430 /*
2431 * AES ECB, CBC, CFB and OFB modes.
2432 */
2433 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002434 .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002435 .ablkcipher = {
2436 .min_keysize = AES_MIN_KEY_SIZE,
2437 .max_keysize = AES_MAX_KEY_SIZE,
2438 .setkey = hifn_setkey,
2439 .encrypt = hifn_encrypt_aes_ecb,
2440 .decrypt = hifn_decrypt_aes_ecb,
2441 },
2442 },
2443 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002444 .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002445 .ablkcipher = {
Patrick McHardy4b804b52008-05-07 22:35:47 +08002446 .ivsize = HIFN_AES_IV_LENGTH,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002447 .min_keysize = AES_MIN_KEY_SIZE,
2448 .max_keysize = AES_MAX_KEY_SIZE,
2449 .setkey = hifn_setkey,
2450 .encrypt = hifn_encrypt_aes_cbc,
2451 .decrypt = hifn_decrypt_aes_cbc,
2452 },
2453 },
2454 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002455 .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002456 .ablkcipher = {
2457 .min_keysize = AES_MIN_KEY_SIZE,
2458 .max_keysize = AES_MAX_KEY_SIZE,
2459 .setkey = hifn_setkey,
2460 .encrypt = hifn_encrypt_aes_cfb,
2461 .decrypt = hifn_decrypt_aes_cfb,
2462 },
2463 },
2464 {
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002465 .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002466 .ablkcipher = {
2467 .min_keysize = AES_MIN_KEY_SIZE,
2468 .max_keysize = AES_MAX_KEY_SIZE,
2469 .setkey = hifn_setkey,
2470 .encrypt = hifn_encrypt_aes_ofb,
2471 .decrypt = hifn_decrypt_aes_ofb,
2472 },
2473 },
2474};
2475
2476static int hifn_cra_init(struct crypto_tfm *tfm)
2477{
2478 struct crypto_alg *alg = tfm->__crt_alg;
2479 struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2480 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2481
2482 ctx->dev = ha->dev;
Patrick McHardy5df4c0c2008-11-24 22:01:42 +08002483 tfm->crt_ablkcipher.reqsize = sizeof(struct hifn_request_context);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002484 return 0;
2485}
2486
2487static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2488{
2489 struct hifn_crypto_alg *alg;
2490 int err;
2491
2492 alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL);
2493 if (!alg)
2494 return -ENOMEM;
2495
2496 snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
Patrick McHardy281d6bd2008-05-07 22:35:07 +08002497 snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s",
2498 t->drv_name, dev->name);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002499
2500 alg->alg.cra_priority = 300;
Herbert Xu332f88402007-11-15 22:36:07 +08002501 alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002502 alg->alg.cra_blocksize = t->bsize;
2503 alg->alg.cra_ctxsize = sizeof(struct hifn_context);
Patrick McHardyd0690332008-05-07 22:33:37 +08002504 alg->alg.cra_alignmask = 0;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002505 alg->alg.cra_type = &crypto_ablkcipher_type;
2506 alg->alg.cra_module = THIS_MODULE;
2507 alg->alg.cra_u.ablkcipher = t->ablkcipher;
2508 alg->alg.cra_init = hifn_cra_init;
2509
2510 alg->dev = dev;
2511
2512 list_add_tail(&alg->entry, &dev->alg_list);
2513
2514 err = crypto_register_alg(&alg->alg);
2515 if (err) {
2516 list_del(&alg->entry);
2517 kfree(alg);
2518 }
2519
2520 return err;
2521}
2522
2523static void hifn_unregister_alg(struct hifn_device *dev)
2524{
2525 struct hifn_crypto_alg *a, *n;
2526
2527 list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2528 list_del(&a->entry);
2529 crypto_unregister_alg(&a->alg);
2530 kfree(a);
2531 }
2532}
2533
2534static int hifn_register_alg(struct hifn_device *dev)
2535{
2536 int i, err;
2537
2538 for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) {
2539 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2540 if (err)
2541 goto err_out_exit;
2542 }
2543
2544 return 0;
2545
2546err_out_exit:
2547 hifn_unregister_alg(dev);
2548 return err;
2549}
2550
Evgeniy Polyakova1e6ef22007-11-10 20:24:18 +08002551static void hifn_tasklet_callback(unsigned long data)
2552{
2553 struct hifn_device *dev = (struct hifn_device *)data;
2554
2555 /*
2556 * This is ok to call this without lock being held,
2557 * althogh it modifies some parameters used in parallel,
2558 * (like dev->success), but they are used in process
2559 * context or update is atomic (like setting dev->sa[i] to NULL).
2560 */
Evgeniy Polyakovd6a10c82008-11-24 22:04:39 +08002561 hifn_clear_rings(dev, 0);
Patrick McHardyed4f92e2008-11-24 22:02:55 +08002562
2563 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2564 hifn_process_queue(dev);
Evgeniy Polyakova1e6ef22007-11-10 20:24:18 +08002565}
2566
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002567static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2568{
2569 int err, i;
2570 struct hifn_device *dev;
2571 char name[8];
2572
2573 err = pci_enable_device(pdev);
2574 if (err)
2575 return err;
2576 pci_set_master(pdev);
2577
Yang Hongyang284901a2009-04-06 19:01:15 -07002578 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002579 if (err)
2580 goto err_out_disable_pci_device;
2581
2582 snprintf(name, sizeof(name), "hifn%d",
2583 atomic_inc_return(&hifn_dev_number)-1);
2584
2585 err = pci_request_regions(pdev, name);
2586 if (err)
2587 goto err_out_disable_pci_device;
2588
2589 if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2590 pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2591 pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2592 dprintk("%s: Broken hardware - I/O regions are too small.\n",
2593 pci_name(pdev));
2594 err = -ENODEV;
2595 goto err_out_free_regions;
2596 }
2597
2598 dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2599 GFP_KERNEL);
2600 if (!dev) {
2601 err = -ENOMEM;
2602 goto err_out_free_regions;
2603 }
2604
2605 INIT_LIST_HEAD(&dev->alg_list);
2606
2607 snprintf(dev->name, sizeof(dev->name), "%s", name);
2608 spin_lock_init(&dev->lock);
2609
2610 for (i=0; i<3; ++i) {
2611 unsigned long addr, size;
2612
2613 addr = pci_resource_start(pdev, i);
2614 size = pci_resource_len(pdev, i);
2615
2616 dev->bar[i] = ioremap_nocache(addr, size);
2617 if (!dev->bar[i])
2618 goto err_out_unmap_bars;
2619 }
2620
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002621 dev->desc_virt = pci_alloc_consistent(pdev, sizeof(struct hifn_dma),
2622 &dev->desc_dma);
2623 if (!dev->desc_virt) {
2624 dprintk("Failed to allocate descriptor rings.\n");
Patrick McHardy3ec858d2008-11-24 22:03:37 +08002625 goto err_out_unmap_bars;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002626 }
2627 memset(dev->desc_virt, 0, sizeof(struct hifn_dma));
2628
2629 dev->pdev = pdev;
2630 dev->irq = pdev->irq;
2631
2632 for (i=0; i<HIFN_D_RES_RSIZE; ++i)
2633 dev->sa[i] = NULL;
2634
2635 pci_set_drvdata(pdev, dev);
2636
Evgeniy Polyakova1e6ef22007-11-10 20:24:18 +08002637 tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2638
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002639 crypto_init_queue(&dev->queue, 1);
2640
2641 err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2642 if (err) {
2643 dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err);
2644 dev->irq = 0;
2645 goto err_out_free_desc;
2646 }
2647
2648 err = hifn_start_device(dev);
2649 if (err)
2650 goto err_out_free_irq;
2651
2652 err = hifn_test(dev, 1, 0);
2653 if (err)
2654 goto err_out_stop_device;
2655
Patrick McHardyfcd06752007-11-21 12:51:52 +08002656 err = hifn_register_rng(dev);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002657 if (err)
2658 goto err_out_stop_device;
2659
Patrick McHardyfcd06752007-11-21 12:51:52 +08002660 err = hifn_register_alg(dev);
2661 if (err)
2662 goto err_out_unregister_rng;
2663
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002664 INIT_DELAYED_WORK(&dev->work, hifn_work);
2665 schedule_delayed_work(&dev->work, HZ);
2666
2667 dprintk("HIFN crypto accelerator card at %s has been "
2668 "successfully registered as %s.\n",
2669 pci_name(pdev), dev->name);
2670
2671 return 0;
2672
Patrick McHardyfcd06752007-11-21 12:51:52 +08002673err_out_unregister_rng:
2674 hifn_unregister_rng(dev);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002675err_out_stop_device:
2676 hifn_reset_dma(dev, 1);
2677 hifn_stop_device(dev);
2678err_out_free_irq:
2679 free_irq(dev->irq, dev->name);
Evgeniy Polyakova1e6ef22007-11-10 20:24:18 +08002680 tasklet_kill(&dev->tasklet);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002681err_out_free_desc:
2682 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2683 dev->desc_virt, dev->desc_dma);
2684
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002685err_out_unmap_bars:
2686 for (i=0; i<3; ++i)
2687 if (dev->bar[i])
2688 iounmap(dev->bar[i]);
2689
2690err_out_free_regions:
2691 pci_release_regions(pdev);
2692
2693err_out_disable_pci_device:
2694 pci_disable_device(pdev);
2695
2696 return err;
2697}
2698
2699static void hifn_remove(struct pci_dev *pdev)
2700{
2701 int i;
2702 struct hifn_device *dev;
2703
2704 dev = pci_get_drvdata(pdev);
2705
2706 if (dev) {
2707 cancel_delayed_work(&dev->work);
2708 flush_scheduled_work();
2709
Patrick McHardyfcd06752007-11-21 12:51:52 +08002710 hifn_unregister_rng(dev);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002711 hifn_unregister_alg(dev);
2712 hifn_reset_dma(dev, 1);
2713 hifn_stop_device(dev);
2714
2715 free_irq(dev->irq, dev->name);
Evgeniy Polyakova1e6ef22007-11-10 20:24:18 +08002716 tasklet_kill(&dev->tasklet);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002717
2718 hifn_flush(dev);
2719
2720 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2721 dev->desc_virt, dev->desc_dma);
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002722 for (i=0; i<3; ++i)
2723 if (dev->bar[i])
2724 iounmap(dev->bar[i]);
2725
2726 kfree(dev);
2727 }
2728
2729 pci_release_regions(pdev);
2730 pci_disable_device(pdev);
2731}
2732
2733static struct pci_device_id hifn_pci_tbl[] = {
2734 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2735 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2736 { 0 }
2737};
2738MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2739
2740static struct pci_driver hifn_pci_driver = {
2741 .name = "hifn795x",
2742 .id_table = hifn_pci_tbl,
2743 .probe = hifn_probe,
2744 .remove = __devexit_p(hifn_remove),
2745};
2746
2747static int __devinit hifn_init(void)
2748{
Patrick McHardy37a80232007-11-21 12:47:13 +08002749 unsigned int freq;
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002750 int err;
2751
Evgeniy Polyakova44b56c2008-10-12 20:14:15 +08002752 if (sizeof(dma_addr_t) > 4) {
2753 printk(KERN_INFO "HIFN supports only 32-bit addresses.\n");
2754 return -EINVAL;
2755 }
2756
Patrick McHardy37a80232007-11-21 12:47:13 +08002757 if (strncmp(hifn_pll_ref, "ext", 3) &&
2758 strncmp(hifn_pll_ref, "pci", 3)) {
2759 printk(KERN_ERR "hifn795x: invalid hifn_pll_ref clock, "
2760 "must be pci or ext");
2761 return -EINVAL;
2762 }
2763
2764 /*
2765 * For the 7955/7956 the reference clock frequency must be in the
2766 * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz,
2767 * but this chip is currently not supported.
2768 */
2769 if (hifn_pll_ref[3] != '\0') {
2770 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
2771 if (freq < 20 || freq > 100) {
2772 printk(KERN_ERR "hifn795x: invalid hifn_pll_ref "
2773 "frequency, must be in the range "
2774 "of 20-100");
2775 return -EINVAL;
2776 }
2777 }
2778
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +08002779 err = pci_register_driver(&hifn_pci_driver);
2780 if (err < 0) {
2781 dprintk("Failed to register PCI driver for %s device.\n",
2782 hifn_pci_driver.name);
2783 return -ENODEV;
2784 }
2785
2786 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2787 "has been successfully registered.\n");
2788
2789 return 0;
2790}
2791
2792static void __devexit hifn_fini(void)
2793{
2794 pci_unregister_driver(&hifn_pci_driver);
2795
2796 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2797 "has been successfully unregistered.\n");
2798}
2799
2800module_init(hifn_init);
2801module_exit(hifn_fini);
2802
2803MODULE_LICENSE("GPL");
2804MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2805MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");