Uwe Kleine-König | 5886269 | 2007-05-09 07:51:49 +0200 | [diff] [blame] | 1 | /*arch/powerpc/platforms/8xx/mpc885ads_setup.c |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 2 | * |
| 3 | * Platform setup for the Freescale mpc885ads board |
| 4 | * |
| 5 | * Vitaly Bordug <vbordug@ru.mvista.com> |
| 6 | * |
| 7 | * Copyright 2005 MontaVista Software Inc. |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public License |
| 10 | * version 2. This program is licensed "as is" without any warranty of any |
| 11 | * kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/param.h> |
| 17 | #include <linux/string.h> |
| 18 | #include <linux/ioport.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/root_dev.h> |
| 22 | |
| 23 | #include <linux/fs_enet_pd.h> |
| 24 | #include <linux/fs_uart_pd.h> |
Vitaly Bordug | 80128ff | 2007-07-09 11:37:35 -0700 | [diff] [blame] | 25 | #include <linux/fsl_devices.h> |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 26 | #include <linux/mii.h> |
| 27 | |
| 28 | #include <asm/delay.h> |
| 29 | #include <asm/io.h> |
| 30 | #include <asm/machdep.h> |
| 31 | #include <asm/page.h> |
| 32 | #include <asm/processor.h> |
| 33 | #include <asm/system.h> |
| 34 | #include <asm/time.h> |
| 35 | #include <asm/ppcboot.h> |
| 36 | #include <asm/mpc8xx.h> |
| 37 | #include <asm/8xx_immap.h> |
| 38 | #include <asm/commproc.h> |
| 39 | #include <asm/fs_pd.h> |
| 40 | #include <asm/prom.h> |
| 41 | |
| 42 | extern void cpm_reset(void); |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 43 | extern void mpc8xx_show_cpuinfo(struct seq_file *); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 44 | extern void mpc8xx_restart(char *cmd); |
| 45 | extern void mpc8xx_calibrate_decr(void); |
| 46 | extern int mpc8xx_set_rtc_time(struct rtc_time *tm); |
| 47 | extern void mpc8xx_get_rtc_time(struct rtc_time *tm); |
| 48 | extern void m8xx_pic_init(void); |
| 49 | extern unsigned int mpc8xx_get_irq(void); |
| 50 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 51 | static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi); |
| 52 | static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi); |
| 53 | static void init_scc3_ioports(struct fs_platform_info *ptr); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 54 | |
Vitaly Bordug | 80128ff | 2007-07-09 11:37:35 -0700 | [diff] [blame] | 55 | #ifdef CONFIG_PCMCIA_M8XX |
| 56 | static void pcmcia_hw_setup(int slot, int enable) |
| 57 | { |
| 58 | unsigned *bcsr_io; |
| 59 | |
| 60 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); |
| 61 | if (enable) |
| 62 | clrbits32(bcsr_io, BCSR1_PCCEN); |
| 63 | else |
| 64 | setbits32(bcsr_io, BCSR1_PCCEN); |
| 65 | |
| 66 | iounmap(bcsr_io); |
| 67 | } |
| 68 | |
| 69 | static int pcmcia_set_voltage(int slot, int vcc, int vpp) |
| 70 | { |
| 71 | u32 reg = 0; |
| 72 | unsigned *bcsr_io; |
| 73 | |
| 74 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); |
| 75 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 76 | switch (vcc) { |
Vitaly Bordug | 80128ff | 2007-07-09 11:37:35 -0700 | [diff] [blame] | 77 | case 0: |
| 78 | break; |
| 79 | case 33: |
| 80 | reg |= BCSR1_PCCVCC0; |
| 81 | break; |
| 82 | case 50: |
| 83 | reg |= BCSR1_PCCVCC1; |
| 84 | break; |
| 85 | default: |
| 86 | return 1; |
| 87 | } |
| 88 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 89 | switch (vpp) { |
Vitaly Bordug | 80128ff | 2007-07-09 11:37:35 -0700 | [diff] [blame] | 90 | case 0: |
| 91 | break; |
| 92 | case 33: |
| 93 | case 50: |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 94 | if (vcc == vpp) |
Vitaly Bordug | 80128ff | 2007-07-09 11:37:35 -0700 | [diff] [blame] | 95 | reg |= BCSR1_PCCVPP1; |
| 96 | else |
| 97 | return 1; |
| 98 | break; |
| 99 | case 120: |
| 100 | if ((vcc == 33) || (vcc == 50)) |
| 101 | reg |= BCSR1_PCCVPP0; |
| 102 | else |
| 103 | return 1; |
| 104 | default: |
| 105 | return 1; |
| 106 | } |
| 107 | |
| 108 | /* first, turn off all power */ |
| 109 | clrbits32(bcsr_io, 0x00610000); |
| 110 | |
| 111 | /* enable new powersettings */ |
| 112 | setbits32(bcsr_io, reg); |
| 113 | |
| 114 | iounmap(bcsr_io); |
| 115 | return 0; |
| 116 | } |
| 117 | #endif |
| 118 | |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 119 | void __init mpc885ads_board_setup(void) |
| 120 | { |
| 121 | cpm8xx_t *cp; |
| 122 | unsigned int *bcsr_io; |
| 123 | u8 tmpval8; |
| 124 | |
| 125 | #ifdef CONFIG_FS_ENET |
| 126 | iop8xx_t *io_port; |
| 127 | #endif |
| 128 | |
| 129 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 130 | cp = (cpm8xx_t *) immr_map(im_cpm); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 131 | |
| 132 | if (bcsr_io == NULL) { |
| 133 | printk(KERN_CRIT "Could not remap BCSR\n"); |
| 134 | return; |
| 135 | } |
| 136 | #ifdef CONFIG_SERIAL_CPM_SMC1 |
| 137 | clrbits32(bcsr_io, BCSR1_RS232EN_1); |
| 138 | clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */ |
| 139 | tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX); |
| 140 | out_8(&(cp->cp_smc[0].smc_smcm), tmpval8); |
| 141 | clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */ |
| 142 | #else |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 143 | setbits32(bcsr_io, BCSR1_RS232EN_1); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 144 | out_be16(&cp->cp_smc[0].smc_smcmr, 0); |
| 145 | out_8(&cp->cp_smc[0].smc_smce, 0); |
| 146 | #endif |
| 147 | |
| 148 | #ifdef CONFIG_SERIAL_CPM_SMC2 |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 149 | clrbits32(bcsr_io, BCSR1_RS232EN_2); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 150 | clrbits32(&cp->cp_simode, 0xe0000000 >> 1); |
| 151 | setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */ |
| 152 | tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX); |
| 153 | out_8(&(cp->cp_smc[1].smc_smcm), tmpval8); |
| 154 | clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN); |
| 155 | |
| 156 | init_smc2_uart_ioports(0); |
| 157 | #else |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 158 | setbits32(bcsr_io, BCSR1_RS232EN_2); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 159 | out_be16(&cp->cp_smc[1].smc_smcmr, 0); |
| 160 | out_8(&cp->cp_smc[1].smc_smce, 0); |
| 161 | #endif |
| 162 | immr_unmap(cp); |
| 163 | iounmap(bcsr_io); |
| 164 | |
| 165 | #ifdef CONFIG_FS_ENET |
| 166 | /* use MDC for MII (common) */ |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 167 | io_port = (iop8xx_t *) immr_map(im_ioport); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 168 | setbits16(&io_port->iop_pdpar, 0x0080); |
| 169 | clrbits16(&io_port->iop_pddir, 0x0080); |
| 170 | |
| 171 | bcsr_io = ioremap(BCSR5, sizeof(unsigned long)); |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 172 | clrbits32(bcsr_io, BCSR5_MII1_EN); |
| 173 | clrbits32(bcsr_io, BCSR5_MII1_RST); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 174 | #ifndef CONFIG_FC_ENET_HAS_SCC |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 175 | clrbits32(bcsr_io, BCSR5_MII2_EN); |
| 176 | clrbits32(bcsr_io, BCSR5_MII2_RST); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 177 | |
| 178 | #endif |
| 179 | iounmap(bcsr_io); |
| 180 | immr_unmap(io_port); |
| 181 | |
| 182 | #endif |
Vitaly Bordug | 80128ff | 2007-07-09 11:37:35 -0700 | [diff] [blame] | 183 | |
| 184 | #ifdef CONFIG_PCMCIA_M8XX |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 185 | /*Set up board specific hook-ups */ |
Vitaly Bordug | 80128ff | 2007-07-09 11:37:35 -0700 | [diff] [blame] | 186 | m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup; |
| 187 | m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage; |
| 188 | #endif |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 189 | } |
| 190 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 191 | static void init_fec1_ioports(struct fs_platform_info *ptr) |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 192 | { |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 193 | cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm); |
| 194 | iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 195 | |
| 196 | /* configure FEC1 pins */ |
| 197 | setbits16(&io_port->iop_papar, 0xf830); |
| 198 | setbits16(&io_port->iop_padir, 0x0830); |
| 199 | clrbits16(&io_port->iop_padir, 0xf000); |
| 200 | |
| 201 | setbits32(&cp->cp_pbpar, 0x00001001); |
| 202 | clrbits32(&cp->cp_pbdir, 0x00001001); |
| 203 | |
| 204 | setbits16(&io_port->iop_pcpar, 0x000c); |
| 205 | clrbits16(&io_port->iop_pcdir, 0x000c); |
| 206 | |
| 207 | setbits32(&cp->cp_pepar, 0x00000003); |
| 208 | setbits32(&cp->cp_pedir, 0x00000003); |
| 209 | clrbits32(&cp->cp_peso, 0x00000003); |
| 210 | clrbits32(&cp->cp_cptr, 0x00000100); |
| 211 | |
| 212 | immr_unmap(io_port); |
| 213 | immr_unmap(cp); |
| 214 | } |
| 215 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 216 | static void init_fec2_ioports(struct fs_platform_info *ptr) |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 217 | { |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 218 | cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm); |
| 219 | iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 220 | |
| 221 | /* configure FEC2 pins */ |
| 222 | setbits32(&cp->cp_pepar, 0x0003fffc); |
| 223 | setbits32(&cp->cp_pedir, 0x0003fffc); |
| 224 | clrbits32(&cp->cp_peso, 0x000087fc); |
| 225 | setbits32(&cp->cp_peso, 0x00037800); |
| 226 | clrbits32(&cp->cp_cptr, 0x00000080); |
| 227 | |
| 228 | immr_unmap(io_port); |
| 229 | immr_unmap(cp); |
| 230 | } |
| 231 | |
| 232 | void init_fec_ioports(struct fs_platform_info *fpi) |
| 233 | { |
| 234 | int fec_no = fs_get_fec_index(fpi->fs_no); |
| 235 | |
| 236 | switch (fec_no) { |
| 237 | case 0: |
| 238 | init_fec1_ioports(fpi); |
| 239 | break; |
| 240 | case 1: |
| 241 | init_fec2_ioports(fpi); |
| 242 | break; |
| 243 | default: |
| 244 | printk(KERN_ERR "init_fec_ioports: invalid FEC number\n"); |
| 245 | return; |
| 246 | } |
| 247 | } |
| 248 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 249 | static void init_scc3_ioports(struct fs_platform_info *fpi) |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 250 | { |
| 251 | unsigned *bcsr_io; |
| 252 | iop8xx_t *io_port; |
| 253 | cpm8xx_t *cp; |
| 254 | |
| 255 | bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 256 | io_port = (iop8xx_t *) immr_map(im_ioport); |
| 257 | cp = (cpm8xx_t *) immr_map(im_cpm); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 258 | |
| 259 | if (bcsr_io == NULL) { |
| 260 | printk(KERN_CRIT "Could not remap BCSR\n"); |
| 261 | return; |
| 262 | } |
| 263 | |
| 264 | /* Enable the PHY. |
| 265 | */ |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 266 | clrbits32(bcsr_io + 4, BCSR4_ETH10_RST); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 267 | udelay(1000); |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 268 | setbits32(bcsr_io + 4, BCSR4_ETH10_RST); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 269 | /* Configure port A pins for Txd and Rxd. |
| 270 | */ |
| 271 | setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD); |
| 272 | clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD); |
| 273 | |
| 274 | /* Configure port C pins to enable CLSN and RENA. |
| 275 | */ |
| 276 | clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); |
| 277 | clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); |
| 278 | setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); |
| 279 | |
| 280 | /* Configure port E for TCLK and RCLK. |
| 281 | */ |
| 282 | setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK); |
| 283 | clrbits32(&cp->cp_pepar, PE_ENET_TENA); |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 284 | clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 285 | clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK); |
| 286 | setbits32(&cp->cp_peso, PE_ENET_TENA); |
| 287 | |
| 288 | /* Configure Serial Interface clock routing. |
| 289 | * First, clear all SCC bits to zero, then set the ones we want. |
| 290 | */ |
| 291 | clrbits32(&cp->cp_sicr, SICR_ENET_MASK); |
| 292 | setbits32(&cp->cp_sicr, SICR_ENET_CLKRT); |
| 293 | |
| 294 | /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used. |
| 295 | */ |
| 296 | clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); |
| 297 | /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode |
| 298 | * by H/W setting after reset. SCC ethernet controller support only half duplex. |
| 299 | * This discrepancy of modes causes a lot of carrier lost errors. |
| 300 | */ |
| 301 | |
| 302 | /* In the original SCC enet driver the following code is placed at |
| 303 | the end of the initialization */ |
| 304 | setbits32(&cp->cp_pepar, PE_ENET_TENA); |
| 305 | clrbits32(&cp->cp_pedir, PE_ENET_TENA); |
| 306 | setbits32(&cp->cp_peso, PE_ENET_TENA); |
| 307 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 308 | setbits32(bcsr_io + 4, BCSR1_ETHEN); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 309 | iounmap(bcsr_io); |
| 310 | immr_unmap(io_port); |
| 311 | immr_unmap(cp); |
| 312 | } |
| 313 | |
| 314 | void init_scc_ioports(struct fs_platform_info *fpi) |
| 315 | { |
| 316 | int scc_no = fs_get_scc_index(fpi->fs_no); |
| 317 | |
| 318 | switch (scc_no) { |
| 319 | case 2: |
| 320 | init_scc3_ioports(fpi); |
| 321 | break; |
| 322 | default: |
| 323 | printk(KERN_ERR "init_scc_ioports: invalid SCC number\n"); |
| 324 | return; |
| 325 | } |
| 326 | } |
| 327 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 328 | static void init_smc1_uart_ioports(struct fs_uart_platform_info *ptr) |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 329 | { |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 330 | unsigned *bcsr_io; |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 331 | cpm8xx_t *cp; |
| 332 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 333 | cp = (cpm8xx_t *) immr_map(im_cpm); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 334 | setbits32(&cp->cp_pepar, 0x000000c0); |
| 335 | clrbits32(&cp->cp_pedir, 0x000000c0); |
| 336 | clrbits32(&cp->cp_peso, 0x00000040); |
| 337 | setbits32(&cp->cp_peso, 0x00000080); |
| 338 | immr_unmap(cp); |
| 339 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 340 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 341 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 342 | if (bcsr_io == NULL) { |
| 343 | printk(KERN_CRIT "Could not remap BCSR1\n"); |
| 344 | return; |
| 345 | } |
| 346 | clrbits32(bcsr_io, BCSR1_RS232EN_1); |
| 347 | iounmap(bcsr_io); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 348 | } |
| 349 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 350 | static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi) |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 351 | { |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 352 | unsigned *bcsr_io; |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 353 | cpm8xx_t *cp; |
| 354 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 355 | cp = (cpm8xx_t *) immr_map(im_cpm); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 356 | setbits32(&cp->cp_pepar, 0x00000c00); |
| 357 | clrbits32(&cp->cp_pedir, 0x00000c00); |
| 358 | clrbits32(&cp->cp_peso, 0x00000400); |
| 359 | setbits32(&cp->cp_peso, 0x00000800); |
| 360 | immr_unmap(cp); |
| 361 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 362 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 363 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 364 | if (bcsr_io == NULL) { |
| 365 | printk(KERN_CRIT "Could not remap BCSR1\n"); |
| 366 | return; |
| 367 | } |
| 368 | clrbits32(bcsr_io, BCSR1_RS232EN_2); |
| 369 | iounmap(bcsr_io); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | void init_smc_ioports(struct fs_uart_platform_info *data) |
| 373 | { |
| 374 | int smc_no = fs_uart_id_fsid2smc(data->fs_no); |
| 375 | |
| 376 | switch (smc_no) { |
| 377 | case 0: |
| 378 | init_smc1_uart_ioports(data); |
| 379 | data->brg = data->clk_rx; |
| 380 | break; |
| 381 | case 1: |
| 382 | init_smc2_uart_ioports(data); |
| 383 | data->brg = data->clk_rx; |
| 384 | break; |
| 385 | default: |
| 386 | printk(KERN_ERR "init_scc_ioports: invalid SCC number\n"); |
| 387 | return; |
| 388 | } |
| 389 | } |
| 390 | |
Stephen Rothwell | e2eb639 | 2007-04-03 22:26:41 +1000 | [diff] [blame] | 391 | int platform_device_skip(const char *model, int id) |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 392 | { |
| 393 | #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 |
| 394 | const char *dev = "FEC"; |
| 395 | int n = 2; |
| 396 | #else |
| 397 | const char *dev = "SCC"; |
| 398 | int n = 3; |
| 399 | #endif |
| 400 | |
| 401 | if (!strcmp(model, dev) && n == id) |
| 402 | return 1; |
| 403 | |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | static void __init mpc885ads_setup_arch(void) |
| 408 | { |
| 409 | struct device_node *cpu; |
| 410 | |
| 411 | cpu = of_find_node_by_type(NULL, "cpu"); |
| 412 | if (cpu != 0) { |
| 413 | const unsigned int *fp; |
| 414 | |
Stephen Rothwell | e2eb639 | 2007-04-03 22:26:41 +1000 | [diff] [blame] | 415 | fp = of_get_property(cpu, "clock-frequency", NULL); |
Vitaly Bordug | df34403 | 2007-01-24 22:41:42 +0300 | [diff] [blame] | 416 | if (fp != 0) |
| 417 | loops_per_jiffy = *fp / HZ; |
| 418 | else |
| 419 | loops_per_jiffy = 50000000 / HZ; |
| 420 | of_node_put(cpu); |
| 421 | } |
| 422 | |
| 423 | cpm_reset(); |
| 424 | |
| 425 | mpc885ads_board_setup(); |
| 426 | |
| 427 | ROOT_DEV = Root_NFS; |
| 428 | } |
| 429 | |
| 430 | static int __init mpc885ads_probe(void) |
| 431 | { |
| 432 | char *model = of_get_flat_dt_prop(of_get_flat_dt_root(), |
| 433 | "model", NULL); |
| 434 | if (model == NULL) |
| 435 | return 0; |
| 436 | if (strcmp(model, "MPC885ADS")) |
| 437 | return 0; |
| 438 | |
| 439 | return 1; |
| 440 | } |
| 441 | |
Vitaly Bordug | 99121c0 | 2007-07-17 04:03:37 -0700 | [diff] [blame^] | 442 | define_machine(mpc885_ads) |
| 443 | { |
| 444 | .name = "MPC885 ADS",.probe = mpc885ads_probe,.setup_arch = |
| 445 | mpc885ads_setup_arch,.init_IRQ = |
| 446 | m8xx_pic_init,.show_cpuinfo = mpc8xx_show_cpuinfo,.get_irq = |
| 447 | mpc8xx_get_irq,.restart = mpc8xx_restart,.calibrate_decr = |
| 448 | mpc8xx_calibrate_decr,.set_rtc_time = |
| 449 | mpc8xx_set_rtc_time,.get_rtc_time = mpc8xx_get_rtc_time,}; |