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gerrit-public.fairphone.software / kernel / msm-4.9 / 99131f0c035526c216d62e6dd96a2ee78c547eda / . / include / uapi / drm / msm_drm_pp.h
blob: d9155a957cbe53327e00413c11ff2a6d5da06c92 [file] [log] [blame]
Gopikrishnaiah Anandan8cc073f2015-10-29 18:41:38 -0700[diff] [blame]1#ifndef _MSM_DRM_PP_H_
2#define _MSM_DRM_PP_H_
3
Gopikrishnaiah Anandan530f6012017-01-03 14:42:37 -0800[diff] [blame]4#include <linux/types.h>
Gopikrishnaiah Anandan8cc073f2015-10-29 18:41:38 -0700[diff] [blame]5/**
6 * struct drm_msm_pcc_coeff - PCC coefficient structure for each color
7 * component.
8 * @c: constant coefficient.
9 * @r: red coefficient.
10 * @g: green coefficient.
11 * @b: blue coefficient.
12 * @rg: red green coefficient.
13 * @gb: green blue coefficient.
14 * @rb: red blue coefficient.
15 * @rgb: red blue green coefficient.
16 */
17
18struct drm_msm_pcc_coeff {
19 __u32 c;
20 __u32 r;
21 __u32 g;
22 __u32 b;
23 __u32 rg;
24 __u32 gb;
25 __u32 rb;
26 __u32 rgb;
27};
28
29/**
30 * struct drm_msm_pcc - pcc feature structure
Benet Clarkd009b1d2016-06-27 14:45:59 -0700[diff] [blame]31 * flags: for customizing operations
Gopikrishnaiah Anandan8cc073f2015-10-29 18:41:38 -0700[diff] [blame]32 * r: red coefficients.
33 * g: green coefficients.
34 * b: blue coefficients.
35 */
36
37struct drm_msm_pcc {
38 __u64 flags;
39 struct drm_msm_pcc_coeff r;
40 struct drm_msm_pcc_coeff g;
41 struct drm_msm_pcc_coeff b;
42};
43
Benet Clarkd009b1d2016-06-27 14:45:59 -0700[diff] [blame]44/* struct drm_msm_pa_vlut - picture adjustment vLUT structure
45 * flags: for customizing vlut operation
46 * val: vLUT values
47 */
Gopikrishnaiah Anandanb67b0d12016-06-23 11:43:08 -0700[diff] [blame]48#define PA_VLUT_SIZE 256
49struct drm_msm_pa_vlut {
50 __u64 flags;
51 __u32 val[PA_VLUT_SIZE];
52};
53
Benet Clarkd009b1d2016-06-27 14:45:59 -0700[diff] [blame]54/* struct drm_msm_memcol - Memory color feature strucuture.
55 * Skin, sky, foliage features are supported.
56 * @prot_flags: Bit mask for enabling protection feature.
57 * @color_adjust_p0: Adjustment curve.
58 * @color_adjust_p1: Adjustment curve.
59 * @color_adjust_p2: Adjustment curve.
60 * @blend_gain: Blend gain weightage from othe PA features.
61 * @sat_hold: Saturation hold value.
62 * @val_hold: Value hold info.
63 * @hue_region: Hue qualifier.
64 * @sat_region: Saturation qualifier.
65 * @val_region: Value qualifier.
66 */
67#define DRM_MSM_MEMCOL
68struct drm_msm_memcol {
69 __u64 prot_flags;
70 __u32 color_adjust_p0;
71 __u32 color_adjust_p1;
72 __u32 color_adjust_p2;
73 __u32 blend_gain;
74 __u32 sat_hold;
75 __u32 val_hold;
76 __u32 hue_region;
77 __u32 sat_region;
78 __u32 val_region;
79};
80
Gopikrishnaiah Anandan530f6012017-01-03 14:42:37 -0800[diff] [blame]81#define GAMUT_3D_MODE_17 1
82#define GAMUT_3D_MODE_5 2
83#define GAMUT_3D_MODE_13 3
84
85#define GAMUT_3D_MODE17_TBL_SZ 1229
86#define GAMUT_3D_MODE5_TBL_SZ 32
87#define GAMUT_3D_MODE13_TBL_SZ 550
88#define GAMUT_3D_SCALE_OFF_SZ 16
89#define GAMUT_3D_TBL_NUM 4
90#define GAMUT_3D_SCALE_OFF_TBL_NUM 3
91#define GAMUT_3D_MAP_EN (1 << 0)
92
93/**
94 * struct drm_msm_3d_col - 3d gamut color component structure
95 * @c0: Holds c0 value
96 * @c2_c1: Holds c2/c1 values
97 */
98struct drm_msm_3d_col {
Gopikrishnaiah Anandan530f6012017-01-03 14:42:37 -0800[diff] [blame]99 __u32 c2_c1;
Gopikrishnaiah Anandan8b1498a2017-05-10 16:58:04 -0700[diff] [blame]100 __u32 c0;
Gopikrishnaiah Anandan530f6012017-01-03 14:42:37 -0800[diff] [blame]101};
102/**
103 * struct drm_msm_3d_gamut - 3d gamut feature structure
104 * @flags: flags for the feature values are:
105 * 0 - no map
106 * GAMUT_3D_MAP_EN - enable map
107 * @mode: lut mode can take following values:
108 * - GAMUT_3D_MODE_17
109 * - GAMUT_3D_MODE_5
110 * - GAMUT_3D_MODE_13
111 * @scale_off: Scale offset table
112 * @col: Color component tables
113 */
114struct drm_msm_3d_gamut {
115 __u64 flags;
116 __u32 mode;
117 __u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];
118 struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ];
119};
Gopikrishnaiah Anandanaedb9862017-01-16 11:04:29 -0800[diff] [blame]120
121#define PGC_TBL_LEN 512
122#define PGC_8B_ROUND (1 << 0)
123/**
124 * struct drm_msm_pgc_lut - pgc lut feature structure
125 * @flags: flags for the featue values can be:
126 * - PGC_8B_ROUND
127 * @c0: color0 component lut
128 * @c1: color1 component lut
129 * @c2: color2 component lut
130 */
131struct drm_msm_pgc_lut {
132 __u64 flags;
133 __u32 c0[PGC_TBL_LEN];
134 __u32 c1[PGC_TBL_LEN];
135 __u32 c2[PGC_TBL_LEN];
136};
Gopikrishnaiah Anandan1d9d0002017-02-03 10:35:40 -0800[diff] [blame]137
138#define AD4_LUT_GRP0_SIZE 33
139#define AD4_LUT_GRP1_SIZE 32
140/*
141 * struct drm_msm_ad4_init - ad4 init structure set by user-space client.
142 * Init param values can change based on tuning
143 * hence it is passed by user-space clients.
144 */
145struct drm_msm_ad4_init {
146 __u32 init_param_001[AD4_LUT_GRP0_SIZE];
147 __u32 init_param_002[AD4_LUT_GRP0_SIZE];
148 __u32 init_param_003[AD4_LUT_GRP0_SIZE];
149 __u32 init_param_004[AD4_LUT_GRP0_SIZE];
150 __u32 init_param_005[AD4_LUT_GRP1_SIZE];
151 __u32 init_param_006[AD4_LUT_GRP1_SIZE];
152 __u32 init_param_007[AD4_LUT_GRP0_SIZE];
153 __u32 init_param_008[AD4_LUT_GRP0_SIZE];
154 __u32 init_param_009;
155 __u32 init_param_010;
156 __u32 init_param_011;
157 __u32 init_param_012;
158 __u32 init_param_013;
159 __u32 init_param_014;
160 __u32 init_param_015;
161 __u32 init_param_016;
162 __u32 init_param_017;
163 __u32 init_param_018;
164 __u32 init_param_019;
165 __u32 init_param_020;
166 __u32 init_param_021;
167 __u32 init_param_022;
168 __u32 init_param_023;
169 __u32 init_param_024;
170 __u32 init_param_025;
171 __u32 init_param_026;
172 __u32 init_param_027;
173 __u32 init_param_028;
174 __u32 init_param_029;
175 __u32 init_param_030;
176 __u32 init_param_031;
177 __u32 init_param_032;
178 __u32 init_param_033;
179 __u32 init_param_034;
180 __u32 init_param_035;
181 __u32 init_param_036;
182 __u32 init_param_037;
183 __u32 init_param_038;
184 __u32 init_param_039;
185 __u32 init_param_040;
186 __u32 init_param_041;
187 __u32 init_param_042;
188 __u32 init_param_043;
189 __u32 init_param_044;
190 __u32 init_param_045;
191 __u32 init_param_046;
192 __u32 init_param_047;
193 __u32 init_param_048;
194 __u32 init_param_049;
195 __u32 init_param_050;
196 __u32 init_param_051;
197 __u32 init_param_052;
198 __u32 init_param_053;
199 __u32 init_param_054;
200 __u32 init_param_055;
201 __u32 init_param_056;
202 __u32 init_param_057;
203 __u32 init_param_058;
204 __u32 init_param_059;
205 __u32 init_param_060;
206 __u32 init_param_061;
207 __u32 init_param_062;
208 __u32 init_param_063;
209 __u32 init_param_064;
210 __u32 init_param_065;
211 __u32 init_param_066;
212 __u32 init_param_067;
213 __u32 init_param_068;
214 __u32 init_param_069;
215 __u32 init_param_070;
216 __u32 init_param_071;
217 __u32 init_param_072;
218 __u32 init_param_073;
219 __u32 init_param_074;
220 __u32 init_param_075;
221};
222
223/*
224 * struct drm_msm_ad4_cfg - ad4 config structure set by user-space client.
225 * Config param values can vary based on tuning,
226 * hence it is passed by user-space clients.
227 */
228struct drm_msm_ad4_cfg {
229 __u32 cfg_param_001;
230 __u32 cfg_param_002;
231 __u32 cfg_param_003;
232 __u32 cfg_param_004;
233 __u32 cfg_param_005;
234 __u32 cfg_param_006;
235 __u32 cfg_param_007;
236 __u32 cfg_param_008;
237 __u32 cfg_param_009;
238 __u32 cfg_param_010;
239 __u32 cfg_param_011;
240 __u32 cfg_param_012;
241 __u32 cfg_param_013;
242 __u32 cfg_param_014;
243 __u32 cfg_param_015;
244 __u32 cfg_param_016;
245 __u32 cfg_param_017;
246 __u32 cfg_param_018;
247 __u32 cfg_param_019;
248 __u32 cfg_param_020;
249 __u32 cfg_param_021;
250 __u32 cfg_param_022;
251 __u32 cfg_param_023;
252 __u32 cfg_param_024;
253 __u32 cfg_param_025;
254 __u32 cfg_param_026;
255 __u32 cfg_param_027;
256 __u32 cfg_param_028;
257 __u32 cfg_param_029;
258 __u32 cfg_param_030;
259 __u32 cfg_param_031;
260 __u32 cfg_param_032;
261 __u32 cfg_param_033;
262 __u32 cfg_param_034;
263 __u32 cfg_param_035;
264 __u32 cfg_param_036;
265 __u32 cfg_param_037;
266 __u32 cfg_param_038;
267 __u32 cfg_param_039;
268 __u32 cfg_param_040;
269 __u32 cfg_param_041;
270 __u32 cfg_param_042;
271 __u32 cfg_param_043;
272 __u32 cfg_param_044;
273 __u32 cfg_param_045;
274 __u32 cfg_param_046;
275 __u32 cfg_param_047;
276 __u32 cfg_param_048;
277 __u32 cfg_param_049;
278 __u32 cfg_param_050;
279 __u32 cfg_param_051;
280 __u32 cfg_param_052;
281 __u32 cfg_param_053;
282};
283
Gopikrishnaiah Anandan8cc073f2015-10-29 18:41:38 -0700[diff] [blame]284#endif /* _MSM_DRM_PP_H_ */