blob: 7d56b47e4fcfd8e5774d31d5dc5f3bf7bc3a4bcf [file] [log] [blame]
Andy Shevchenko667dfed2015-07-27 18:04:02 +03001/*
2 * Core driver for the Intel integrated DMA 64-bit
3 *
4 * Copyright (C) 2015 Intel Corporation
5 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/bitops.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmapool.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include "idma64.h"
23
24/* Platform driver name */
25#define DRV_NAME "idma64"
26
27/* For now we support only two channels */
28#define IDMA64_NR_CHAN 2
29
30/* ---------------------------------------------------------------------- */
31
32static struct device *chan2dev(struct dma_chan *chan)
33{
34 return &chan->dev->device;
35}
36
37/* ---------------------------------------------------------------------- */
38
39static void idma64_off(struct idma64 *idma64)
40{
41 unsigned short count = 100;
42
43 dma_writel(idma64, CFG, 0);
44
45 channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
46 channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
47 channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
48 channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
49 channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
50
51 do {
52 cpu_relax();
53 } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
54}
55
56static void idma64_on(struct idma64 *idma64)
57{
58 dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
59}
60
61/* ---------------------------------------------------------------------- */
62
63static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
64{
65 u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
66 u32 cfglo = 0;
67
Andy Shevchenko667dfed2015-07-27 18:04:02 +030068 /* Set default burst alignment */
69 cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
70
71 channel_writel(idma64c, CFG_LO, cfglo);
72 channel_writel(idma64c, CFG_HI, cfghi);
73
74 /* Enable interrupts */
75 channel_set_bit(idma64, MASK(XFER), idma64c->mask);
76 channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
77
78 /*
79 * Enforce the controller to be turned on.
80 *
81 * The iDMA is turned off in ->probe() and looses context during system
82 * suspend / resume cycle. That's why we have to enable it each time we
83 * use it.
84 */
85 idma64_on(idma64);
86}
87
88static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
89{
90 channel_clear_bit(idma64, CH_EN, idma64c->mask);
91}
92
93static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
94{
95 struct idma64_desc *desc = idma64c->desc;
96 struct idma64_hw_desc *hw = &desc->hw[0];
97
98 channel_writeq(idma64c, SAR, 0);
99 channel_writeq(idma64c, DAR, 0);
100
101 channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
102 channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
103
104 channel_writeq(idma64c, LLP, hw->llp);
105
106 channel_set_bit(idma64, CH_EN, idma64c->mask);
107}
108
109static void idma64_stop_transfer(struct idma64_chan *idma64c)
110{
111 struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
112
113 idma64_chan_stop(idma64, idma64c);
114}
115
116static void idma64_start_transfer(struct idma64_chan *idma64c)
117{
118 struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
119 struct virt_dma_desc *vdesc;
120
121 /* Get the next descriptor */
122 vdesc = vchan_next_desc(&idma64c->vchan);
123 if (!vdesc) {
124 idma64c->desc = NULL;
125 return;
126 }
127
128 list_del(&vdesc->node);
129 idma64c->desc = to_idma64_desc(vdesc);
130
131 /* Configure the channel */
132 idma64_chan_init(idma64, idma64c);
133
134 /* Start the channel with a new descriptor */
135 idma64_chan_start(idma64, idma64c);
136}
137
138/* ---------------------------------------------------------------------- */
139
140static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
141 u32 status_err, u32 status_xfer)
142{
143 struct idma64_chan *idma64c = &idma64->chan[c];
144 struct idma64_desc *desc;
145 unsigned long flags;
146
147 spin_lock_irqsave(&idma64c->vchan.lock, flags);
148 desc = idma64c->desc;
149 if (desc) {
150 if (status_err & (1 << c)) {
151 dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
152 desc->status = DMA_ERROR;
153 } else if (status_xfer & (1 << c)) {
154 dma_writel(idma64, CLEAR(XFER), idma64c->mask);
155 desc->status = DMA_COMPLETE;
156 vchan_cookie_complete(&desc->vdesc);
157 idma64_start_transfer(idma64c);
158 }
159
160 /* idma64_start_transfer() updates idma64c->desc */
161 if (idma64c->desc == NULL || desc->status == DMA_ERROR)
162 idma64_stop_transfer(idma64c);
163 }
164 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
165}
166
167static irqreturn_t idma64_irq(int irq, void *dev)
168{
169 struct idma64 *idma64 = dev;
170 u32 status = dma_readl(idma64, STATUS_INT);
171 u32 status_xfer;
172 u32 status_err;
173 unsigned short i;
174
175 dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
176
177 /* Check if we have any interrupt from the DMA controller */
178 if (!status)
179 return IRQ_NONE;
180
181 /* Disable interrupts */
182 channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
183 channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
184
185 status_xfer = dma_readl(idma64, RAW(XFER));
186 status_err = dma_readl(idma64, RAW(ERROR));
187
188 for (i = 0; i < idma64->dma.chancnt; i++)
189 idma64_chan_irq(idma64, i, status_err, status_xfer);
190
191 /* Re-enable interrupts */
192 channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask);
193 channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
194
195 return IRQ_HANDLED;
196}
197
198/* ---------------------------------------------------------------------- */
199
200static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
201{
202 struct idma64_desc *desc;
203
204 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
205 if (!desc)
206 return NULL;
207
208 desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
209 if (!desc->hw) {
210 kfree(desc);
211 return NULL;
212 }
213
214 return desc;
215}
216
217static void idma64_desc_free(struct idma64_chan *idma64c,
218 struct idma64_desc *desc)
219{
220 struct idma64_hw_desc *hw;
221
222 if (desc->ndesc) {
223 unsigned int i = desc->ndesc;
224
225 do {
226 hw = &desc->hw[--i];
227 dma_pool_free(idma64c->pool, hw->lli, hw->llp);
228 } while (i);
229 }
230
231 kfree(desc->hw);
232 kfree(desc);
233}
234
235static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
236{
237 struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
238
239 idma64_desc_free(idma64c, to_idma64_desc(vdesc));
240}
241
242static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
243 struct dma_slave_config *config,
244 enum dma_transfer_direction direction, u64 llp)
245{
246 struct idma64_lli *lli = hw->lli;
247 u64 sar, dar;
248 u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
249 u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
250 u32 src_width, dst_width;
251
252 if (direction == DMA_MEM_TO_DEV) {
253 sar = hw->phys;
254 dar = config->dst_addr;
255 ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
256 IDMA64C_CTLL_FC_M2P;
Andy Shevchenko22b74402015-09-14 11:55:38 +0300257 src_width = __ffs(sar | hw->len | 4);
Andy Shevchenko87b04592015-09-14 11:55:37 +0300258 dst_width = __ffs(config->dst_addr_width);
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300259 } else { /* DMA_DEV_TO_MEM */
260 sar = config->src_addr;
261 dar = hw->phys;
262 ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
263 IDMA64C_CTLL_FC_P2M;
Andy Shevchenko87b04592015-09-14 11:55:37 +0300264 src_width = __ffs(config->src_addr_width);
Andy Shevchenko22b74402015-09-14 11:55:38 +0300265 dst_width = __ffs(dar | hw->len | 4);
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300266 }
267
268 lli->sar = sar;
269 lli->dar = dar;
270
271 lli->ctlhi = ctlhi;
272 lli->ctllo = ctllo |
273 IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
274 IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
275 IDMA64C_CTLL_DST_WIDTH(dst_width) |
276 IDMA64C_CTLL_SRC_WIDTH(src_width);
277
278 lli->llp = llp;
279 return hw->llp;
280}
281
282static void idma64_desc_fill(struct idma64_chan *idma64c,
283 struct idma64_desc *desc)
284{
285 struct dma_slave_config *config = &idma64c->config;
286 struct idma64_hw_desc *hw = &desc->hw[desc->ndesc - 1];
287 struct idma64_lli *lli = hw->lli;
288 u64 llp = 0;
289 unsigned int i = desc->ndesc;
290
291 /* Fill the hardware descriptors and link them to a list */
292 do {
293 hw = &desc->hw[--i];
294 llp = idma64_hw_desc_fill(hw, config, desc->direction, llp);
295 desc->length += hw->len;
296 } while (i);
297
298 /* Trigger interrupt after last block */
299 lli->ctllo |= IDMA64C_CTLL_INT_EN;
300}
301
302static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
303 struct dma_chan *chan, struct scatterlist *sgl,
304 unsigned int sg_len, enum dma_transfer_direction direction,
305 unsigned long flags, void *context)
306{
307 struct idma64_chan *idma64c = to_idma64_chan(chan);
308 struct idma64_desc *desc;
309 struct scatterlist *sg;
310 unsigned int i;
311
312 desc = idma64_alloc_desc(sg_len);
313 if (!desc)
314 return NULL;
315
316 for_each_sg(sgl, sg, sg_len, i) {
317 struct idma64_hw_desc *hw = &desc->hw[i];
318
319 /* Allocate DMA capable memory for hardware descriptor */
320 hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
321 if (!hw->lli) {
322 desc->ndesc = i;
323 idma64_desc_free(idma64c, desc);
324 return NULL;
325 }
326
327 hw->phys = sg_dma_address(sg);
328 hw->len = sg_dma_len(sg);
329 }
330
331 desc->ndesc = sg_len;
332 desc->direction = direction;
333 desc->status = DMA_IN_PROGRESS;
334
335 idma64_desc_fill(idma64c, desc);
336 return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
337}
338
339static void idma64_issue_pending(struct dma_chan *chan)
340{
341 struct idma64_chan *idma64c = to_idma64_chan(chan);
342 unsigned long flags;
343
344 spin_lock_irqsave(&idma64c->vchan.lock, flags);
345 if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
346 idma64_start_transfer(idma64c);
347 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
348}
349
350static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
351{
352 struct idma64_desc *desc = idma64c->desc;
353 struct idma64_hw_desc *hw;
354 size_t bytes = desc->length;
Andy Shevchenko0b23a1e2015-09-14 11:55:36 +0300355 u64 llp = channel_readq(idma64c, LLP);
356 u32 ctlhi = channel_readl(idma64c, CTL_HI);
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300357 unsigned int i = 0;
358
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300359 do {
360 hw = &desc->hw[i];
Andy Shevchenko0b23a1e2015-09-14 11:55:36 +0300361 if (hw->llp == llp)
362 break;
363 bytes -= hw->len;
364 } while (++i < desc->ndesc);
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300365
366 if (!i)
367 return bytes;
368
Andy Shevchenko0b23a1e2015-09-14 11:55:36 +0300369 /* The current chunk is not fully transfered yet */
370 bytes += desc->hw[--i].len;
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300371
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300372 return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
373}
374
375static enum dma_status idma64_tx_status(struct dma_chan *chan,
376 dma_cookie_t cookie, struct dma_tx_state *state)
377{
378 struct idma64_chan *idma64c = to_idma64_chan(chan);
379 struct virt_dma_desc *vdesc;
380 enum dma_status status;
381 size_t bytes;
382 unsigned long flags;
383
384 status = dma_cookie_status(chan, cookie, state);
385 if (status == DMA_COMPLETE)
386 return status;
387
388 spin_lock_irqsave(&idma64c->vchan.lock, flags);
389 vdesc = vchan_find_desc(&idma64c->vchan, cookie);
390 if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
391 bytes = idma64_active_desc_size(idma64c);
392 dma_set_residue(state, bytes);
393 status = idma64c->desc->status;
394 } else if (vdesc) {
395 bytes = to_idma64_desc(vdesc)->length;
396 dma_set_residue(state, bytes);
397 }
398 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
399
400 return status;
401}
402
403static void convert_burst(u32 *maxburst)
404{
405 if (*maxburst)
406 *maxburst = __fls(*maxburst);
407 else
408 *maxburst = 0;
409}
410
411static int idma64_slave_config(struct dma_chan *chan,
412 struct dma_slave_config *config)
413{
414 struct idma64_chan *idma64c = to_idma64_chan(chan);
415
416 /* Check if chan will be configured for slave transfers */
417 if (!is_slave_direction(config->direction))
418 return -EINVAL;
419
420 memcpy(&idma64c->config, config, sizeof(idma64c->config));
421
422 convert_burst(&idma64c->config.src_maxburst);
423 convert_burst(&idma64c->config.dst_maxburst);
424
425 return 0;
426}
427
Andy Shevchenko2e9b55b2015-09-14 11:55:40 +0300428static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300429{
430 unsigned short count = 100;
431 u32 cfglo;
432
433 cfglo = channel_readl(idma64c, CFG_LO);
Andy Shevchenko2e9b55b2015-09-14 11:55:40 +0300434 if (drain)
435 cfglo |= IDMA64C_CFGL_CH_DRAIN;
436 else
437 cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
438
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300439 channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
440 do {
441 udelay(1);
442 cfglo = channel_readl(idma64c, CFG_LO);
443 } while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
444}
445
446static void idma64_chan_activate(struct idma64_chan *idma64c)
447{
448 u32 cfglo;
449
450 cfglo = channel_readl(idma64c, CFG_LO);
451 channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
452}
453
454static int idma64_pause(struct dma_chan *chan)
455{
456 struct idma64_chan *idma64c = to_idma64_chan(chan);
457 unsigned long flags;
458
459 spin_lock_irqsave(&idma64c->vchan.lock, flags);
460 if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
Andy Shevchenko2e9b55b2015-09-14 11:55:40 +0300461 idma64_chan_deactivate(idma64c, false);
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300462 idma64c->desc->status = DMA_PAUSED;
463 }
464 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
465
466 return 0;
467}
468
469static int idma64_resume(struct dma_chan *chan)
470{
471 struct idma64_chan *idma64c = to_idma64_chan(chan);
472 unsigned long flags;
473
474 spin_lock_irqsave(&idma64c->vchan.lock, flags);
475 if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
476 idma64c->desc->status = DMA_IN_PROGRESS;
477 idma64_chan_activate(idma64c);
478 }
479 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
480
481 return 0;
482}
483
484static int idma64_terminate_all(struct dma_chan *chan)
485{
486 struct idma64_chan *idma64c = to_idma64_chan(chan);
487 unsigned long flags;
488 LIST_HEAD(head);
489
490 spin_lock_irqsave(&idma64c->vchan.lock, flags);
Andy Shevchenko2e9b55b2015-09-14 11:55:40 +0300491 idma64_chan_deactivate(idma64c, true);
Andy Shevchenko667dfed2015-07-27 18:04:02 +0300492 idma64_stop_transfer(idma64c);
493 if (idma64c->desc) {
494 idma64_vdesc_free(&idma64c->desc->vdesc);
495 idma64c->desc = NULL;
496 }
497 vchan_get_all_descriptors(&idma64c->vchan, &head);
498 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
499
500 vchan_dma_desc_free_list(&idma64c->vchan, &head);
501 return 0;
502}
503
504static int idma64_alloc_chan_resources(struct dma_chan *chan)
505{
506 struct idma64_chan *idma64c = to_idma64_chan(chan);
507
508 /* Create a pool of consistent memory blocks for hardware descriptors */
509 idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
510 chan->device->dev,
511 sizeof(struct idma64_lli), 8, 0);
512 if (!idma64c->pool) {
513 dev_err(chan2dev(chan), "No memory for descriptors\n");
514 return -ENOMEM;
515 }
516
517 return 0;
518}
519
520static void idma64_free_chan_resources(struct dma_chan *chan)
521{
522 struct idma64_chan *idma64c = to_idma64_chan(chan);
523
524 vchan_free_chan_resources(to_virt_chan(chan));
525 dma_pool_destroy(idma64c->pool);
526 idma64c->pool = NULL;
527}
528
529/* ---------------------------------------------------------------------- */
530
531#define IDMA64_BUSWIDTHS \
532 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
533 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
534 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
535
536static int idma64_probe(struct idma64_chip *chip)
537{
538 struct idma64 *idma64;
539 unsigned short nr_chan = IDMA64_NR_CHAN;
540 unsigned short i;
541 int ret;
542
543 idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
544 if (!idma64)
545 return -ENOMEM;
546
547 idma64->regs = chip->regs;
548 chip->idma64 = idma64;
549
550 idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
551 GFP_KERNEL);
552 if (!idma64->chan)
553 return -ENOMEM;
554
555 idma64->all_chan_mask = (1 << nr_chan) - 1;
556
557 /* Turn off iDMA controller */
558 idma64_off(idma64);
559
560 ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
561 dev_name(chip->dev), idma64);
562 if (ret)
563 return ret;
564
565 INIT_LIST_HEAD(&idma64->dma.channels);
566 for (i = 0; i < nr_chan; i++) {
567 struct idma64_chan *idma64c = &idma64->chan[i];
568
569 idma64c->vchan.desc_free = idma64_vdesc_free;
570 vchan_init(&idma64c->vchan, &idma64->dma);
571
572 idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
573 idma64c->mask = BIT(i);
574 }
575
576 dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
577 dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
578
579 idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
580 idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
581
582 idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
583
584 idma64->dma.device_issue_pending = idma64_issue_pending;
585 idma64->dma.device_tx_status = idma64_tx_status;
586
587 idma64->dma.device_config = idma64_slave_config;
588 idma64->dma.device_pause = idma64_pause;
589 idma64->dma.device_resume = idma64_resume;
590 idma64->dma.device_terminate_all = idma64_terminate_all;
591
592 idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
593 idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
594 idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
595 idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
596
597 idma64->dma.dev = chip->dev;
598
599 ret = dma_async_device_register(&idma64->dma);
600 if (ret)
601 return ret;
602
603 dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
604 return 0;
605}
606
607static int idma64_remove(struct idma64_chip *chip)
608{
609 struct idma64 *idma64 = chip->idma64;
610 unsigned short i;
611
612 dma_async_device_unregister(&idma64->dma);
613
614 /*
615 * Explicitly call devm_request_irq() to avoid the side effects with
616 * the scheduled tasklets.
617 */
618 devm_free_irq(chip->dev, chip->irq, idma64);
619
620 for (i = 0; i < idma64->dma.chancnt; i++) {
621 struct idma64_chan *idma64c = &idma64->chan[i];
622
623 tasklet_kill(&idma64c->vchan.task);
624 }
625
626 return 0;
627}
628
629/* ---------------------------------------------------------------------- */
630
631static int idma64_platform_probe(struct platform_device *pdev)
632{
633 struct idma64_chip *chip;
634 struct device *dev = &pdev->dev;
635 struct resource *mem;
636 int ret;
637
638 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
639 if (!chip)
640 return -ENOMEM;
641
642 chip->irq = platform_get_irq(pdev, 0);
643 if (chip->irq < 0)
644 return chip->irq;
645
646 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
647 chip->regs = devm_ioremap_resource(dev, mem);
648 if (IS_ERR(chip->regs))
649 return PTR_ERR(chip->regs);
650
651 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
652 if (ret)
653 return ret;
654
655 chip->dev = dev;
656
657 ret = idma64_probe(chip);
658 if (ret)
659 return ret;
660
661 platform_set_drvdata(pdev, chip);
662 return 0;
663}
664
665static int idma64_platform_remove(struct platform_device *pdev)
666{
667 struct idma64_chip *chip = platform_get_drvdata(pdev);
668
669 return idma64_remove(chip);
670}
671
672#ifdef CONFIG_PM_SLEEP
673
674static int idma64_pm_suspend(struct device *dev)
675{
676 struct platform_device *pdev = to_platform_device(dev);
677 struct idma64_chip *chip = platform_get_drvdata(pdev);
678
679 idma64_off(chip->idma64);
680 return 0;
681}
682
683static int idma64_pm_resume(struct device *dev)
684{
685 struct platform_device *pdev = to_platform_device(dev);
686 struct idma64_chip *chip = platform_get_drvdata(pdev);
687
688 idma64_on(chip->idma64);
689 return 0;
690}
691
692#endif /* CONFIG_PM_SLEEP */
693
694static const struct dev_pm_ops idma64_dev_pm_ops = {
695 SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
696};
697
698static struct platform_driver idma64_platform_driver = {
699 .probe = idma64_platform_probe,
700 .remove = idma64_platform_remove,
701 .driver = {
702 .name = DRV_NAME,
703 .pm = &idma64_dev_pm_ops,
704 },
705};
706
707module_platform_driver(idma64_platform_driver);
708
709MODULE_LICENSE("GPL v2");
710MODULE_DESCRIPTION("iDMA64 core driver");
711MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
712MODULE_ALIAS("platform:" DRV_NAME);