Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #define MMCIPOWER 0x000 |
| 11 | #define MCI_PWR_OFF 0x00 |
| 12 | #define MCI_PWR_UP 0x02 |
| 13 | #define MCI_PWR_ON 0x03 |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 14 | #define MCI_DATA2DIREN (1 << 2) |
| 15 | #define MCI_CMDDIREN (1 << 3) |
| 16 | #define MCI_DATA0DIREN (1 << 4) |
| 17 | #define MCI_DATA31DIREN (1 << 5) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #define MCI_OD (1 << 6) |
| 19 | #define MCI_ROD (1 << 7) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 20 | /* The ST Micro version does not have ROD */ |
| 21 | #define MCI_FBCLKEN (1 << 7) |
| 22 | #define MCI_DATA74DIREN (1 << 8) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | |
| 24 | #define MMCICLOCK 0x004 |
| 25 | #define MCI_CLK_ENABLE (1 << 8) |
| 26 | #define MCI_CLK_PWRSAVE (1 << 9) |
| 27 | #define MCI_CLK_BYPASS (1 << 10) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 28 | #define MCI_WIDE_BUS (1 << 11) |
| 29 | /* HW flow control on the ST Micro version */ |
| 30 | #define MCI_FCEN (1 << 13) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
| 32 | #define MMCIARGUMENT 0x008 |
| 33 | #define MMCICOMMAND 0x00c |
| 34 | #define MCI_CPSM_RESPONSE (1 << 6) |
| 35 | #define MCI_CPSM_LONGRSP (1 << 7) |
| 36 | #define MCI_CPSM_INTERRUPT (1 << 8) |
| 37 | #define MCI_CPSM_PENDING (1 << 9) |
| 38 | #define MCI_CPSM_ENABLE (1 << 10) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 39 | #define MCI_SDIO_SUSP (1 << 11) |
| 40 | #define MCI_ENCMD_COMPL (1 << 12) |
| 41 | #define MCI_NIEN (1 << 13) |
| 42 | #define MCI_CE_ATACMD (1 << 14) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
| 44 | #define MMCIRESPCMD 0x010 |
| 45 | #define MMCIRESPONSE0 0x014 |
| 46 | #define MMCIRESPONSE1 0x018 |
| 47 | #define MMCIRESPONSE2 0x01c |
| 48 | #define MMCIRESPONSE3 0x020 |
| 49 | #define MMCIDATATIMER 0x024 |
| 50 | #define MMCIDATALENGTH 0x028 |
| 51 | #define MMCIDATACTRL 0x02c |
| 52 | #define MCI_DPSM_ENABLE (1 << 0) |
| 53 | #define MCI_DPSM_DIRECTION (1 << 1) |
| 54 | #define MCI_DPSM_MODE (1 << 2) |
| 55 | #define MCI_DPSM_DMAENABLE (1 << 3) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 56 | #define MCI_DPSM_BLOCKSIZE (1 << 4) |
| 57 | #define MCI_DPSM_RWSTART (1 << 8) |
| 58 | #define MCI_DPSM_RWSTOP (1 << 9) |
| 59 | #define MCI_DPSM_RWMOD (1 << 10) |
| 60 | #define MCI_DPSM_SDIOEN (1 << 11) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | |
| 62 | #define MMCIDATACNT 0x030 |
| 63 | #define MMCISTATUS 0x034 |
| 64 | #define MCI_CMDCRCFAIL (1 << 0) |
| 65 | #define MCI_DATACRCFAIL (1 << 1) |
| 66 | #define MCI_CMDTIMEOUT (1 << 2) |
| 67 | #define MCI_DATATIMEOUT (1 << 3) |
| 68 | #define MCI_TXUNDERRUN (1 << 4) |
| 69 | #define MCI_RXOVERRUN (1 << 5) |
| 70 | #define MCI_CMDRESPEND (1 << 6) |
| 71 | #define MCI_CMDSENT (1 << 7) |
| 72 | #define MCI_DATAEND (1 << 8) |
| 73 | #define MCI_DATABLOCKEND (1 << 10) |
| 74 | #define MCI_CMDACTIVE (1 << 11) |
| 75 | #define MCI_TXACTIVE (1 << 12) |
| 76 | #define MCI_RXACTIVE (1 << 13) |
| 77 | #define MCI_TXFIFOHALFEMPTY (1 << 14) |
| 78 | #define MCI_RXFIFOHALFFULL (1 << 15) |
| 79 | #define MCI_TXFIFOFULL (1 << 16) |
| 80 | #define MCI_RXFIFOFULL (1 << 17) |
| 81 | #define MCI_TXFIFOEMPTY (1 << 18) |
| 82 | #define MCI_RXFIFOEMPTY (1 << 19) |
| 83 | #define MCI_TXDATAAVLBL (1 << 20) |
| 84 | #define MCI_RXDATAAVLBL (1 << 21) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 85 | #define MCI_SDIOIT (1 << 22) |
| 86 | #define MCI_CEATAEND (1 << 23) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | |
| 88 | #define MMCICLEAR 0x038 |
| 89 | #define MCI_CMDCRCFAILCLR (1 << 0) |
| 90 | #define MCI_DATACRCFAILCLR (1 << 1) |
| 91 | #define MCI_CMDTIMEOUTCLR (1 << 2) |
| 92 | #define MCI_DATATIMEOUTCLR (1 << 3) |
| 93 | #define MCI_TXUNDERRUNCLR (1 << 4) |
| 94 | #define MCI_RXOVERRUNCLR (1 << 5) |
| 95 | #define MCI_CMDRESPENDCLR (1 << 6) |
| 96 | #define MCI_CMDSENTCLR (1 << 7) |
| 97 | #define MCI_DATAENDCLR (1 << 8) |
| 98 | #define MCI_DATABLOCKENDCLR (1 << 10) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 99 | #define MCI_SDIOITC (1 << 22) |
| 100 | #define MCI_CEATAENDC (1 << 23) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | |
| 102 | #define MMCIMASK0 0x03c |
| 103 | #define MCI_CMDCRCFAILMASK (1 << 0) |
| 104 | #define MCI_DATACRCFAILMASK (1 << 1) |
| 105 | #define MCI_CMDTIMEOUTMASK (1 << 2) |
| 106 | #define MCI_DATATIMEOUTMASK (1 << 3) |
| 107 | #define MCI_TXUNDERRUNMASK (1 << 4) |
| 108 | #define MCI_RXOVERRUNMASK (1 << 5) |
| 109 | #define MCI_CMDRESPENDMASK (1 << 6) |
| 110 | #define MCI_CMDSENTMASK (1 << 7) |
| 111 | #define MCI_DATAENDMASK (1 << 8) |
| 112 | #define MCI_DATABLOCKENDMASK (1 << 10) |
| 113 | #define MCI_CMDACTIVEMASK (1 << 11) |
| 114 | #define MCI_TXACTIVEMASK (1 << 12) |
| 115 | #define MCI_RXACTIVEMASK (1 << 13) |
| 116 | #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) |
| 117 | #define MCI_RXFIFOHALFFULLMASK (1 << 15) |
| 118 | #define MCI_TXFIFOFULLMASK (1 << 16) |
| 119 | #define MCI_RXFIFOFULLMASK (1 << 17) |
| 120 | #define MCI_TXFIFOEMPTYMASK (1 << 18) |
| 121 | #define MCI_RXFIFOEMPTYMASK (1 << 19) |
| 122 | #define MCI_TXDATAAVLBLMASK (1 << 20) |
| 123 | #define MCI_RXDATAAVLBLMASK (1 << 21) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 124 | #define MCI_SDIOITMASK (1 << 22) |
| 125 | #define MCI_CEATAENDMASK (1 << 23) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | |
| 127 | #define MMCIMASK1 0x040 |
| 128 | #define MMCIFIFOCNT 0x048 |
| 129 | #define MMCIFIFO 0x080 /* to 0x0bc */ |
| 130 | |
| 131 | #define MCI_IRQENABLE \ |
| 132 | (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ |
| 133 | MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ |
| 134 | MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK) |
| 135 | |
| 136 | /* |
| 137 | * The size of the FIFO in bytes. |
| 138 | */ |
| 139 | #define MCI_FIFOSIZE (16*4) |
| 140 | |
| 141 | #define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2) |
| 142 | |
| 143 | #define NR_SG 16 |
| 144 | |
| 145 | struct clk; |
| 146 | |
| 147 | struct mmci_host { |
| 148 | void __iomem *base; |
| 149 | struct mmc_request *mrq; |
| 150 | struct mmc_command *cmd; |
| 151 | struct mmc_data *data; |
| 152 | struct mmc_host *mmc; |
| 153 | struct clk *clk; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 154 | int gpio_cd; |
| 155 | int gpio_wp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | |
| 157 | unsigned int data_xfered; |
| 158 | |
| 159 | spinlock_t lock; |
| 160 | |
| 161 | unsigned int mclk; |
| 162 | unsigned int cclk; |
| 163 | u32 pwr; |
| 164 | struct mmc_platform_data *plat; |
| 165 | |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 166 | u8 hw_designer; |
| 167 | u8 hw_revision:4; |
| 168 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | struct timer_list timer; |
| 170 | unsigned int oldstat; |
| 171 | |
| 172 | unsigned int sg_len; |
| 173 | |
| 174 | /* pio stuff */ |
| 175 | struct scatterlist *sg_ptr; |
| 176 | unsigned int sg_off; |
| 177 | unsigned int size; |
| 178 | }; |
| 179 | |
| 180 | static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
| 181 | { |
| 182 | /* |
| 183 | * Ideally, we want the higher levels to pass us a scatter list. |
| 184 | */ |
| 185 | host->sg_len = data->sg_len; |
| 186 | host->sg_ptr = data->sg; |
| 187 | host->sg_off = 0; |
| 188 | } |
| 189 | |
| 190 | static inline int mmci_next_sg(struct mmci_host *host) |
| 191 | { |
| 192 | host->sg_ptr++; |
| 193 | host->sg_off = 0; |
| 194 | return --host->sg_len; |
| 195 | } |
| 196 | |
| 197 | static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags) |
| 198 | { |
| 199 | struct scatterlist *sg = host->sg_ptr; |
| 200 | |
| 201 | local_irq_save(*flags); |
Emil Medve | 4e01776 | 2007-10-23 20:37:24 +0200 | [diff] [blame] | 202 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | } |
| 204 | |
Evgeniy Polyakov | f3e2628 | 2006-01-05 10:31:23 +0000 | [diff] [blame] | 205 | static inline void mmci_kunmap_atomic(struct mmci_host *host, void *buffer, unsigned long *flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | { |
Evgeniy Polyakov | f3e2628 | 2006-01-05 10:31:23 +0000 | [diff] [blame] | 207 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | local_irq_restore(*flags); |
| 209 | } |