| Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _ADRENO_A4XX_H_ |
| 15 | #define _ADRENO_A4XX_H_ |
| 16 | |
| 17 | #include "a4xx_reg.h" |
| 18 | |
| 19 | #define A4XX_IRQ_FLAGS \ |
| 20 | { BIT(A4XX_INT_RBBM_GPU_IDLE), "RBBM_GPU_IDLE" }, \ |
| 21 | { BIT(A4XX_INT_RBBM_REG_TIMEOUT), "RBBM_REG_TIMEOUT" }, \ |
| 22 | { BIT(A4XX_INT_RBBM_ME_MS_TIMEOUT), "RBBM_ME_MS_TIMEOUT" }, \ |
| 23 | { BIT(A4XX_INT_RBBM_PFP_MS_TIMEOUT), "RBBM_PFP_MS_TIMEOUT" }, \ |
| 24 | { BIT(A4XX_INT_RBBM_ETS_MS_TIMEOUT), "RBBM_ETS_MS_TIMEOUT" }, \ |
| 25 | { BIT(A4XX_INT_RBBM_ASYNC_OVERFLOW), "RBBM_ASYNC_OVERFLOW" }, \ |
| 26 | { BIT(A4XX_INT_RBBM_GPC_ERR), "RBBM_GPC_ERR" }, \ |
| 27 | { BIT(A4XX_INT_CP_SW), "CP_SW" }, \ |
| 28 | { BIT(A4XX_INT_CP_OPCODE_ERROR), "CP_OPCODE_ERROR" }, \ |
| 29 | { BIT(A4XX_INT_CP_RESERVED_BIT_ERROR), "CP_RESERVED_BIT_ERROR" }, \ |
| 30 | { BIT(A4XX_INT_CP_HW_FAULT), "CP_HW_FAULT" }, \ |
| 31 | { BIT(A4XX_INT_CP_DMA), "CP_DMA" }, \ |
| 32 | { BIT(A4XX_INT_CP_IB2_INT), "CP_IB2_INT" }, \ |
| 33 | { BIT(A4XX_INT_CP_IB1_INT), "CP_IB1_INT" }, \ |
| 34 | { BIT(A4XX_INT_CP_RB_INT), "CP_RB_INT" }, \ |
| 35 | { BIT(A4XX_INT_CP_REG_PROTECT_FAULT), "CP_REG_PROTECT_FAULT" }, \ |
| 36 | { BIT(A4XX_INT_CP_RB_DONE_TS), "CP_RB_DONE_TS" }, \ |
| 37 | { BIT(A4XX_INT_CP_VS_DONE_TS), "CP_VS_DONE_TS" }, \ |
| 38 | { BIT(A4XX_INT_CP_PS_DONE_TS), "CP_PS_DONE_TS" }, \ |
| 39 | { BIT(A4XX_INT_CACHE_FLUSH_TS), "CACHE_FLUSH_TS" }, \ |
| 40 | { BIT(A4XX_INT_CP_AHB_ERROR_HALT), "CP_AHB_ERROR_HALT" }, \ |
| 41 | { BIT(A4XX_INT_RBBM_ATB_BUS_OVERFLOW), "RBBM_ATB_BUS_OVERFLOW" }, \ |
| 42 | { BIT(A4XX_INT_MISC_HANG_DETECT), "MISC_HANG_DETECT" }, \ |
| 43 | { BIT(A4XX_INT_UCHE_OOB_ACCESS), "UCHE_OOB_ACCESS" }, \ |
| 44 | { BIT(A4XX_INT_RBBM_DPM_CALC_ERR), "RBBM_DPM_CALC_ERR" }, \ |
| 45 | { BIT(A4XX_INT_RBBM_DPM_EPOCH_ERR), "RBBM_DPM_CALC_ERR" }, \ |
| 46 | { BIT(A4XX_INT_RBBM_DPM_THERMAL_YELLOW_ERR), \ |
| 47 | "RBBM_DPM_THERMAL_YELLOW_ERR" }, \ |
| 48 | { BIT(A4XX_INT_RBBM_DPM_THERMAL_RED_ERR), "RBBM_DPM_THERMAL_RED_ERR" } |
| 49 | |
| 50 | unsigned int a4xx_preemption_pre_ibsubmit(struct adreno_device *adreno_dev, |
| 51 | struct adreno_ringbuffer *rb, |
| 52 | unsigned int *cmds, |
| 53 | struct kgsl_context *context); |
| 54 | |
| 55 | void a4xx_preemption_schedule(struct adreno_device *adreno_dev); |
| 56 | |
| 57 | int a4xx_preemption_init(struct adreno_device *adreno_dev); |
| 58 | |
| 59 | void a4xx_snapshot(struct adreno_device *adreno_dev, |
| 60 | struct kgsl_snapshot *snapshot); |
| 61 | |
| 62 | #endif |