Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2010-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __KGSL_PWRCTRL_H |
| 14 | #define __KGSL_PWRCTRL_H |
| 15 | |
| 16 | #include <linux/pm_qos.h> |
| 17 | |
| 18 | /***************************************************************************** |
| 19 | * power flags |
| 20 | ****************************************************************************/ |
| 21 | #define KGSL_PWRFLAGS_ON 1 |
| 22 | #define KGSL_PWRFLAGS_OFF 0 |
| 23 | |
| 24 | #define KGSL_PWRLEVEL_TURBO 0 |
| 25 | |
| 26 | #define KGSL_PWR_ON 0xFFFF |
| 27 | |
Harshdeep Dhatt | 70c80f9 | 2017-04-26 22:10:26 -0600 | [diff] [blame] | 28 | #define KGSL_MAX_CLKS 17 |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 29 | #define KGSL_MAX_REGULATORS 2 |
| 30 | |
| 31 | #define KGSL_MAX_PWRLEVELS 10 |
| 32 | |
| 33 | /* Only two supported levels, min & max */ |
| 34 | #define KGSL_CONSTRAINT_PWR_MAXLEVELS 2 |
| 35 | |
| 36 | #define KGSL_XO_CLK_FREQ 19200000 |
| 37 | #define KGSL_RBBMTIMER_CLK_FREQ KGSL_XO_CLK_FREQ |
| 38 | #define KGSL_ISENSE_CLK_FREQ 200000000 |
| 39 | |
| 40 | /* Symbolic table for the constraint type */ |
| 41 | #define KGSL_CONSTRAINT_TYPES \ |
| 42 | { KGSL_CONSTRAINT_NONE, "None" }, \ |
| 43 | { KGSL_CONSTRAINT_PWRLEVEL, "Pwrlevel" } |
| 44 | /* Symbolic table for the constraint sub type */ |
| 45 | #define KGSL_CONSTRAINT_PWRLEVEL_SUBTYPES \ |
| 46 | { KGSL_CONSTRAINT_PWR_MIN, "Min" }, \ |
| 47 | { KGSL_CONSTRAINT_PWR_MAX, "Max" } |
| 48 | |
| 49 | #define KGSL_PWR_ADD_LIMIT 0 |
| 50 | #define KGSL_PWR_DEL_LIMIT 1 |
| 51 | #define KGSL_PWR_SET_LIMIT 2 |
| 52 | |
| 53 | enum kgsl_pwrctrl_timer_type { |
| 54 | KGSL_PWR_IDLE_TIMER, |
| 55 | }; |
| 56 | |
| 57 | /* |
| 58 | * States for thermal cycling. _DISABLE means that no cycling has been |
| 59 | * requested. _ENABLE means that cycling has been requested, but GPU |
| 60 | * DCVS is currently recommending running at a lower frequency than the |
| 61 | * cycle frequency. _ACTIVE means that the frequency is actively being |
| 62 | * cycled. |
| 63 | */ |
| 64 | #define CYCLE_DISABLE 0 |
| 65 | #define CYCLE_ENABLE 1 |
| 66 | #define CYCLE_ACTIVE 2 |
| 67 | |
| 68 | struct platform_device; |
| 69 | |
| 70 | struct kgsl_clk_stats { |
| 71 | unsigned int busy; |
| 72 | unsigned int total; |
| 73 | unsigned int busy_old; |
| 74 | unsigned int total_old; |
| 75 | }; |
| 76 | |
| 77 | struct kgsl_pwr_constraint { |
| 78 | unsigned int type; |
| 79 | unsigned int sub_type; |
| 80 | union { |
| 81 | struct { |
| 82 | unsigned int level; |
| 83 | } pwrlevel; |
| 84 | } hint; |
| 85 | unsigned long expires; |
| 86 | uint32_t owner_id; |
| 87 | }; |
| 88 | |
| 89 | /** |
| 90 | * struct kgsl_pwrlevel - Struct holding different pwrlevel info obtained from |
| 91 | * from dtsi file |
| 92 | * @gpu_freq: GPU frequency vote in Hz |
| 93 | * @bus_freq: Bus bandwidth vote index |
| 94 | * @bus_min: Min bus index @gpu_freq |
| 95 | * @bus_max: Max bus index @gpu_freq |
| 96 | */ |
| 97 | struct kgsl_pwrlevel { |
| 98 | unsigned int gpu_freq; |
| 99 | unsigned int bus_freq; |
| 100 | unsigned int bus_min; |
| 101 | unsigned int bus_max; |
| 102 | }; |
| 103 | |
| 104 | struct kgsl_regulator { |
| 105 | struct regulator *reg; |
| 106 | char name[8]; |
| 107 | }; |
| 108 | |
| 109 | /** |
| 110 | * struct kgsl_pwrctrl - Power control settings for a KGSL device |
| 111 | * @interrupt_num - The interrupt number for the device |
| 112 | * @grp_clks - Array of clocks structures that we control |
| 113 | * @power_flags - Control flags for power |
| 114 | * @pwrlevels - List of supported power levels |
| 115 | * @active_pwrlevel - The currently active power level |
| 116 | * @previous_pwrlevel - The power level before transition |
| 117 | * @thermal_pwrlevel - maximum powerlevel constraint from thermal |
| 118 | * @default_pwrlevel - device wake up power level |
| 119 | * @max_pwrlevel - maximum allowable powerlevel per the user |
| 120 | * @min_pwrlevel - minimum allowable powerlevel per the user |
| 121 | * @num_pwrlevels - number of available power levels |
| 122 | * @interval_timeout - timeout in jiffies to be idle before a power event |
| 123 | * @clock_times - Each GPU frequency's accumulated active time in us |
| 124 | * @regulators - array of pointers to kgsl_regulator structs |
| 125 | * @pcl - bus scale identifier |
| 126 | * @ocmem - ocmem bus scale identifier |
| 127 | * @irq_name - resource name for the IRQ |
| 128 | * @clk_stats - structure of clock statistics |
| 129 | * @l2pc_cpus_mask - mask to avoid L2PC on masked CPUs |
| 130 | * @l2pc_cpus_qos - qos structure to avoid L2PC on CPUs |
| 131 | * @pm_qos_req_dma - the power management quality of service structure |
| 132 | * @pm_qos_active_latency - allowed CPU latency in microseconds when active |
| 133 | * @pm_qos_cpu_mask_latency - allowed CPU mask latency in microseconds |
| 134 | * @pm_qos_wakeup_latency - allowed CPU latency in microseconds during wakeup |
| 135 | * @bus_control - true if the bus calculation is independent |
| 136 | * @bus_mod - modifier from the current power level for the bus vote |
| 137 | * @bus_percent_ab - current percent of total possible bus usage |
| 138 | * @bus_width - target specific bus width in number of bytes |
| 139 | * @bus_ab_mbytes - AB vote in Mbytes for current bus usage |
| 140 | * @bus_index - default bus index into the bus_ib table |
| 141 | * @bus_ib - the set of unique ib requests needed for the bus calculation |
| 142 | * @constraint - currently active power constraint |
| 143 | * @superfast - Boolean flag to indicate that the GPU start should be run in the |
| 144 | * higher priority thread |
| 145 | * @thermal_cycle_ws - Work struct for scheduling thermal cycling |
| 146 | * @thermal_timer - Timer for thermal cycling |
| 147 | * @thermal_timeout - Cycling timeout for switching between frequencies |
| 148 | * @thermal_cycle - Is thermal cycling enabled |
| 149 | * @thermal_highlow - flag for swithcing between high and low frequency |
| 150 | * @limits - list head for limits |
| 151 | * @limits_lock - spin lock to protect limits list |
| 152 | * @sysfs_pwr_limit - pointer to the sysfs limits node |
| 153 | * isense_clk_indx - index of isense clock, 0 if no isense |
| 154 | * isense_clk_on_level - isense clock rate is XO rate below this level. |
| 155 | * tzone_name - pointer to thermal zone name of GPU temperature sensor |
| 156 | */ |
| 157 | |
| 158 | struct kgsl_pwrctrl { |
| 159 | int interrupt_num; |
| 160 | struct clk *grp_clks[KGSL_MAX_CLKS]; |
| 161 | struct clk *gpu_bimc_int_clk; |
| 162 | int isense_clk_indx; |
| 163 | int isense_clk_on_level; |
| 164 | unsigned long power_flags; |
| 165 | unsigned long ctrl_flags; |
| 166 | struct kgsl_pwrlevel pwrlevels[KGSL_MAX_PWRLEVELS]; |
| 167 | unsigned int active_pwrlevel; |
| 168 | unsigned int previous_pwrlevel; |
| 169 | unsigned int thermal_pwrlevel; |
| 170 | unsigned int default_pwrlevel; |
| 171 | unsigned int wakeup_maxpwrlevel; |
| 172 | unsigned int max_pwrlevel; |
| 173 | unsigned int min_pwrlevel; |
| 174 | unsigned int num_pwrlevels; |
| 175 | unsigned long interval_timeout; |
| 176 | u64 clock_times[KGSL_MAX_PWRLEVELS]; |
| 177 | struct kgsl_regulator regulators[KGSL_MAX_REGULATORS]; |
| 178 | uint32_t pcl; |
| 179 | uint32_t ocmem_pcl; |
| 180 | const char *irq_name; |
| 181 | struct kgsl_clk_stats clk_stats; |
| 182 | unsigned int l2pc_cpus_mask; |
| 183 | struct pm_qos_request l2pc_cpus_qos; |
| 184 | struct pm_qos_request pm_qos_req_dma; |
| 185 | unsigned int pm_qos_active_latency; |
| 186 | unsigned int pm_qos_cpu_mask_latency; |
| 187 | unsigned int pm_qos_wakeup_latency; |
| 188 | bool bus_control; |
| 189 | int bus_mod; |
| 190 | unsigned int bus_percent_ab; |
| 191 | unsigned int bus_width; |
| 192 | unsigned long bus_ab_mbytes; |
| 193 | struct device *devbw; |
| 194 | unsigned int bus_index[KGSL_MAX_PWRLEVELS]; |
| 195 | uint64_t *bus_ib; |
| 196 | struct kgsl_pwr_constraint constraint; |
| 197 | bool superfast; |
| 198 | struct work_struct thermal_cycle_ws; |
| 199 | struct timer_list thermal_timer; |
| 200 | uint32_t thermal_timeout; |
| 201 | uint32_t thermal_cycle; |
| 202 | uint32_t thermal_highlow; |
| 203 | struct list_head limits; |
| 204 | spinlock_t limits_lock; |
| 205 | struct kgsl_pwr_limit *sysfs_pwr_limit; |
| 206 | unsigned int gpu_bimc_int_clk_freq; |
| 207 | bool gpu_bimc_interface_enabled; |
| 208 | const char *tzone_name; |
| 209 | }; |
| 210 | |
| 211 | int kgsl_pwrctrl_init(struct kgsl_device *device); |
| 212 | void kgsl_pwrctrl_close(struct kgsl_device *device); |
| 213 | void kgsl_timer(unsigned long data); |
| 214 | void kgsl_idle_check(struct work_struct *work); |
| 215 | void kgsl_pre_hwaccess(struct kgsl_device *device); |
| 216 | void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device, |
| 217 | unsigned int level); |
| 218 | void kgsl_pwrctrl_buslevel_update(struct kgsl_device *device, |
| 219 | bool on); |
| 220 | int kgsl_pwrctrl_init_sysfs(struct kgsl_device *device); |
| 221 | void kgsl_pwrctrl_uninit_sysfs(struct kgsl_device *device); |
| 222 | int kgsl_pwrctrl_change_state(struct kgsl_device *device, int state); |
| 223 | |
| 224 | static inline unsigned long kgsl_get_clkrate(struct clk *clk) |
| 225 | { |
| 226 | return (clk != NULL) ? clk_get_rate(clk) : 0; |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * kgsl_pwrctrl_active_freq - get currently configured frequency |
| 231 | * @pwr: kgsl_pwrctrl structure for the device |
| 232 | * |
| 233 | * Returns the currently configured frequency for the device. |
| 234 | */ |
| 235 | static inline unsigned long |
| 236 | kgsl_pwrctrl_active_freq(struct kgsl_pwrctrl *pwr) |
| 237 | { |
| 238 | return pwr->pwrlevels[pwr->active_pwrlevel].gpu_freq; |
| 239 | } |
| 240 | |
| 241 | int __must_check kgsl_active_count_get(struct kgsl_device *device); |
| 242 | void kgsl_active_count_put(struct kgsl_device *device); |
| 243 | int kgsl_active_count_wait(struct kgsl_device *device, int count); |
| 244 | void kgsl_pwrctrl_busy_time(struct kgsl_device *device, u64 time, u64 busy); |
| 245 | void kgsl_pwrctrl_set_constraint(struct kgsl_device *device, |
| 246 | struct kgsl_pwr_constraint *pwrc, uint32_t id); |
| 247 | void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device); |
| 248 | #endif /* __KGSL_PWRCTRL_H */ |