blob: 31c063d4b93e40083879875c09d5dae9dc4f6dab [file] [log] [blame]
Banajit Goswami2d3eebc2017-02-01 12:52:50 -08001/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
Banajit Goswamide8271c2017-01-18 00:28:59 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include "../../../drivers/clk/qcom/common.h"
21#include <linux/platform_device.h>
22#include <linux/gpio.h>
23#include <linux/of_gpio.h>
Banajit Goswami2d3eebc2017-02-01 12:52:50 -080024#include <dt-bindings/clock/qcom,audio-ext-clk.h>
Banajit Goswamide8271c2017-01-18 00:28:59 -080025#include <sound/q6afe-v2.h>
Karthikeyan Mani858132b2017-06-27 20:03:08 -070026#include "audio-ext-clk-up.h"
Banajit Goswamide8271c2017-01-18 00:28:59 -080027
28enum audio_clk_mux {
29 AP_CLK2,
30 LPASS_MCLK,
31 LPASS_MCLK2,
32};
33
34struct pinctrl_info {
35 struct pinctrl *pinctrl;
36 struct pinctrl_state *sleep;
37 struct pinctrl_state *active;
Meng Wang417e5712017-03-07 09:44:05 +080038 char __iomem *base;
Banajit Goswamide8271c2017-01-18 00:28:59 -080039};
40
41struct audio_ext_ap_clk {
42 bool enabled;
43 int gpio;
44 struct clk_fixed_factor fact;
45};
46
47struct audio_ext_pmi_clk {
48 int gpio;
49 struct clk_fixed_factor fact;
50};
51
52struct audio_ext_ap_clk2 {
53 bool enabled;
54 struct pinctrl_info pnctrl_info;
55 struct clk_fixed_factor fact;
56};
57
58struct audio_ext_lpass_mclk {
59 struct pinctrl_info pnctrl_info;
60 struct clk_fixed_factor fact;
61};
62
63static struct afe_clk_set clk2_config = {
64 Q6AFE_LPASS_CLK_CONFIG_API_VERSION,
65 Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR,
66 Q6AFE_LPASS_IBIT_CLK_11_P2896_MHZ,
67 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
68 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
69 0,
70};
71
72static struct afe_clk_set lpass_default = {
73 Q6AFE_LPASS_CLK_CONFIG_API_VERSION,
74 Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR,
75 Q6AFE_LPASS_IBIT_CLK_11_P2896_MHZ,
76 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
77 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
78 0,
79};
80
81static struct afe_clk_set lpass_mclk = {
82 Q6AFE_LPASS_CLK_CONFIG_API_VERSION,
83 Q6AFE_LPASS_CLK_ID_MCLK_1,
84 Q6AFE_LPASS_OSR_CLK_11_P2896_MHZ,
85 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
86 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
87 0,
88};
89
90static inline struct audio_ext_ap_clk *to_audio_ap_clk(struct clk_hw *hw)
91{
92 return container_of(hw, struct audio_ext_ap_clk, fact.hw);
93}
94
95static int audio_ext_clk_prepare(struct clk_hw *hw)
96{
97 struct audio_ext_ap_clk *audio_clk = to_audio_ap_clk(hw);
98
99 pr_debug("%s: gpio: %d\n", __func__, audio_clk->gpio);
100 if (gpio_is_valid(audio_clk->gpio))
101 return gpio_direction_output(audio_clk->gpio, 1);
102 return 0;
103}
104
105static void audio_ext_clk_unprepare(struct clk_hw *hw)
106{
107 struct audio_ext_ap_clk *audio_clk = to_audio_ap_clk(hw);
108
109 pr_debug("%s: gpio: %d\n", __func__, audio_clk->gpio);
110 if (gpio_is_valid(audio_clk->gpio))
111 gpio_direction_output(audio_clk->gpio, 0);
112}
113
114static inline struct audio_ext_ap_clk2 *to_audio_ap_clk2(struct clk_hw *hw)
115{
116 return container_of(hw, struct audio_ext_ap_clk2, fact.hw);
117}
118
119static int audio_ext_clk2_prepare(struct clk_hw *hw)
120{
121 struct audio_ext_ap_clk2 *audio_clk2 = to_audio_ap_clk2(hw);
122 struct pinctrl_info *pnctrl_info = &audio_clk2->pnctrl_info;
123 int ret;
124
125
126 if (!pnctrl_info->pinctrl || !pnctrl_info->active)
127 return 0;
128
129 ret = pinctrl_select_state(pnctrl_info->pinctrl,
130 pnctrl_info->active);
131 if (ret) {
132 pr_err("%s: active state select failed with %d\n",
133 __func__, ret);
134 return -EIO;
135 }
136
137 clk2_config.enable = 1;
138 ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk2_config);
139 if (ret < 0) {
140 pr_err("%s: failed to set clock, ret = %d\n", __func__, ret);
141 return -EINVAL;
142 }
143
144 return 0;
145}
146
147static void audio_ext_clk2_unprepare(struct clk_hw *hw)
148{
149 struct audio_ext_ap_clk2 *audio_clk2 = to_audio_ap_clk2(hw);
150 struct pinctrl_info *pnctrl_info = &audio_clk2->pnctrl_info;
151 int ret;
152
153 if (!pnctrl_info->pinctrl || !pnctrl_info->sleep)
154 return;
155
156 ret = pinctrl_select_state(pnctrl_info->pinctrl,
157 pnctrl_info->sleep);
158 if (ret)
159 pr_err("%s: sleep state select failed with %d\n",
160 __func__, ret);
161
162 clk2_config.enable = 0;
163 ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk2_config);
164 if (ret < 0)
165 pr_err("%s: failed to reset clock, ret = %d\n", __func__, ret);
166}
167
168static inline struct audio_ext_lpass_mclk *to_audio_lpass_mclk(
169 struct clk_hw *hw)
170{
171 return container_of(hw, struct audio_ext_lpass_mclk, fact.hw);
172}
173
174static int audio_ext_lpass_mclk_prepare(struct clk_hw *hw)
175{
176 struct audio_ext_lpass_mclk *audio_lpass_mclk = to_audio_lpass_mclk(hw);
177 struct pinctrl_info *pnctrl_info = &audio_lpass_mclk->pnctrl_info;
178 int ret;
179
Laxminath Kasam1f233cd2017-05-29 12:21:11 +0530180 lpass_mclk.enable = 1;
181 ret = afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX,
182 &lpass_mclk);
183 if (ret < 0) {
184 pr_err("%s afe_set_digital_codec_core_clock failed\n",
185 __func__);
186 return ret;
187 }
188
Banajit Goswamide8271c2017-01-18 00:28:59 -0800189 if (pnctrl_info->pinctrl) {
190 ret = pinctrl_select_state(pnctrl_info->pinctrl,
191 pnctrl_info->active);
192 if (ret) {
193 pr_err("%s: active state select failed with %d\n",
194 __func__, ret);
195 return -EIO;
196 }
197 }
198
Meng Wang417e5712017-03-07 09:44:05 +0800199 if (pnctrl_info->base)
200 iowrite32(1, pnctrl_info->base);
Banajit Goswamide8271c2017-01-18 00:28:59 -0800201 return 0;
202}
203
204static void audio_ext_lpass_mclk_unprepare(struct clk_hw *hw)
205{
206 struct audio_ext_lpass_mclk *audio_lpass_mclk = to_audio_lpass_mclk(hw);
207 struct pinctrl_info *pnctrl_info = &audio_lpass_mclk->pnctrl_info;
208 int ret;
209
210 if (pnctrl_info->pinctrl) {
211 ret = pinctrl_select_state(pnctrl_info->pinctrl,
212 pnctrl_info->sleep);
213 if (ret) {
214 pr_err("%s: active state select failed with %d\n",
215 __func__, ret);
216 return;
217 }
218 }
219
220 lpass_mclk.enable = 0;
221 ret = afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX,
222 &lpass_mclk);
223 if (ret < 0)
224 pr_err("%s: afe_set_digital_codec_core_clock failed, ret = %d\n",
225 __func__, ret);
Meng Wang417e5712017-03-07 09:44:05 +0800226 if (pnctrl_info->base)
227 iowrite32(0, pnctrl_info->base);
Banajit Goswamide8271c2017-01-18 00:28:59 -0800228}
229
230static int audio_ext_lpass_mclk2_prepare(struct clk_hw *hw)
231{
232 struct audio_ext_lpass_mclk *audio_lpass_mclk2 =
233 to_audio_lpass_mclk(hw);
234 struct pinctrl_info *pnctrl_info = &audio_lpass_mclk2->pnctrl_info;
235 int ret;
236
237 if (pnctrl_info->pinctrl) {
238 ret = pinctrl_select_state(pnctrl_info->pinctrl,
239 pnctrl_info->active);
240 if (ret) {
241 pr_err("%s: active state select failed with %d\n",
242 __func__, ret);
243 return -EIO;
244 }
245 }
246
247 lpass_default.enable = 1;
248 ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &lpass_default);
249 if (ret < 0) {
250 pr_err("%s: failed to set clock, ret = %d\n", __func__, ret);
251 return -EINVAL;
252 }
253
254 return 0;
255}
256
257static void audio_ext_lpass_mclk2_unprepare(struct clk_hw *hw)
258{
259 struct audio_ext_lpass_mclk *audio_lpass_mclk2 =
260 to_audio_lpass_mclk(hw);
261 struct pinctrl_info *pnctrl_info = &audio_lpass_mclk2->pnctrl_info;
262 int ret;
263
264 if (pnctrl_info->pinctrl) {
265 ret = pinctrl_select_state(pnctrl_info->pinctrl,
266 pnctrl_info->sleep);
267 if (ret)
268 pr_err("%s: sleep state select failed with %d\n",
269 __func__, ret);
270 }
271
272 lpass_default.enable = 0;
273 ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &lpass_default);
274 if (ret < 0)
275 pr_err("%s: failed to reset clock, ret = %d\n", __func__, ret);
276}
277
278static const struct clk_ops audio_ext_ap_clk_ops = {
279 .prepare = audio_ext_clk_prepare,
280 .unprepare = audio_ext_clk_unprepare,
281};
282
283static const struct clk_ops audio_ext_ap_clk2_ops = {
284 .prepare = audio_ext_clk2_prepare,
285 .unprepare = audio_ext_clk2_unprepare,
286};
287
288static const struct clk_ops audio_ext_lpass_mclk_ops = {
289 .prepare = audio_ext_lpass_mclk_prepare,
290 .unprepare = audio_ext_lpass_mclk_unprepare,
291};
292
293static const struct clk_ops audio_ext_lpass_mclk2_ops = {
294 .prepare = audio_ext_lpass_mclk2_prepare,
295 .unprepare = audio_ext_lpass_mclk2_unprepare,
296};
297
298static struct audio_ext_pmi_clk audio_pmi_clk = {
299 .gpio = -EINVAL,
300 .fact = {
301 .mult = 1,
302 .div = 1,
303 .hw.init = &(struct clk_init_data){
304 .name = "audio_ext_pmi_clk",
Yeleswarapu Nagaradhesh3f051562017-01-17 16:05:34 +0530305 .parent_names = (const char *[]){ "div_clk1" },
306 .num_parents = 1,
Banajit Goswamide8271c2017-01-18 00:28:59 -0800307 .ops = &clk_dummy_ops,
308 },
309 },
310};
311
312static struct audio_ext_pmi_clk audio_pmi_lnbb_clk = {
313 .gpio = -EINVAL,
314 .fact = {
315 .mult = 1,
316 .div = 1,
317 .hw.init = &(struct clk_init_data){
318 .name = "audio_ext_pmi_lnbb_clk",
Yeleswarapu Nagaradhesh3f051562017-01-17 16:05:34 +0530319 .parent_names = (const char *[]){ "ln_bb_clk2" },
320 .num_parents = 1,
Banajit Goswamide8271c2017-01-18 00:28:59 -0800321 .ops = &clk_dummy_ops,
322 },
323 },
324};
325
326static struct audio_ext_ap_clk audio_ap_clk = {
327 .gpio = -EINVAL,
328 .fact = {
329 .mult = 1,
330 .div = 1,
331 .hw.init = &(struct clk_init_data){
332 .name = "audio_ap_clk",
333 .ops = &audio_ext_ap_clk_ops,
334 },
335 },
336};
337
338static struct audio_ext_ap_clk2 audio_ap_clk2 = {
339 .enabled = false,
340 .pnctrl_info = {NULL},
341 .fact = {
342 .mult = 1,
343 .div = 1,
344 .hw.init = &(struct clk_init_data){
345 .name = "audio_ap_clk2",
346 .ops = &audio_ext_ap_clk2_ops,
347 },
348 },
349};
350
351static struct audio_ext_lpass_mclk audio_lpass_mclk = {
352 .pnctrl_info = {NULL},
353 .fact = {
354 .mult = 1,
355 .div = 1,
356 .hw.init = &(struct clk_init_data){
357 .name = "audio_lpass_mclk",
358 .ops = &audio_ext_lpass_mclk_ops,
359 },
360 },
361};
362
363static struct audio_ext_lpass_mclk audio_lpass_mclk2 = {
364 .pnctrl_info = {NULL},
365 .fact = {
366 .mult = 1,
367 .div = 1,
368 .hw.init = &(struct clk_init_data){
369 .name = "audio_lpass_mclk2",
370 .ops = &audio_ext_lpass_mclk2_ops,
371 },
372 },
373};
374
375static struct clk_hw *audio_msm_hws[] = {
376 &audio_pmi_clk.fact.hw,
Banajit Goswamide8271c2017-01-18 00:28:59 -0800377 &audio_ap_clk.fact.hw,
378 &audio_ap_clk2.fact.hw,
379 &audio_lpass_mclk.fact.hw,
380 &audio_lpass_mclk2.fact.hw,
381};
382
Yeleswarapu Nagaradhesh3f051562017-01-17 16:05:34 +0530383static struct clk_hw *audio_msm_hws1[] = {
384 &audio_pmi_lnbb_clk.fact.hw,
385};
386
Banajit Goswamide8271c2017-01-18 00:28:59 -0800387static int audio_get_pinctrl(struct platform_device *pdev,
388 enum audio_clk_mux mux)
389{
Meng Wang417e5712017-03-07 09:44:05 +0800390 struct device *dev = &pdev->dev;
Banajit Goswamide8271c2017-01-18 00:28:59 -0800391 struct pinctrl_info *pnctrl_info;
392 struct pinctrl *pinctrl;
393 int ret;
Meng Wang417e5712017-03-07 09:44:05 +0800394 u32 reg;
Banajit Goswamide8271c2017-01-18 00:28:59 -0800395
396 switch (mux) {
397 case AP_CLK2:
398 pnctrl_info = &audio_ap_clk2.pnctrl_info;
399 break;
400 case LPASS_MCLK:
401 pnctrl_info = &audio_lpass_mclk.pnctrl_info;
402 break;
403 case LPASS_MCLK2:
404 pnctrl_info = &audio_lpass_mclk2.pnctrl_info;
405 break;
406 default:
Meng Wang417e5712017-03-07 09:44:05 +0800407 dev_err(dev, "%s Not a valid MUX ID: %d\n",
Banajit Goswamide8271c2017-01-18 00:28:59 -0800408 __func__, mux);
409 return -EINVAL;
410 }
Banajit Goswamide8271c2017-01-18 00:28:59 -0800411
412 if (pnctrl_info->pinctrl) {
Meng Wang417e5712017-03-07 09:44:05 +0800413 dev_dbg(dev, "%s: already requested before\n",
Banajit Goswamide8271c2017-01-18 00:28:59 -0800414 __func__);
415 return -EINVAL;
416 }
417
Meng Wang417e5712017-03-07 09:44:05 +0800418 pinctrl = devm_pinctrl_get(dev);
Banajit Goswamide8271c2017-01-18 00:28:59 -0800419 if (IS_ERR_OR_NULL(pinctrl)) {
Meng Wang417e5712017-03-07 09:44:05 +0800420 dev_dbg(dev, "%s: Unable to get pinctrl handle\n",
Banajit Goswamide8271c2017-01-18 00:28:59 -0800421 __func__);
422 return -EINVAL;
423 }
424 pnctrl_info->pinctrl = pinctrl;
425 /* get all state handles from Device Tree */
426 pnctrl_info->sleep = pinctrl_lookup_state(pinctrl, "sleep");
427 if (IS_ERR(pnctrl_info->sleep)) {
Meng Wang417e5712017-03-07 09:44:05 +0800428 dev_err(dev, "%s: could not get sleep pinstate\n",
Banajit Goswamide8271c2017-01-18 00:28:59 -0800429 __func__);
430 goto err;
431 }
432 pnctrl_info->active = pinctrl_lookup_state(pinctrl, "active");
433 if (IS_ERR(pnctrl_info->active)) {
Meng Wang417e5712017-03-07 09:44:05 +0800434 dev_err(dev, "%s: could not get active pinstate\n",
Banajit Goswamide8271c2017-01-18 00:28:59 -0800435 __func__);
436 goto err;
437 }
438 /* Reset the TLMM pins to a default state */
439 ret = pinctrl_select_state(pnctrl_info->pinctrl,
440 pnctrl_info->sleep);
441 if (ret) {
Meng Wang417e5712017-03-07 09:44:05 +0800442 dev_err(dev, "%s: Disable TLMM pins failed with %d\n",
Banajit Goswamide8271c2017-01-18 00:28:59 -0800443 __func__, ret);
444 goto err;
445 }
Meng Wang417e5712017-03-07 09:44:05 +0800446
447 ret = of_property_read_u32(dev->of_node, "qcom,mclk-clk-reg", &reg);
448 if (ret < 0) {
449 dev_dbg(dev, "%s: miss mclk reg\n", __func__);
450 } else {
451 pnctrl_info->base = ioremap(reg, sizeof(u32));
452 if (pnctrl_info->base == NULL) {
453 dev_err(dev, "%s ioremap failed\n", __func__);
454 goto err;
455 }
456 }
457
Banajit Goswamide8271c2017-01-18 00:28:59 -0800458 return 0;
459
460err:
461 devm_pinctrl_put(pnctrl_info->pinctrl);
462 return -EINVAL;
463}
464
465static int audio_ref_clk_probe(struct platform_device *pdev)
466{
467 int clk_gpio;
468 int ret;
469 u32 mclk_freq;
470 struct clk *audio_clk;
471 struct device *dev = &pdev->dev;
472 int i;
473 struct clk_onecell_data *clk_data;
474
475 ret = of_property_read_u32(pdev->dev.of_node,
476 "qcom,codec-mclk-clk-freq",
477 &mclk_freq);
478 if (!ret) {
479 lpass_mclk.clk_freq_in_hz = mclk_freq;
480
481 ret = audio_get_pinctrl(pdev, LPASS_MCLK);
482 if (ret)
483 dev_err(&pdev->dev, "%s: Parsing pinctrl %s failed\n",
484 __func__, "LPASS_MCLK");
485 ret = audio_get_pinctrl(pdev, LPASS_MCLK2);
486 if (ret)
487 dev_dbg(&pdev->dev, "%s: Parsing pinctrl %s failed\n",
488 __func__, "LPASS_MCLK2");
489 }
490
491 clk_gpio = of_get_named_gpio(pdev->dev.of_node,
492 "qcom,audio-ref-clk-gpio", 0);
493 if (clk_gpio > 0) {
494 ret = gpio_request(clk_gpio, "EXT_CLK");
495 if (ret) {
496 dev_err(&pdev->dev,
497 "Request ext clk gpio failed %d, err:%d\n",
498 clk_gpio, ret);
499 goto err;
500 }
501 if (of_property_read_bool(pdev->dev.of_node,
502 "qcom,node_has_rpm_clock")) {
503 audio_pmi_clk.gpio = clk_gpio;
504 } else
505 audio_ap_clk.gpio = clk_gpio;
506
507 }
508
509 ret = audio_get_pinctrl(pdev, AP_CLK2);
510 if (ret)
511 dev_dbg(&pdev->dev, "%s: Parsing pinctrl failed\n",
512 __func__);
513
514 clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
515 if (!clk_data)
516 goto err_gpio;
517
Yeleswarapu Nagaradhesh3f051562017-01-17 16:05:34 +0530518
519 clk_gpio = of_get_named_gpio(pdev->dev.of_node,
520 "qcom,audio-ref-clk-gpio", 0);
521 if (clk_gpio > 0) {
Banajit Goswamie5daf7b2017-02-25 04:00:43 -0800522 clk_data->clk_num = ARRAY_SIZE(audio_msm_hws);
523 clk_data->clks = devm_kzalloc(&pdev->dev,
524 clk_data->clk_num *
525 sizeof(struct clk *),
526 GFP_KERNEL);
527 if (!clk_data->clks)
528 goto err_clk;
529
Yeleswarapu Nagaradhesh3f051562017-01-17 16:05:34 +0530530 for (i = 0; i < ARRAY_SIZE(audio_msm_hws); i++) {
531 audio_clk = devm_clk_register(dev, audio_msm_hws[i]);
532 if (IS_ERR(audio_clk)) {
533 dev_err(&pdev->dev,
534 "%s: ref clock: %d register failed\n",
535 __func__, i);
536 return PTR_ERR(audio_clk);
537 }
538 clk_data->clks[i] = audio_clk;
Banajit Goswamide8271c2017-01-18 00:28:59 -0800539 }
Yeleswarapu Nagaradhesh3f051562017-01-17 16:05:34 +0530540 } else {
Banajit Goswamie5daf7b2017-02-25 04:00:43 -0800541 clk_data->clk_num = ARRAY_SIZE(audio_msm_hws1);
542 clk_data->clks = devm_kzalloc(&pdev->dev,
543 clk_data->clk_num *
544 sizeof(struct clk *),
545 GFP_KERNEL);
546 if (!clk_data->clks)
547 goto err_clk;
548
Yeleswarapu Nagaradhesh3f051562017-01-17 16:05:34 +0530549 for (i = 0; i < ARRAY_SIZE(audio_msm_hws1); i++) {
550 audio_clk = devm_clk_register(dev, audio_msm_hws1[i]);
551 if (IS_ERR(audio_clk)) {
552 dev_err(&pdev->dev,
553 "%s: ref clock: %d register failed\n",
554 __func__, i);
555 return PTR_ERR(audio_clk);
556 }
557 clk_data->clks[i] = audio_clk;
558 }
Banajit Goswamide8271c2017-01-18 00:28:59 -0800559 }
560
561 ret = of_clk_add_provider(pdev->dev.of_node,
562 of_clk_src_onecell_get, clk_data);
563 if (ret) {
564 dev_err(&pdev->dev, "%s: audio ref clock register failed\n",
565 __func__);
566 goto err_gpio;
567 }
568
569 return 0;
570
571err_clk:
572 if (clk_data)
573 devm_kfree(&pdev->dev, clk_data->clks);
574 devm_kfree(&pdev->dev, clk_data);
575err_gpio:
576 gpio_free(clk_gpio);
577
578err:
579 return ret;
580}
581
582static int audio_ref_clk_remove(struct platform_device *pdev)
583{
584 struct pinctrl_info *pnctrl_info = &audio_ap_clk2.pnctrl_info;
585
586 if (audio_pmi_clk.gpio > 0)
587 gpio_free(audio_pmi_clk.gpio);
588 else if (audio_ap_clk.gpio > 0)
589 gpio_free(audio_ap_clk.gpio);
590
591 if (pnctrl_info->pinctrl) {
592 devm_pinctrl_put(pnctrl_info->pinctrl);
593 pnctrl_info->pinctrl = NULL;
594 }
595
596 return 0;
597}
598
599static const struct of_device_id audio_ref_clk_match[] = {
600 {.compatible = "qcom,audio-ref-clk"},
601 {}
602};
603MODULE_DEVICE_TABLE(of, audio_ref_clk_match);
604
605static struct platform_driver audio_ref_clk_driver = {
606 .driver = {
607 .name = "audio-ref-clk",
608 .owner = THIS_MODULE,
609 .of_match_table = audio_ref_clk_match,
610 },
611 .probe = audio_ref_clk_probe,
612 .remove = audio_ref_clk_remove,
613};
614
Karthikeyan Mani858132b2017-06-27 20:03:08 -0700615int audio_ref_clk_platform_init(void)
Banajit Goswamide8271c2017-01-18 00:28:59 -0800616{
617 return platform_driver_register(&audio_ref_clk_driver);
618}
Banajit Goswamide8271c2017-01-18 00:28:59 -0800619
Karthikeyan Mani858132b2017-06-27 20:03:08 -0700620void audio_ref_clk_platform_exit(void)
Banajit Goswamide8271c2017-01-18 00:28:59 -0800621{
622 platform_driver_unregister(&audio_ref_clk_driver);
623}
Banajit Goswamide8271c2017-01-18 00:28:59 -0800624
625MODULE_DESCRIPTION("Audio Ref Up Clock module platform driver");
626MODULE_LICENSE("GPL v2");