blob: 9c32b23322bdfbc35d7d3723a6e51cc2c2bf4ba8 [file] [log] [blame]
Colin Cross7056d422010-04-22 20:30:13 -07001/*
Colin Cross7056d422010-04-22 20:30:13 -07002 * Copyright (C) 2010 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@google.com>
6 * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/types.h>
22#include <linux/sched.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/init.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28#include <linux/io.h>
Colin Cross1eb2ecf2010-08-05 17:40:39 -070029#include <linux/suspend.h>
Colin Cross7056d422010-04-22 20:30:13 -070030
Colin Cross7056d422010-04-22 20:30:13 -070031static struct cpufreq_frequency_table freq_table[] = {
Viresh Kumar5d690302013-05-14 19:08:50 +053032 { .frequency = 216000 },
33 { .frequency = 312000 },
34 { .frequency = 456000 },
35 { .frequency = 608000 },
36 { .frequency = 760000 },
37 { .frequency = 816000 },
38 { .frequency = 912000 },
39 { .frequency = 1000000 },
40 { .frequency = CPUFREQ_TABLE_END },
Colin Cross7056d422010-04-22 20:30:13 -070041};
42
43#define NUM_CPUS 2
44
45static struct clk *cpu_clk;
Stephen Warrence32dda2012-09-10 17:05:01 -060046static struct clk *pll_x_clk;
47static struct clk *pll_p_clk;
Colin Cross7a281282010-11-22 18:54:36 -080048static struct clk *emc_clk;
Colin Cross7056d422010-04-22 20:30:13 -070049
50static unsigned long target_cpu_speed[NUM_CPUS];
Colin Cross1eb2ecf2010-08-05 17:40:39 -070051static DEFINE_MUTEX(tegra_cpu_lock);
52static bool is_suspended;
Colin Cross7056d422010-04-22 20:30:13 -070053
Olof Johansson6686c732011-10-09 21:57:04 -070054static unsigned int tegra_getspeed(unsigned int cpu)
Colin Cross7056d422010-04-22 20:30:13 -070055{
56 unsigned long rate;
57
58 if (cpu >= NUM_CPUS)
59 return 0;
60
61 rate = clk_get_rate(cpu_clk) / 1000;
62 return rate;
63}
64
Stephen Warrence32dda2012-09-10 17:05:01 -060065static int tegra_cpu_clk_set_rate(unsigned long rate)
66{
67 int ret;
68
69 /*
70 * Take an extra reference to the main pll so it doesn't turn
71 * off when we move the cpu off of it
72 */
73 clk_prepare_enable(pll_x_clk);
74
75 ret = clk_set_parent(cpu_clk, pll_p_clk);
76 if (ret) {
77 pr_err("Failed to switch cpu to clock pll_p\n");
78 goto out;
79 }
80
81 if (rate == clk_get_rate(pll_p_clk))
82 goto out;
83
84 ret = clk_set_rate(pll_x_clk, rate);
85 if (ret) {
86 pr_err("Failed to change pll_x to %lu\n", rate);
87 goto out;
88 }
89
90 ret = clk_set_parent(cpu_clk, pll_x_clk);
91 if (ret) {
92 pr_err("Failed to switch cpu to clock pll_x\n");
93 goto out;
94 }
95
96out:
97 clk_disable_unprepare(pll_x_clk);
98 return ret;
99}
100
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530101static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
102 unsigned long rate)
Colin Cross7056d422010-04-22 20:30:13 -0700103{
Colin Cross7056d422010-04-22 20:30:13 -0700104 int ret = 0;
105 struct cpufreq_freqs freqs;
106
Colin Cross7056d422010-04-22 20:30:13 -0700107 freqs.old = tegra_getspeed(0);
108 freqs.new = rate;
109
110 if (freqs.old == freqs.new)
111 return ret;
112
Colin Cross7a281282010-11-22 18:54:36 -0800113 /*
114 * Vote on memory bus frequency based on cpu frequency
115 * This sets the minimum frequency, display or avp may request higher
116 */
117 if (rate >= 816000)
118 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
119 else if (rate >= 456000)
120 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
121 else
122 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
123
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530124 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
Colin Cross7056d422010-04-22 20:30:13 -0700125
126#ifdef CONFIG_CPU_FREQ_DEBUG
127 printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
128 freqs.old, freqs.new);
129#endif
130
Stephen Warrence32dda2012-09-10 17:05:01 -0600131 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
Colin Cross7056d422010-04-22 20:30:13 -0700132 if (ret) {
133 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
134 freqs.new);
Viresh Kumarf56cc992013-06-19 11:18:20 +0530135 freqs.new = freqs.old;
Colin Cross7056d422010-04-22 20:30:13 -0700136 }
137
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530138 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
Colin Cross7056d422010-04-22 20:30:13 -0700139
Viresh Kumarf56cc992013-06-19 11:18:20 +0530140 return ret;
Colin Cross7056d422010-04-22 20:30:13 -0700141}
142
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700143static unsigned long tegra_cpu_highest_speed(void)
144{
145 unsigned long rate = 0;
146 int i;
147
148 for_each_online_cpu(i)
149 rate = max(rate, target_cpu_speed[i]);
150 return rate;
151}
152
Colin Cross7056d422010-04-22 20:30:13 -0700153static int tegra_target(struct cpufreq_policy *policy,
154 unsigned int target_freq,
155 unsigned int relation)
156{
Olof Johanssonfdb684a2011-10-09 21:31:23 -0700157 unsigned int idx;
Colin Cross7056d422010-04-22 20:30:13 -0700158 unsigned int freq;
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700159 int ret = 0;
160
161 mutex_lock(&tegra_cpu_lock);
162
163 if (is_suspended) {
164 ret = -EBUSY;
165 goto out;
166 }
Colin Cross7056d422010-04-22 20:30:13 -0700167
168 cpufreq_frequency_table_target(policy, freq_table, target_freq,
169 relation, &idx);
170
171 freq = freq_table[idx].frequency;
172
173 target_cpu_speed[policy->cpu] = freq;
174
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530175 ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700176
177out:
178 mutex_unlock(&tegra_cpu_lock);
179 return ret;
Colin Cross7056d422010-04-22 20:30:13 -0700180}
181
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700182static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
183 void *dummy)
184{
185 mutex_lock(&tegra_cpu_lock);
186 if (event == PM_SUSPEND_PREPARE) {
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530187 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700188 is_suspended = true;
189 pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
190 freq_table[0].frequency);
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530191 tegra_update_cpu_speed(policy, freq_table[0].frequency);
192 cpufreq_cpu_put(policy);
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700193 } else if (event == PM_POST_SUSPEND) {
194 is_suspended = false;
195 }
196 mutex_unlock(&tegra_cpu_lock);
197
198 return NOTIFY_OK;
199}
200
201static struct notifier_block tegra_cpu_pm_notifier = {
202 .notifier_call = tegra_pm_notify,
203};
204
Colin Cross7056d422010-04-22 20:30:13 -0700205static int tegra_cpu_init(struct cpufreq_policy *policy)
206{
207 if (policy->cpu >= NUM_CPUS)
208 return -EINVAL;
209
Prashant Gaikwad6a5278d2012-06-05 09:59:35 +0530210 clk_prepare_enable(emc_clk);
211 clk_prepare_enable(cpu_clk);
Colin Cross89a5fb82010-10-20 17:47:59 -0700212
Viresh Kumar23387992013-09-16 18:56:39 +0530213 cpufreq_table_validate_and_show(policy, freq_table);
Viresh Kumar21c895c2013-10-03 20:29:05 +0530214 target_cpu_speed[policy->cpu] = tegra_getspeed(policy->cpu);
Colin Cross7056d422010-04-22 20:30:13 -0700215
216 /* FIXME: what's the actual transition time? */
217 policy->cpuinfo.transition_latency = 300 * 1000;
218
Viresh Kumar16a44f82013-02-01 06:40:00 +0000219 cpumask_copy(policy->cpus, cpu_possible_mask);
Colin Cross7056d422010-04-22 20:30:13 -0700220
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700221 if (policy->cpu == 0)
222 register_pm_notifier(&tegra_cpu_pm_notifier);
223
Colin Cross7056d422010-04-22 20:30:13 -0700224 return 0;
225}
226
227static int tegra_cpu_exit(struct cpufreq_policy *policy)
228{
Viresh Kumar2e6a5c802013-09-16 18:56:40 +0530229 cpufreq_frequency_table_put_attr(policy->cpu);
Prashant Gaikwad6a5278d2012-06-05 09:59:35 +0530230 clk_disable_unprepare(emc_clk);
Colin Cross7056d422010-04-22 20:30:13 -0700231 return 0;
232}
233
Colin Cross7056d422010-04-22 20:30:13 -0700234static struct cpufreq_driver tegra_cpufreq_driver = {
Viresh Kumar8e08cf02013-10-03 20:28:29 +0530235 .verify = cpufreq_generic_frequency_table_verify,
Colin Cross7056d422010-04-22 20:30:13 -0700236 .target = tegra_target,
237 .get = tegra_getspeed,
238 .init = tegra_cpu_init,
239 .exit = tegra_cpu_exit,
240 .name = "tegra",
Viresh Kumar8e08cf02013-10-03 20:28:29 +0530241 .attr = cpufreq_generic_attr,
Colin Cross7056d422010-04-22 20:30:13 -0700242};
243
244static int __init tegra_cpufreq_init(void)
245{
Joseph Lob192b912013-08-23 09:43:58 +0800246 cpu_clk = clk_get_sys(NULL, "cclk");
Richard Zhaoc26cefd2012-12-21 00:09:55 +0000247 if (IS_ERR(cpu_clk))
248 return PTR_ERR(cpu_clk);
249
250 pll_x_clk = clk_get_sys(NULL, "pll_x");
251 if (IS_ERR(pll_x_clk))
252 return PTR_ERR(pll_x_clk);
253
Joseph Lob192b912013-08-23 09:43:58 +0800254 pll_p_clk = clk_get_sys(NULL, "pll_p");
Richard Zhaoc26cefd2012-12-21 00:09:55 +0000255 if (IS_ERR(pll_p_clk))
256 return PTR_ERR(pll_p_clk);
257
258 emc_clk = clk_get_sys("cpu", "emc");
259 if (IS_ERR(emc_clk)) {
260 clk_put(cpu_clk);
261 return PTR_ERR(emc_clk);
262 }
263
Colin Cross7056d422010-04-22 20:30:13 -0700264 return cpufreq_register_driver(&tegra_cpufreq_driver);
265}
266
267static void __exit tegra_cpufreq_exit(void)
268{
269 cpufreq_unregister_driver(&tegra_cpufreq_driver);
Richard Zhaoc26cefd2012-12-21 00:09:55 +0000270 clk_put(emc_clk);
271 clk_put(cpu_clk);
Colin Cross7056d422010-04-22 20:30:13 -0700272}
273
274
275MODULE_AUTHOR("Colin Cross <ccross@android.com>");
276MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
277MODULE_LICENSE("GPL");
278module_init(tegra_cpufreq_init);
279module_exit(tegra_cpufreq_exit);